On 24/04/07 17:01 +0530, Pradyumna Sampath wrote:
> Hi Everyone,
>
> I have been trying to get the linux-2.6.20-rt3 for arch/powerpc to
> boot on my lite5200b. Here are the things that I have tried so far. I
> have a custom board based on the lite5200b and then the evaluation
> board too.
>
> - I
On Tue, 2007-04-24 at 20:34 -0700, Siva Prasad wrote:
> Thanks Ben.
>
> I managed to fix this. I am working on how best we can rewrite the self
> modifying code we have for create_hpte routine. I would prefer to read
> from SDR1, than to hardcode (or self modify the code) the way it is done
> now.
Thanks Ben.
I managed to fix this. I am working on how best we can rewrite the self
modifying code we have for create_hpte routine. I would prefer to read
from SDR1, than to hardcode (or self modify the code) the way it is done
now.
Feel free to let me know what you think.
Thanks
Siva
-Ori
Hi,
What is the primary difference between Ramdisk and NFS with respect to
the wait_queue's?
If I use ramdisk, every thing works fine, but with NFS (or you may read
as 'no ramdisk') kernel/sched.c:__wake_up_common() routines has a
problem. Basically the value of "&q->task_list->next" is out of ou
> + .activate = FB_ACTIVATE_NOW,
> + .height = 99, /* in mm of NEC NL6448BC20-08 on ML300 */
> + .width =132 /* in mm of NEC NL6448BC20-08 on ML300 */
> +};
The size looks very specific to a particular display hardware. I guess
when the driver gets conve
On 4/24/07, Andrei Konovalov <[EMAIL PROTECTED]> wrote:
> Add support for the video controller IP block included into Xilinx ML300 and
> ML403 reference designs.
>
> Signed-off-by: Andrei Konovalov <[EMAIL PROTECTED]>
> ---
>
> This patch relies on the "Patchset to establish sanity in Xilinx Virtex
On 4/24/07, Mohammad Sadegh Sadri <[EMAIL PROTECTED]> wrote:
>
> Then in mailing list I saw some where that AVNET mini-modules are using a
> version of FX12 FPGA which has problem with PPC caches and as the solution
> the caches should be off.
>
> Does the kernel always turns on the caches? Or If
AFAICT, the TEMAC device has not been registered on the platform bus.
You should add this stuff to arch/ppc/syslib/virtex_devices.c
(if you use the recent patches by Grant Likely).
xtemac_g.c is not used in 2.6 TEMAC driver(s I have seen).
Thanks,
Andrei
Mirek23 wrote:
> Thanks for the suggestio
Thanks for the suggestions. I have changed the command line argument:
console:ttl0 -> ttyUL0 and kernel has booted up to the point to mount the
root file system.
I have set up the kernel to mount the root file systems via the nfs. I have
started the nfs server on the remote pc.
Unfortunately t
Then in mailing list I saw some where that AVNET mini-modules are using a
version of FX12 FPGA which has problem with PPC caches and as the solution the
caches should be off.
Does the kernel always turns on the caches? Or If I choose in the base system
builder to not to use caches, the kernel
> Message: 1
> Date: Tue, 24 Apr 2007 17:58:13 +0400
> From: Andrei Konovalov <[EMAIL PROTECTED]>
> Subject: Re: Using Xilinx Framebuffer on ML405 and 2.6.20.4
> To: Grant Likely <[EMAIL PROTECTED]>
> Cc: linuxppc-embedded@ozlabs.org
> Message-ID: <[EMAIL PROTECTED]>
> Content-Type: text/plain; cha
On 4/24/07, Mohammad Sadegh Sadri <[EMAIL PROTECTED]> wrote:
>
>
> what about the cache?
> Does the current kernel use the cache efficiently?
Yes, the caches work and are turned on by the kernel.
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
[EMAIL PROTECTED]
(403) 399-0195
On 4/24/07, Andrei Konovalov <[EMAIL PROTECTED]> wrote:
> Hi Grant,
>
> I've discovered the IBM Microdrive fits perfectly into the ML403 CF slot :)
> So I've repeated the bonnie++ stress test on ML403 with the hard disk.
> The log is below.
> The test completed OK, but there was one message from th
what about the cache?
Does the current kernel use the cache efficiently?
> Date: Tue, 24 Apr 2007 07:55:48 -0600
> From: [EMAIL PROTECTED]
> To: [EMAIL PROTECTED]
> Subject: Re: 2.6 Kernel , Xilinx Virtex and PPC 405 On chip memory
> controllers ( DSOC
Andrei Konovalov wrote:
> Add support for the video controller IP block included into Xilinx
> ML300 and
> ML403 reference designs.
>
> Signed-off-by: Andrei Konovalov <[EMAIL PROTECTED]>
> ---
>
> This patch relies on the "Patchset to establish sanity in Xilinx
> Virtex support" by Gran Likely t
On 4/24/07, Mohammad Sadegh Sadri <[EMAIL PROTECTED]> wrote:
>
> suppose that in my base system I have included 8kbytes of memory for DS OCM
> and 8K for IS OCM,
> I have generated the proper xparameters.h and copied it into kernel
>
> Now I want to know if kernel will use this portion of memory d
Andrei Konovalov wrote:
> Grant Likely wrote:
>> On 4/24/07, Peter Mendham <[EMAIL PROTECTED]> wrote:
>>> Dear all,
>>>
>>> I am wanting to use the Xilinx TFT controller from the ML403/5
>>> reference
>>> project (probably from ML300 as well) under a 2.6.20.4 kernel. I have
>>> Grant Likely's pat
Add support for the video controller IP block included into Xilinx ML300 and
ML403 reference designs.
Signed-off-by: Andrei Konovalov <[EMAIL PROTECTED]>
---
This patch relies on the "Patchset to establish sanity in Xilinx Virtex
support" by Gran Likely to have
the frame buffer device registere
Grant Likely wrote:
> On 4/24/07, Peter Mendham <[EMAIL PROTECTED]> wrote:
>> Dear all,
>>
>> I am wanting to use the Xilinx TFT controller from the ML403/5 reference
>> project (probably from ML300 as well) under a 2.6.20.4 kernel. I have
>> Grant Likely's patchset applied in which there is a pla
Grant Likely wrote:
> Heh, I've got a driver. I just haven't published it yet. Give me a
> few days...
Fantastic. I'm happy to be on the front line of alpha testing if that's
any help.
No worries with a few day's delay though, I'm trying to fit the TFT
controller into with my design with a T
Thanks for the suggestions. I have changed the command line argument:
console:ttl0 -> ttyUL0 and kernel has booted up to the point to mount the
root file system.
I have set up the kernel to mount the root file systems via the nfs. I have
started the nfs server on the remote pc.
Unfortunately the
On 4/24/07, Peter Mendham <[EMAIL PROTECTED]> wrote:
> Dear all,
>
> I am wanting to use the Xilinx TFT controller from the ML403/5 reference
> project (probably from ML300 as well) under a 2.6.20.4 kernel. I have
> Grant Likely's patchset applied in which there is a platform device
> entry for th
Hi all,
Just a very simple question about the 2.6 kerenl,
suppose that in my base system I have included 8kbytes of memory for DS OCM and
8K for IS OCM,
I have generated the proper xparameters.h and copied it into kernel
Now I want to know if kernel will use this portion of memory during it's
Hi Everyone,
I have been trying to get the linux-2.6.20-rt3 for arch/powerpc to
boot on my lite5200b. Here are the things that I have tried so far. I
have a custom board based on the lite5200b and then the evaluation
board too.
- I have a working 2.6.16-rt29 kernel compiled using ARCH=ppc for bot
On Tue, 2007-04-24 at 07:55 +0200, Heiko Schocher wrote:
> Hello,
>
> I have a MPC885 and a running 2.6.16 kernel on it. I use the CPU15
> Errata Patch from
> (http://ozlabs.org/pipermail/linuxppc-dev/2007-April/033789.html)
>
> Now if a lwarx/stwcx insn crossing a page boundary, the CPU hangs in
Dear all,
I am wanting to use the Xilinx TFT controller from the ML403/5 reference
project (probably from ML300 as well) under a 2.6.20.4 kernel. I have
Grant Likely's patchset applied in which there is a platform device
entry for the framebuffer. Does anyone know if there is mainline
suppor
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