[Lldb-commits] [PATCH] D157000: [lldb][AArch64] Check SIMD save/restore in SVE SIMD test

omjavaid accepted this revision. omjavaid added inline comments. This revision is now accepted and ready to land. Comment at: lldb/test/API/commands/register/register/aarch64_sve_simd_registers/main.c:43 +void write_simd_regs_expr() { +#define WRITE_SIMD(NUM)

[Lldb-commits] [PATCH] D157488: [lldb][AArch64] Add testing of save/restore for Linux MTE control register

omjavaid added a comment. This looks fine but instead of adding a new test cant we add MTE control register tests to already available MTE tests? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157488/new/ https://reviews.llvm.org/D157488 _

[Lldb-commits] [PATCH] D156687: [lldb][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

omjavaid added a comment. I have a feeling that expressions are becoming an expensive operation with amount of data we need to move back and forth between various buffers. Is there a way we can optimise this may be write register directly from source buffer. Also how much minimum data we need t

[Lldb-commits] [PATCH] D156687: [lldb][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

omjavaid added a comment. > I don't know about expensive literally but I did wonder if we could rely on > the NativeRegisterContextLinux_arm64 buffers not being modified while the > expression runs. Then do what I think you mean which is just flush them all > to the process. > > I'll need to wo

[Lldb-commits] [PATCH] D156687: [lldb][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

omjavaid added a comment. In D156687#4628743 , @DavidSpickett wrote: > First thing to note is that WriteRegister also behaves this way, but there it > is more appropriate because it updates only part of the buffer before writing > it out in its entiret

[Lldb-commits] [PATCH] D156687: [lldb][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

omjavaid added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:573 - ::memcpy(dst, GetGPRBuffer(), GetGPRBufferSize()); - dst += GetGPRBufferSize(); + dst = AddSavedRegisters(dst, SavedRegistersKind::GPR, GetGPRBuffer(), +

[Lldb-commits] [PATCH] D157845: [lldb][AArch64] Remove bool return from UpdateARM64SVERegistersInfos

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. Thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157845/new/ https://reviews.llvm.org/D157845

[Lldb-commits] [PATCH] D156687: [lldb][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

omjavaid added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:539 Status error; - uint32_t reg_data_byte_size = GetGPRBufferSize(); + uint32_t reg_data_byte_size = sizeof(SavedRegistersKind) + GetGPRBufferSize(); erro

[Lldb-commits] [PATCH] D156687: [lldb][AArch64] Add kind marker to ReadAll/WriteALLRegisterValues data

omjavaid added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:503 +enum SavedRegistersKind : uint32_t { + GPR, + SVE, // Used for SVE and SSVE. Consider renaming this to RegisterSetName or RegisterSetType

[Lldb-commits] [PATCH] D157883: [lldb][AArch64] Add SME's Array Storage (ZA) and streaming vector length (SVG) registers

omjavaid requested changes to this revision. omjavaid added a comment. This revision now requires changes to proceed. The patch looks to implement all stuff needed at once lets break it down into three patches instead: 1. First patch that just adds SME register set and does not implement Regist

[Lldb-commits] [PATCH] D157846: [lldb][AArch64] Add SME's SVE register state to TestArm64DynamicRegsets

omjavaid added a comment. Can you add more description to this patch. at the moment reading it without SME context in mind does not provide enough information to figure out what we are doing. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157846/ne

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

omjavaid added a comment. This patch requires rebasing does not apply cleanly on top of its parent. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D159505/new/ https://reviews.llvm.org/D159505 ___ lldb-com

[Lldb-commits] [PATCH] D157846: [lldb][AArch64] Add SME's tests for SVE register state to TestArm64DynamicRegsets

omjavaid added a comment. In this test can we figure out whether SVE was read from Streaming mode or normal SVE mode?? and if yes may be add a check for that. Comment at: lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py:156 + +

[Lldb-commits] [PATCH] D157846: [lldb][AArch64] Add SME's tests for SVE register state to TestArm64DynamicRegsets

omjavaid added a comment. In D157846#4644241 , @DavidSpickett wrote: >> In this test can we figure out whether SVE was read from Streaming mode or >> normal SVE mode?? and if yes may be add a check for that. > > Not sure what you mean. > > If you mean:

[Lldb-commits] [PATCH] D159502: [lldb][AArch64] Add SME's Array Storage (ZA) register

omjavaid added a comment. This looks good overall thanks for doing the patch split makes the review way less overwhelming. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:342 + // header itself. + m_za_ptrace_payload.resize(((m_za_

[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

omjavaid added a comment. Why do we have svg and za in different register sets? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D159503/new/ https://reviews.llvm.org/D159503 ___ lldb-commits mailing list ll

[Lldb-commits] [PATCH] D159504: [lldb][AArch64] Implement resizing of SME's ZA register

omjavaid added inline comments. Comment at: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h:42 void UpdateARM64SVERegistersInfos(uint64_t vg); + void UpdateARM64SMERegistersInfos(uint64_t vg); }; svg Repository: rG LLVM Github Monorepo

[Lldb-commits] [PATCH] D159504: [lldb][AArch64] Implement resizing of SME's ZA register

omjavaid added a comment. This apparently requires a rebase now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D159504/new/ https://reviews.llvm.org/D159504 ___ lldb-commits mailing list lldb-commits@list

[Lldb-commits] [PATCH] D159502: [lldb][AArch64] Add SME's Array Storage (ZA) register

omjavaid added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:566 TLS, + ZA, + // SME pseudo registers are read only. ZA -> SME? Comment at: lldb/source/Plugins/Process/Utility/Register

[Lldb-commits] [PATCH] D159502: [lldb][AArch64] Add SME's Array Storage (ZA) register

omjavaid added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:597 + // Here this means, does the system have ZA, not whether it is active. + if (GetRegisterInfo().IsZAEnabled()) { +error = ReadZAHeader(); ---

[Lldb-commits] [PATCH] D159502: [lldb][AArch64] Add SME's Array Storage (ZA) register

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. This is LGTM. Thanks for your patience. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D159502/new/ https://reviews.llvm.org/D159502

[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

omjavaid added a comment. This looks find just couple of nits inline. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:354 + + // ZA is part of the SME set but uses a seperate member buffer for storage. + // Therefore its effective

[Lldb-commits] [PATCH] D159504: [lldb][AArch64] Implement resizing of SME's ZA register

omjavaid added inline comments. Comment at: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp:839 + +void GDBRemoteDynamicRegisterInfo::UpdateARM64SMERegistersInfos(uint64_t svg) { + for (auto ® : m_regs) { can we combine UpdateARM64SVERegiste

[Lldb-commits] [PATCH] D159503: [lldb][AArch64] Add SME streaming vector length pseduo register

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. This is LGTM as you suggested pending child reviews. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D159503/new/ https://reviews.llvm.org/D159

[Lldb-commits] [PATCH] D159504: [lldb][AArch64] Implement resizing of SME's ZA register

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. This look good Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D159504/new/ https://reviews.llvm.org/D159504 _

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

omjavaid added inline comments. Comment at: lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py:201 +self.runCmd("register write za '{}'".format(za_value)) +self.expect("register read za", substrs=[za_value]) ---

[Lldb-commits] [PATCH] D159505: [lldb][AArch64] Add testing for SME's ZA and SVG registers

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. this looks good Comment at: lldb/test/API/commands/register/register/aarch64_za_register/za_dynamic_resize/main.c:12 +// (this is just how ptrace works). +// * Writing

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

omjavaid added a comment. Are Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:1181 + + return {}; +} Shouldnt we build a relevant error message here incase ReadSMEControl fails on ReadZAHeader Comment at:

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. This is good too. Thanks!!! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154927/new/ https://reviews.llvm.org/D154927

[Lldb-commits] [PATCH] D158500: [lldb][AArch64] Linux corefile support for SME

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. This looks good with just one nit above. Comment at: lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp:74 - if (m_register_info_up->IsSVEEnabled

[Lldb-commits] [PATCH] D148752: lldb: Fix usage of sve functions on arm64

omjavaid added a comment. HI Manoj Which linux distro are you using for your cross build? I am wondering which version of gcc (aarch64-linux-gnu) are you using for your cross compilation build. I believe sve headers are not defined in older versions of gcc or its packaged sysroot causing cross

[Lldb-commits] [PATCH] D148752: lldb: Fix usage of sve functions on arm64

omjavaid added a comment. In D148752#4283899 , @manojgupta wrote: > I am building on ChromeOS. We only have headers from linux kernel 4.14 > available in our build system (The actual running kernel could be a higher > version). > But given these functi

[Lldb-commits] [PATCH] D149625: [lldb] Refactor SBFileSpec::GetDirectory

omjavaid reopened this revision. omjavaid added a comment. This revision is now accepted and ready to land. This introduced test failures on windows lldb-aarch64-windows buildbot. lldb-api :: functionalities/process_save_core/TestProcessSaveCore.py lldb-api :: python_api/symbol-context/TestSy

[Lldb-commits] [PATCH] D149625: [lldb] Refactor SBFileSpec::GetDirectory

This revision was automatically updated to reflect the committed changes. Closed by commit rG58e6caaba1cf: Revert "[lldb] Refactor SBFileSpec::GetDirectory" (authored by omjavaid). Changed prior to commit: https://reviews.llvm.org/D149625?vs=518782&id=522285#toc Repository: rG LLVM Github Mo

[Lldb-commits] [PATCH] D152519: [lldb][AArch64] Add Scalable Matrix Extension option to QEMU launch script

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. This looks good. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152519/new/ https://reviews.llvm.org/D152519 ___

[Lldb-commits] [PATCH] D152516: [lldb][AArch64] Add thread local storage tpidr register

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. This looks good to me, just a minor nit above. I have not run the test myself. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:286

[Lldb-commits] [PATCH] D154705: [lldb][AArch64] Fix flakiness in TestSVEThreadedDynamic

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. Sounds ok to me. We can always fix it if starts to cause trouble. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154705/new/ https://reviews.

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

omjavaid added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:279 +assert(offset < GetTLSSize()); +src = (uint8_t *)GetTLS() + offset; } else if (IsSVE(reg)) { GetTLS could be GetTLSBuffer similar t

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

omjavaid added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:325 + } else if (IsSME(reg)) { +// This is a pseduo so it never fails. +ReadSMEControl(); typo: pseudo register? Comme

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

omjavaid added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:222 + // In SIMD or Full mode, the data comes from the SVE regset. In streaming + // mode, it also comes from that set, so we have to switch temporarily.

[Lldb-commits] [PATCH] D154930: [lldb][AArch64] Add the tpidr2 TLS register that comes with SME

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. This looks good just a minor suggestion inline. Comment at: lldb/test/API/linux/aarch64/tls_registers/TestAArch64LinuxTLSRegisters.py:84 + +self.check_tls_reg("t

[Lldb-commits] [PATCH] D154926: [lldb][AArch64] Add support for SME's SVE streaming mode registers

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. This looks very good much simpler from the first version. just a minor nit. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:81

[Lldb-commits] [PATCH] D154927: [lldb][AArch64] Add SME's streaming vector control register

omjavaid added a comment. I guess there is not much gain from telling the user between sve/ssve mode for the moment. Can we defer this patch till SME registers are implemented? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154927/new/ https://revi

[Lldb-commits] [PATCH] D156118: [lldb][AArch64] Add reading of TLS tpidr register from core files

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. Looks legit. Thanks Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156118/new/ https://reviews.llvm.org/D156118

[Lldb-commits] [PATCH] D156512: [lldb][AArch64] Save/restore TLS registers around expressions

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. This looks good. Just a nit the summary seems to be using a lot pronouns. Could you kindly improve summary a little and add a one liner about expr_func and how it tests save/restore for fu

[Lldb-commits] [PATCH] D75555: [GlobalISel][Localizer] Enable intra-block localization of already-local uses.

omjavaid added a comment. In D7#1908351 , @aemerson wrote: > @omjavaid can you look over the lldb changes? I don't have the hardware to be > able to actually run this test but I've tried to relax the checks. @aemerson I have moved these test to skip

[Lldb-commits] [PATCH] D75555: [GlobalISel][Localizer] Enable intra-block localization of already-local uses.

omjavaid added a comment. In D7#1909194 , @labath wrote: > Yep, that test really shouldn't be doing that. Historically, lldb has been > avoiding architecture specific artifacts (like assembly) in its tests, but > that didn't really work out here. Tha

[Lldb-commits] [PATCH] D77043: Fix process gdb-remote usage of value_regs/invalidate_regs

omjavaid created this revision. omjavaid added reviewers: labath, jankratochvil. Herald added subscribers: danielkiss, kristof.beyls. Herald added a reviewer: rengolin. Native register descriptions in LLDB specify lldb register numbers in value_regs and invalidate_regs lists. These register numbe

[Lldb-commits] [PATCH] D77045: Add invalidate list to primary regs in arm64 register infos

omjavaid created this revision. omjavaid added a reviewer: labath. Herald added subscribers: danielkiss, kristof.beyls. AArch64 reigster X and V registers are primary GPR and vector registers respectively. If these registers are modified their corresponding children w regs or s/d regs should be

[Lldb-commits] [PATCH] D77044: Extend max register size to accommodate AArch64 SVE vector regs

omjavaid created this revision. omjavaid added reviewers: labath, jankratochvil. Herald added subscribers: danielkiss, kristof.beyls, tschuett. Herald added a reviewer: rengolin. This patch increases maximum register size to 256 bytes to accommodate AArch64 SVE registers maximum possible size of

[Lldb-commits] [PATCH] D77047: AArch64 SVE register infos and ptrace support

omjavaid created this revision. omjavaid added reviewers: labath, clayborg, jankratochvil, jasonmolenda. Herald added subscribers: danielkiss, kristof.beyls, tschuett. Herald added a reviewer: rengolin. This patch adds support for AArch64 SVE register infos description and register access via ptr

[Lldb-commits] [PATCH] D72251: [RFC] Support SVE registers access on AArch64 Linux

omjavaid abandoned this revision. omjavaid added a comment. Herald added a subscriber: danielkiss. Abandoned in favor of following patches and more to come as suggested by labath in separate patches. https://reviews.llvm.org/D77047 https://reviews.llvm.org/D77045 https://reviews.llvm.org/D7704

[Lldb-commits] [PATCH] D77043: Fix process gdb-remote usage of value_regs/invalidate_regs

omjavaid updated this revision to Diff 25. omjavaid added a comment. Posting full diff. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77043/new/ https://reviews.llvm.org/D77043 Files: lldb/docs/lldb-gdb-remote.txt lldb/include/lldb/Host/common/NativeRegisterContext.h lldb/pac

[Lldb-commits] [PATCH] D77043: Fix process gdb-remote usage of value_regs/invalidate_regs

omjavaid added a comment. In D77043#1954672 , @labath wrote: > I am still thinking this over, but for now I have two comments. First, could > you re-upload the diff with full context (e.g. `git show -U`). That would > make it a lot easier to review t

[Lldb-commits] [PATCH] D77047: AArch64 SVE register infos and ptrace support

omjavaid updated this revision to Diff 254454. omjavaid added a comment. Posting full diff. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77047/new/ https://reviews.llvm.org/D77047 Files: lldb/source/Plugins/Process/Linux/LinuxPTraceDefines_arm64sve.h lldb/source/Plugins/Process/Li

[Lldb-commits] [PATCH] D77047: AArch64 SVE register infos and ptrace support

omjavaid added a comment. In D77047#1954696 , @labath wrote: > > There is no physical hardware currently available to test SVE and we make > > use of QEMU for the purpose of testing this feature. > > Are these registers presented in core files in any way?

[Lldb-commits] [PATCH] D77045: Add invalidate list to primary regs in arm64 register infos

omjavaid marked an inline comment as done. omjavaid added a comment. In D77045#1954690 , @labath wrote: > This sounds like it could use a test case. Adding a testcase would be tricky as these register overlap in memory and we store them with overlapping

[Lldb-commits] [PATCH] D77044: Extend max register size to accommodate AArch64 SVE vector regs

omjavaid marked 2 inline comments as done. omjavaid added a comment. In D77044#1954685 , @labath wrote: > Sounds fairly noncontroversial. I don't think we have too many of these > objects floating around, but if it turns out we do, we could switch to a >

[Lldb-commits] [PATCH] D77044: Extend max register size to accommodate AArch64 SVE vector regs

omjavaid updated this revision to Diff 254479. omjavaid added a comment. Posting full diff. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77044/new/ https://reviews.llvm.org/D77044 Files: lldb/include/lldb/Utility/RegisterValue.h lldb/source/Plugins/Process/gdb-remote/GDBRemoteComm

[Lldb-commits] [PATCH] D77214: [lldb] Add option to retry Fix-Its multiple times to failed expressions

omjavaid reopened this revision. omjavaid added a comment. This revision is now accepted and ready to land. This patch fails on lldb-aarch64-linux with following backtrace, apparently failing experession eval. I am marking it xfail for now. Traceback (most recent call last): File "/home/omai

[Lldb-commits] [PATCH] D77045: Add invalidate list to primary regs in arm64 register infos

omjavaid added a comment. In D77045#1963896 , @labath wrote: > In D77045#1956879 , @omjavaid wrote: > > > Adding a testcase would be tricky as these register overlap in memory and > > we store them with overlapping

[Lldb-commits] [PATCH] D77047: AArch64 SVE register infos and ptrace support

omjavaid added a comment. In D77047#1956774 , @omjavaid wrote: > In D77047#1954696 , @labath wrote: > > > > There is no physical hardware currently available to test SVE and we make > > > use of QEMU for the purpos

[Lldb-commits] [PATCH] D74398: [lldb-server] jThreadsInfo returns stack memory

omjavaid reopened this revision. omjavaid added a comment. This revision is now accepted and ready to land. This patch breaks on TestMemoryCache.py lldb AArch64/Linux. we ll have to revert it untill fixed FAIL: test_memory_cache_dwarf (TestMemoryCache.MemoryCacheTestCase) Test the MemoryCa

[Lldb-commits] [PATCH] D77793: Fix LLDB elf core dump register access for ARM/AArch64

omjavaid created this revision. omjavaid added a reviewer: labath. Herald added subscribers: danielkiss, kristof.beyls. This patch adds support to access AArch64 FP SIMD core dump registers and adds a test case to verify registers. This patches fixes a bug where doing "register read --all" cause

[Lldb-commits] [PATCH] D77043: Fix process gdb-remote usage of value_regs/invalidate_regs

omjavaid marked 2 inline comments as done. omjavaid added a comment. In D77043#1971486 , @labath wrote: > Register infos in lldb are a mess. However lldb seems to be able to > communicate (more or less successfully) with stub which know nothing about > l

[Lldb-commits] [PATCH] D77047: AArch64 SVE register infos and ptrace support

omjavaid added a comment. In D77047#1971454 , @labath wrote: > In D77047#1966539 , @omjavaid wrote: > > > @labath Core file FP register access is not supported on AArch64. I am > > working on a follow up patch to f

[Lldb-commits] [PATCH] D77043: Fix process gdb-remote usage of value_regs/invalidate_regs

omjavaid added a comment. @labath I have considered alternatives which can be used to avoid this patch altogether. We are creating dynamic register infos vector for SVE in D77047 . This is needed because we have update register size and offset of SVE registers.

[Lldb-commits] [PATCH] D77047: AArch64 SVE register infos and ptrace support

omjavaid marked 4 inline comments as done. omjavaid added inline comments. Comment at: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp:1191 + size_t vq = sve_vq_from_vl(m_sve_header.vl); + SetRegisterInfoMode(vq); + m_sve_ptrace_

[Lldb-commits] [PATCH] D77793: Fix LLDB elf core dump register access for ARM/AArch64

omjavaid updated this revision to Diff 259182. omjavaid added a comment. Updated diff after implementing core file using assembly code. Also removed the redundant register info is null condition. LGTM? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77793/new/ https://reviews.llvm.org/D

[Lldb-commits] [PATCH] D77047: AArch64 SVE register infos and ptrace support

omjavaid added a comment. Also about licensing issues of included macros I am in contact with original authors from ARM and I hope they will be able to help sign off this patch for LLVM submission. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77047/new/ https://reviews.llvm.org/D7704

[Lldb-commits] [PATCH] D78462: get rid of PythonInteger::GetInteger()

omjavaid reopened this revision. omjavaid added a comment. This revision is now accepted and ready to land. This causes multiple test failures on LLDB AArch64 Linux buildbot. http://lab.llvm.org:8011/builders/lldb-aarch64-ubuntu/builds/3695 Repository: rG LLVM Github Monorepo CHANGES SINCE LA

[Lldb-commits] [PATCH] D78462: get rid of PythonInteger::GetInteger()

omjavaid requested changes to this revision. omjavaid added a comment. This revision now requires changes to proceed. I have temporarily reverted this change to turn buildbot green. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78462/new/ https://r

[Lldb-commits] [PATCH] D78462: get rid of PythonInteger::GetInteger()

This revision was not accepted when it landed; it landed in state "Needs Revision". This revision was automatically updated to reflect the committed changes. Closed by commit rG478619cf9a24: Revert "get rid of PythonInteger::GetInteger()" (authored by omjavaid). Changed prior to commit: https:

[Lldb-commits] [PATCH] D77043: Fix process gdb-remote usage of value_regs/invalidate_regs

omjavaid added a comment. In D77043#1996983 , @labath wrote: > Where does the option which I proposed fit in? It sounds like it would be > something like 1a), where we don't actually modify the "invalidate" numbers > stored within lldb-server, but we jus

[Lldb-commits] [PATCH] D78462: get rid of PythonInteger::GetInteger()

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. Thanks for getting this fixed. Looks good now. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78462/new/ https://reviews.llvm.org/D78462

[Lldb-commits] [PATCH] D75607: [lldb] Use llvm::MC for register numbers in AArch64 ABIs

omjavaid accepted this revision. omjavaid added a comment. This revision is now accepted and ready to land. Looks good to me. Tested on AArch64/Linux with no regressions. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75607/new/ https://reviews.llvm

[Lldb-commits] [PATCH] D77044: Extend max register size to accommodate AArch64 SVE vector regs

This revision was automatically updated to reflect the committed changes. Closed by commit rG9f8b4472fb60: Extend max register size to accommodate AArch64 SVE vector regs (authored by omjavaid). Herald added a project: LLDB. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https

[Lldb-commits] [PATCH] D77793: Fix LLDB elf core dump register access for ARM/AArch64

This revision was automatically updated to reflect the committed changes. omjavaid marked an inline comment as done. Closed by commit rGe35dbb3c8878: Fix LLDB elf core dump register access for ARM/AArch64 (authored by omjavaid). Herald added a project: LLDB. Changed prior to commit: https://rev

[Lldb-commits] [PATCH] D75607: [lldb] Use llvm::MC for register numbers in AArch64 ABIs

omjavaid added a subscriber: clayborg. omjavaid added a comment. In D75607#2020365 , @labath wrote: > Thanks for trying this out. Do you by any chance have any ideas why would > lldb assign a dwarf number to the pc register when neither llvm nor the arm64

[Lldb-commits] [PATCH] D77043: Fix process gdb-remote usage of value_regs/invalidate_regs

omjavaid updated this revision to Diff 263107. omjavaid added a comment. @labath as per your suggestion I have implemented a solution where we fixup register index before sending them to the host in xml or registerinfos packet. Also two new helper functions are added which can be overriden by re

[Lldb-commits] [PATCH] D77045: Minor fixups to LLDB AArch64 register infos macros for SVE register infos

omjavaid added a comment. In D77045#1966540 , @omjavaid wrote: > In D77045#1963896 , @labath wrote: > > > In D77045#1956879 , @omjavaid > > wrote: > > > > > Adding a testcas

[Lldb-commits] [PATCH] D77045: Minor fixups to LLDB AArch64 register infos macros for SVE register infos

omjavaid updated this revision to Diff 263105. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77045/new/ https://reviews.llvm.org/D77045 Files: lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h Index: lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h ==

[Lldb-commits] [PATCH] D79699: Add ptrace register access for AArch64 SVE registers

omjavaid created this revision. omjavaid added reviewers: labath, jasonmolenda, clayborg. Herald added subscribers: danielkiss, kristof.beyls, tschuett. Herald added a reviewer: rengolin. This patch adds NativeRegisterContext_arm64 ptrace routines to access AArch64 SVE registers. This patch also

[Lldb-commits] [PATCH] D77047: AArch64 SVE register infos and ptrace support

omjavaid updated this revision to Diff 263106. omjavaid added a comment. This patch now contains AArch64 SVE register infos description and support for core dump SVE register access. Linux ptrace support will be submitted in a follow up patch while linux ptrace headers are being submitted by Arm

[Lldb-commits] [PATCH] D79491: [lldb] Revive TestBasicEntryValuesX86_64

omjavaid added a comment. This breaks on arm-linux. I am going remove arm temporarily. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79491/new/ https://reviews.llvm.org/D79491 ___ lldb-commits mailing

[Lldb-commits] [PATCH] D79777: Fix error in TestNumThreads.py when frame.GetFunctionName returns none

omjavaid created this revision. omjavaid added a reviewer: labath. Herald added a subscriber: kristof.beyls. This patch fixes an error happening in TestNumThreads.py when it encounters frame.GetFunctionName none for address only locations in stripped libc. This error was showing up on arm-linux

[Lldb-commits] [PATCH] D79777: Fix error in TestNumThreads.py when frame.GetFunctionName returns none

This revision was automatically updated to reflect the committed changes. Closed by commit rG0796b170fb3b: Fix error in TestNumThreads.py when frame.GetFunctionName returns none (authored by omjavaid). Herald added a project: LLDB. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[Lldb-commits] [PATCH] D77043: Fix process gdb-remote usage of value_regs/invalidate_regs

omjavaid marked 2 inline comments as done. omjavaid added a comment. In D77043#2031339 , @labath wrote: > The invalidate_regs part looks as I would expect. I think it ought to be > implemented a bit differently, but that can wait until the bigger issue is

[Lldb-commits] [PATCH] D79699: Add ptrace register access for AArch64 SVE registers

omjavaid updated this revision to Diff 263935. omjavaid added a comment. This new updated patch overrides GetRegisterInfoAtIndex in NativeRegisterContextLinux_arm64 to reduce the impacts of register numbering conversion on the generic LLGS code. CHANGES SINCE LAST ACTION https://reviews.llvm

[Lldb-commits] [PATCH] D77043: Fix process gdb-remote usage of value_regs/invalidate_regs

omjavaid updated this revision to Diff 263937. omjavaid added a comment. This updated diff reduces impact of register numbering correction on LLGS code by removing UserRegIndexToRegInfosIndex out of the code and instead overriding GetRegisterInfoAtIndex in NativeRegisterContextLinux_arm64. CHA

[Lldb-commits] [PATCH] D77047: AArch64 SVE register infos and core file support

omjavaid updated this revision to Diff 263934. omjavaid added a comment. New update contains minor update needed to accommodate SVE PTrace macros header from ARM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77047/new/ https://reviews.llvm.org/D77047 Files: lldb/include/lldb/Target

[Lldb-commits] [PATCH] D80104: [LLDB] Remove code duplication from RegisterContextPOSIX_*

omjavaid created this revision. omjavaid added a reviewer: labath. Herald added subscribers: atanasyan, kbarton, kristof.beyls, nemanjai. This patch aims to remove multiple copies of GetByteOrder() and ConvertRegisterKindToRegisterNumber used in various versions of RegisterContextPOSIX_*. Both

[Lldb-commits] [PATCH] D80105: [LLDB] Combine multiple defs of arm64 register sets

omjavaid created this revision. omjavaid added a reviewer: labath. Herald added subscribers: danielkiss, atanasyan, kristof.beyls, emaste. This patch aims to combine similar arm64 register set definitions defined in NativeRegisterContextLinux_arm64 and RegisterContextPOSIX_arm64. I have implement

[Lldb-commits] [PATCH] D77043: Fix process gdb-remote usage of value_regs/invalidate_regs

omjavaid added a comment. In D77043#2041844 , @labath wrote: > Sorry, about the delay. I had to find some time to dig into the code again, > to understand all of the interactions. > > It seems that we (lldb) have painted ourselves in the corner somewhat.

[Lldb-commits] [PATCH] D80150: [lldb/DataFormatter] Check for overflow when finding NSDate epoch

omjavaid reopened this revision. omjavaid added a comment. This revision is now accepted and ready to land. This patch breaks lldb unit tests on lldb-arm-ubuntu buildbot. http://lab.llvm.org:8014/builders/lldb-arm-ubuntu/builds/1697 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTI

[Lldb-commits] [PATCH] D66934: [ARM64] Simplify RegisterInfos_arm64.h with macro based RegisterInfo array

omjavaid created this revision. omjavaid added reviewers: labath, jasonmolenda. Herald added subscribers: kristof.beyls, javed.absar. Herald added a reviewer: rengolin. This patches paves way for upcoming SVE RegisterInfo definitions. This is cosmetic change which allows us to define ARM64 Regist

[Lldb-commits] [PATCH] D66934: [ARM64] Simplify RegisterInfos_arm64.h with macro based RegisterInfo array

omjavaid marked 3 inline comments as done. omjavaid added a comment. Thanks @clayborg suggestions noted and will be fixed in committed patch. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66934/new/ https://reviews.llvm.org/D66934 ___ lldb-

[Lldb-commits] [PATCH] D66934: [ARM64] Simplify RegisterInfos_arm64.h with macro based RegisterInfo array

This revision was automatically updated to reflect the committed changes. Closed by commit rL370644: [ARM64] Simplify RegisterInfos_arm64.h with macro based RegisterInfo array (authored by omjavaid, committed by ). Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Changed pri

[Lldb-commits] [PATCH] D62235: [ARM64][AArch64] Update disassembler attributes to ARMv8.5 ISA with SVE extensions

omjavaid created this revision. omjavaid added a reviewer: labath. Herald added subscribers: kristof.beyls, tschuett, javed.absar. Herald added a project: LLDB. This patch updates assembler attributes for AArch64 targets so we can disassemble newer instructions supported in ISA version 8.5 and SV

[Lldb-commits] [PATCH] D62235: [ARM64][AArch64] Update disassembler attributes to ARMv8.5 ISA with SVE extensions

This revision was automatically updated to reflect the committed changes. Closed by commit rLLDB361451: [ARM64][AArch64] Update disassembler attributes to ARMv8.5 ISA with SVE… (authored by omjavaid, committed by ). Repository: rLLDB LLDB CHANGES SINCE LAST ACTION https://reviews.llvm.org/D6

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