Author: Serge Pavlov
Date: 2024-07-05T09:10:03+07:00
New Revision: 82a6d1572ff4de1491ea58eb167967350eace9fa
URL:
https://github.com/llvm/llvm-project/commit/82a6d1572ff4de1491ea58eb167967350eace9fa
DIFF:
https://github.com/llvm/llvm-project/commit/82a6d1572ff4de1491ea58eb167967350eace9fa.diff
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/97605
>From 84e7eb3c36b99ac7f673d9a7ad0c88c469f7f45d Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Mon, 1 Jul 2024 20:13:54 +0300
Subject: [PATCH 1/2] [AArch64][PAC] Support BLRA* instructions in SLS
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/97605
>From 84e7eb3c36b99ac7f673d9a7ad0c88c469f7f45d Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Mon, 1 Jul 2024 20:13:54 +0300
Subject: [PATCH] [AArch64][PAC] Support BLRA* instructions in SLS
https://github.com/atrosinenko updated
https://github.com/llvm/llvm-project/pull/97605
>From f49c32c8465e9e68d7345fa82ae1294cc2faf0e7 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko
Date: Mon, 1 Jul 2024 20:13:54 +0300
Subject: [PATCH] [AArch64][PAC] Support BLRA* instructions in SLS
llvmbot wrote:
@llvm/pr-subscribers-flang-openmp
@llvm/pr-subscribers-mlir-openmp
Author: Sergio Afonso (skatrak)
Changes
This patch adds support for lowering 'DO SIMD' constructs to MLIR. SIMD
information is now stored in an `omp.simd` loop wrapper, which is currently
ignored by the
https://github.com/skatrak created
https://github.com/llvm/llvm-project/pull/97718
This patch adds support for lowering 'DO SIMD' constructs to MLIR. SIMD
information is now stored in an `omp.simd` loop wrapper, which is currently
ignored by the OpenMP dialect to LLVM IR translation stage.
@@ -183,10 +183,10 @@ define <2 x half> @local_atomic_fadd_v2f16_rtn(ptr
addrspace(3) %ptr, <2 x half>
define amdgpu_kernel void @local_atomic_fadd_v2bf16_noret(ptr addrspace(3)
%ptr, <2 x i16> %data) {
; GFX940-LABEL: local_atomic_fadd_v2bf16_noret:
; GFX940: ; %bb.0:
https://github.com/mjklemm approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/97565
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https://github.com/mjklemm approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/97564
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https://github.com/tblah approved this pull request.
Code changes look good.
I would prefer to see a lit test for this code path. It is good enough if this
is used by a test added later in your PR stack. Otherwise, please could you add
a lit test which hits this condition so that we can catch
@@ -183,10 +183,10 @@ define <2 x half> @local_atomic_fadd_v2f16_rtn(ptr
addrspace(3) %ptr, <2 x half>
define amdgpu_kernel void @local_atomic_fadd_v2bf16_noret(ptr addrspace(3)
%ptr, <2 x i16> %data) {
; GFX940-LABEL: local_atomic_fadd_v2bf16_noret:
; GFX940: ; %bb.0:
@@ -1492,7 +1466,7 @@ genParallelOp(lower::AbstractConverter ,
lower::SymMap ,
firOpBuilder.createBlock(, /*insertPt=*/{}, allRegionArgTypes,
allRegionArgLocs);
-llvm::SmallVector allSymbols = reductionSyms;
+llvm::SmallVector
https://github.com/tblah commented:
This looks good overall. Do you expect there to be a lot more wrapper
operations in the near future? If so, they look like there is a common pattern
that could be further abstracted. Something like
```c++
template
static OP
genWrapperOp(..., llvm::ArrayRef
https://github.com/tblah edited https://github.com/llvm/llvm-project/pull/97566
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@@ -518,8 +518,8 @@ struct OpWithBodyGenInfo {
}
OpWithBodyGenInfo &
- setReductions(llvm::SmallVectorImpl *value1,
-llvm::SmallVectorImpl *value2) {
+ setReductions(llvm::ArrayRef *value1,
+llvm::ArrayRef *value2) {
wangpc-pp wrote:
https://github.com/llvm/llvm-project/pull/97708 is splitted out for adding
`FeaturePredictableSelectIsExpensive`.
https://github.com/llvm/llvm-project/pull/80124
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https://github.com/tblah approved this pull request.
LGTM, thanks!
https://github.com/llvm/llvm-project/pull/97565
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/96444
>From 4590c05051bbf57f0b269b2561aa1a7c74f06fbc Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sun, 23 Jun 2024 17:07:53 +0200
Subject: [PATCH] AMDGPU: Add subtarget feature for memory atomic fadd f64
---
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/96443
>From b29740ba988e2286a7edc67b5a96c5dce0e600a6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sun, 23 Jun 2024 16:44:08 +0200
Subject: [PATCH 1/3] AMDGPU: Add subtarget feature for global atomic fadd
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/96443
>From b633b82d58ecc55bb88eaefd87d5b3030799f2c0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Sun, 23 Jun 2024 16:44:08 +0200
Subject: [PATCH 1/3] AMDGPU: Add subtarget feature for global atomic fadd
wangpc-pp wrote:
Ping.
I'd like to push this forward because we don't take branch probabilities into
consideration now.
Example: https://godbolt.org/z/doGhYadKM
We should use branches instead of selects in this case and this patch (the
enabling of SelectOpt) will optimize this.
`clang -O3
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/80124
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Sun, 18 Feb 2024 11:12:16 +0800
Subject: [PATCH 1/2] Move after addIRPasses
Created using spr 1.3.4
---
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