[llvm-commits] CVS: llvm/lib/Target/README.txt

Changes in directory llvm/lib/Target: README.txt updated: 1.23 -> 1.24 --- Log message: add a note --- Diffs of the changes: (+10 -0) README.txt | 10 ++ 1 files changed, 10 insertions(+) Index: llvm/lib/Target/README.txt diff -u llvm/lib/Target/README.txt:1.23 llvm/lib/Target/

[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td

Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.13 -> 1.14 --- Log message: Fix PSHUF* and SHUF* jit code emission problems --- Diffs of the changes: (+35 -25) X86InstrSSE.td | 60 + 1 files changed, 35 insertions

[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Makefile

Changes in directory llvm-test/SingleSource/UnitTests: Makefile updated: 1.5 -> 1.6 --- Log message: Recurse into the Vector dir --- Diffs of the changes: (+1 -1) Makefile |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm-test/SingleSource/UnitTests/Makefile diff -u l

[llvm-commits] CVS: llvm/lib/ExecutionEngine/ExecutionEngine.cpp

Changes in directory llvm/lib/ExecutionEngine: ExecutionEngine.cpp updated: 1.75 -> 1.76 --- Log message: Eliminate the dependency of ExecutionEngine on the JIT/Interpreter libraries. Now you can build a tool with just the JIT or just the interpreter. --- Diffs of the changes: (+8 -18) Ex

[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/Makefile

Changes in directory llvm-test/SingleSource/UnitTests/Vector: Makefile added (r1.1) --- Log message: I forgot to check this in earlier --- Diffs of the changes: (+7 -0) Makefile |7 +++ 1 files changed, 7 insertions(+) Index: llvm-test/SingleSource/UnitTests/Vector/Makefile diff

[llvm-commits] CVS: llvm/lib/ExecutionEngine/JIT/JIT.cpp JIT.h

Changes in directory llvm/lib/ExecutionEngine/JIT: JIT.cpp updated: 1.59 -> 1.60 JIT.h updated: 1.27 -> 1.28 --- Log message: Eliminate the dependency of ExecutionEngine on the JIT/Interpreter libraries. Now you can build a tool with just the JIT or just the interpreter. --- Diffs of the cha

[llvm-commits] CVS: llvm/lib/ExecutionEngine/Interpreter/Interpreter.cpp Interpreter.h

Changes in directory llvm/lib/ExecutionEngine/Interpreter: Interpreter.cpp updated: 1.26 -> 1.27 Interpreter.h updated: 1.72 -> 1.73 --- Log message: Eliminate the dependency of ExecutionEngine on the JIT/Interpreter libraries. Now you can build a tool with just the JIT or just the interpreter

[llvm-commits] CVS: llvm/include/llvm/ExecutionEngine/ExecutionEngine.h

Changes in directory llvm/include/llvm/ExecutionEngine: ExecutionEngine.h updated: 1.34 -> 1.35 --- Log message: wrap lines to 80 columns. Add static JITCtor/InterpCtor fields --- Diffs of the changes: (+15 -5) ExecutionEngine.h | 20 +++- 1 files changed, 15 insertions(

[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt

Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.78 -> 1.79 --- Log message: This has been implemented. Tweak it into another note --- Diffs of the changes: (+9 -23) README.txt | 32 +--- 1 files changed, 9 insertions(+), 23 deletions(-)

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp PPCISelLowering.cpp PPCISelLowering.h PPCInstrInfo.td PPCRegisterInfo.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCHazardRecognizers.cpp updated: 1.11 -> 1.12 PPCISelLowering.cpp updated: 1.107 -> 1.108 PPCISelLowering.h updated: 1.30 -> 1.31 PPCInstrInfo.td updated: 1.202 -> 1.203 PPCRegisterInfo.cpp updated: 1.48 -> 1.49 --- Log message: When possible, cust

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCAsmPrinter.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelDAGToDAG.cpp updated: 1.174 -> 1.175 PPCAsmPrinter.cpp updated: 1.159 -> 1.160 --- Log message: Add support for "ri" addressing modes where the immediate is a 14-bit field which is shifted left two bits before use. Instructions like STD use

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.116 -> 1.117 --- Log message: fix a warning --- Diffs of the changes: (+4 -3) X86ISelLowering.cpp |7 --- 1 files changed, 4 insertions(+), 3 deletions(-) Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff

[llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp

Changes in directory llvm/lib/Target/X86: X86CodeEmitter.cpp updated: 1.92 -> 1.93 --- Log message: Add a couple more pseudo instructions. --- Diffs of the changes: (+2 -0) X86CodeEmitter.cpp |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/X86/X86CodeEmitter.cpp diff -u

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.115 -> 1.116 X86ISelLowering.h updated: 1.34 -> 1.35 X86InstrSSE.td updated: 1.12 -> 1.13 --- Log message: Some splat and shuffle support. --- Diffs of the changes: (+157 -8) X86ISelLowering.cpp | 85 +++

[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/sumarray.c helpers.h

Changes in directory llvm-test/SingleSource/UnitTests/Vector: sumarray.c added (r1.1) helpers.h updated: 1.1 -> 1.2 --- Log message: Simple vector sum example --- Diffs of the changes: (+24 -0) helpers.h |2 ++ sumarray.c | 22 ++ 2 files changed, 24 insertions(+

[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/

Changes in directory llvm-test/SingleSource/UnitTests/Vector: --- Log message: Directory /var/cvs/llvm/llvm-test/SingleSource/UnitTests/Vector added to the repository --- Diffs of the changes: (+0 -0) 0 files changed ___ llvm-commits mailing

[llvm-commits] CVS: llvm-test/SingleSource/UnitTests/Vector/build.c helpers.h simple.c

Changes in directory llvm-test/SingleSource/UnitTests/Vector: build.c added (r1.1) helpers.h added (r1.1) simple.c added (r1.1) --- Log message: add some trivial testcases. --- Diffs of the changes: (+39 -0) build.c | 14 ++ helpers.h | 10 ++ simple.c | 15 +++

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.330 -> 1.331 --- Log message: Endianness does not affect the order of vector fields. This fixes SingleSource/UnitTests/Vector/build.c --- Diffs of the changes: (+1 -6) LegalizeDAG.cpp |7 +-- 1 files ch

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrFormats.td PPCInstrInfo.td

Changes in directory llvm/lib/Target/PowerPC: PPCInstrFormats.td updated: 1.66 -> 1.67 PPCInstrInfo.td updated: 1.201 -> 1.202 --- Log message: Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp --- Diffs of the changes: (+8 -9) PPCInstrFormats.td |2 +- PPCInstrInfo.

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.329 -> 1.330 --- Log message: Enclose some variables in a scope to avoid error with some gcc versions --- Diffs of the changes: (+3 -2) LegalizeDAG.cpp |5 +++-- 1 files changed, 3 insertions(+), 2 deletions

[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td

Changes in directory llvm/lib/Target/X86: X86InstrMMX.td updated: 1.6 -> 1.7 --- Log message: Didn't mean to check this in. No MMX support yet. --- Diffs of the changes: (+1 -3) X86InstrMMX.td |4 +--- 1 files changed, 1 insertion(+), 3 deletions(-) Index: llvm/lib/Target/X86/X86Instr

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrMMX.td X86InstrSSE.td

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.114 -> 1.115 X86ISelLowering.h updated: 1.33 -> 1.34 X86InstrMMX.td updated: 1.5 -> 1.6 X86InstrSSE.td updated: 1.11 -> 1.12 --- Log message: - Use movaps to store 128-bit vector integers. - Each scalar to vector v8i16 and

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.328 -> 1.329 --- Log message: add expand support for extractelement --- Diffs of the changes: (+31 -1) LegalizeDAG.cpp | 32 +++- 1 files changed, 31 insertions(+), 1 deletion(-)

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.113 -> 1.114 --- Log message: These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will. --- Diffs of the changes: (+1 -0) X86ISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/l

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.106 -> 1.107 --- Log message: These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will. --- Diffs of the changes: (+1 -0) PPCISelLowering.cpp |1 + 1 files changed, 1 insertion(+) Index: ll

[llvm-commits] CVS: llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Changes in directory llvm/include/llvm/CodeGen: SelectionDAGNodes.h updated: 1.116 -> 1.117 --- Log message: add some nodes for extractelement --- Diffs of the changes: (+10 -0) SelectionDAGNodes.h | 10 ++ 1 files changed, 10 insertions(+) Index: llvm/include/llvm/CodeGen/Sele

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.327 -> 1.328 SelectionDAG.cpp updated: 1.277 -> 1.278 SelectionDAGISel.cpp updated: 1.198 -> 1.199 --- Log message: add some trivial support for extractelement. --- Diffs of the changes: (+62 -2) LegalizeDAG.cpp

[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.181 -> 1.182 --- Log message: Don't forget to promote xform function to an explicit node for def : Pat<> patterns. --- Diffs of the changes: (+20 -1) DAGISelEmitter.cpp | 21 - 1 files changed, 20

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCCodeEmitter.cpp updated: 1.48 -> 1.49 --- Log message: Don't emit pseudo instructions! --- Diffs of the changes: (+1 -0) PPCCodeEmitter.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp diff -u

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: LegalizeDAG.cpp updated: 1.326 -> 1.327 SelectionDAG.cpp updated: 1.276 -> 1.277 SelectionDAGISel.cpp updated: 1.197 -> 1.198 --- Log message: Add a hacky workaround for crashes due to vectors live across blocks. Note that this code won't work

[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt

Changes in directory llvm/lib/Target/PowerPC: README.txt updated: 1.77 -> 1.78 --- Log message: Update readme --- Diffs of the changes: (+34 -0) README.txt | 34 ++ 1 files changed, 34 insertions(+) Index: llvm/lib/Target/PowerPC/README.txt diff -u llvm/

[llvm-commits] CVS: llvm/test/Regression/CodeGen/Generic/vector.ll

Changes in directory llvm/test/Regression/CodeGen/Generic: vector.ll updated: 1.5 -> 1.6 --- Log message: Add an integer splat test --- Diffs of the changes: (+19 -0) vector.ll | 19 +++ 1 files changed, 19 insertions(+) Index: llvm/test/Regression/CodeGen/Generic/vecto

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.158 -> 1.159 --- Log message: Print absolute memory references like this: lwz r2, 8(0) instead of this: lwz r2, 8(r0) This fixes the llc/llc-beta failures on PPC last night. --- Diffs of the changes: