Changes in directory llvm/test/Regression/CodeGen/X86:
vec_zero.ll added (r1.1)
---
Log message:
Zero vector testcase
---
Diffs of the changes: (+16 -0)
vec_zero.ll | 16
1 files changed, 16 insertions(+)
Index: llvm/test/Regression/CodeGen/X86/vec_zero.ll
diff -c
Changes in directory llvm/docs:
SourceLevelDebugging.html updated: 1.17 - 1.18
---
Log message:
Fixed some grammer and spelling.
---
Diffs of the changes: (+7 -6)
SourceLevelDebugging.html | 13 +++--
1 files changed, 7 insertions(+), 6 deletions(-)
Index:
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.203 - 1.204
---
Log message:
Rename for truth in advertising.
---
Diffs of the changes: (+2 -2)
SelectionDAGISel.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index:
Changes in directory llvm/include/llvm:
IntrinsicInst.h updated: 1.13 - 1.14
---
Log message:
Rename for truth in advertising.
---
Diffs of the changes: (+1 -1)
IntrinsicInst.h |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/include/llvm/IntrinsicInst.h
diff -u
Changes in directory llvm/lib/VMCore:
IntrinsicInst.cpp updated: 1.1 - 1.2
---
Log message:
Clean up some commentary.
---
Diffs of the changes: (+19 -1)
IntrinsicInst.cpp | 20 +++-
1 files changed, 19 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target:
SubtargetFeature.cpp updated: 1.9 - 1.10
---
Log message:
Clean up some commentary.
---
Diffs of the changes: (+1 -1)
SubtargetFeature.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/SubtargetFeature.cpp
diff -u
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
mem-rr-addr-mode.ll added (r1.1)
---
Log message:
New testcase
---
Diffs of the changes: (+17 -0)
mem-rr-addr-mode.ll | 17 +
1 files changed, 17 insertions(+)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.175 - 1.176
---
Log message:
Like the comment says, prefer to use the implicit add done by [r+r] addressing
modes than emitting an explicit add and using a base of r0. This implements
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.td updated: 1.206 - 1.207
---
Log message:
Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ??
---
Diffs of the changes: (+2 -2)
PPCInstrInfo.td |4 ++--
1 files changed, 2 insertions(+), 2
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.337 - 1.338
---
Log message:
Only to vector shuffle for {x,x,y,y} cases when SCALAR_TO_VECTOR is free.
---
Diffs of the changes: (+2 -1)
LegalizeDAG.cpp |3 ++-
1 files changed, 2 insertions(+), 1
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.55 - 1.56
---
Log message:
expose intrinsic info to the targets.
---
Diffs of the changes: (+3 -0)
TargetSelectionDAG.td |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/Target/TargetSelectionDAG.td
diff
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.12 - 1.13
---
Log message:
Pull in valuetypes.td here, we will use it shortly.
---
Diffs of the changes: (+2 -0)
Intrinsics.td |2 ++
1 files changed, 2 insertions(+)
Index: llvm/include/llvm/Intrinsics.td
diff -u
Changes in directory llvm/lib/Target:
Target.td updated: 1.73 - 1.74
TargetSelectionDAG.td updated: 1.56 - 1.57
---
Log message:
Shuffle some includes around
---
Diffs of the changes: (+2 -4)
Target.td |3 ++-
TargetSelectionDAG.td |3 ---
2 files changed, 2
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.13 - 1.14
---
Log message:
Specify the value type for each llvm type. This needs work for pointers.
---
Diffs of the changes: (+23 -21)
Intrinsics.td | 44 +++-
1 files changed, 23
Changes in directory llvm/utils/TableGen:
IntrinsicEmitter.cpp updated: 1.15 - 1.16
CodeGenIntrinsics.h updated: 1.6 - 1.7
CodeGenTarget.cpp updated: 1.57 - 1.58
---
Log message:
Move CodeGenIntrinsic implementation to CodeGenTarget.cpp with the rest of
the CodeGen* implementations.
Parse the
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.80 - 1.81
---
Log message:
add another note
---
Diffs of the changes: (+15 -0)
README.txt | 15 +++
1 files changed, 15 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.58 - 1.59
---
Log message:
Make sure to initialize the TheDef field!
---
Diffs of the changes: (+1 -0)
CodeGenTarget.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.51 - 1.52
---
Log message:
Hack no more.
---
Diffs of the changes: (+0 -2)
DwarfWriter.cpp |2 --
1 files changed, 2 deletions(-)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.cpp:1.51
Changes in directory llvm/lib/Target:
Target.td updated: 1.74 - 1.75
---
Log message:
Add support for dwarf register numbering.
---
Diffs of the changes: (+21 -0)
Target.td | 21 +
1 files changed, 21 insertions(+)
Index: llvm/lib/Target/Target.td
diff -u
Changes in directory llvm/lib/Target/Sparc:
SparcRegisterInfo.td updated: 1.29 - 1.30
---
Log message:
Add dwarf register numbering to register data.
---
Diffs of the changes: (+80 -31)
SparcRegisterInfo.td | 111 ---
1 files changed, 80
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.td updated: 1.31 - 1.32
---
Log message:
Add dwarf register numbering to register data.
---
Diffs of the changes: (+55 -28)
X86RegisterInfo.td | 83 +++--
1 files changed, 55
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.39 - 1.40
---
Log message:
Add dwarf register numbering to register data.
---
Diffs of the changes: (+18 -1)
RegisterInfoEmitter.cpp | 19 ++-
1 files changed, 18 insertions(+), 1 deletion(-)
Changes in directory llvm/lib/Target/Alpha:
AlphaRegisterInfo.td updated: 1.15 - 1.16
---
Log message:
Add dwarf register numbering to register data.
---
Diffs of the changes: (+64 -33)
AlphaRegisterInfo.td | 97 +--
1 files changed, 64
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.td updated: 1.31 - 1.32
---
Log message:
Add dwarf register numbering to register data.
---
Diffs of the changes: (+140 -71)
PPCRegisterInfo.td | 211 +++--
1 files changed, 140
Changes in directory llvm/lib/Target/IA64:
IA64RegisterInfo.td updated: 1.15 - 1.16
---
Log message:
Add dwarf register numbering to register data.
---
Diffs of the changes: (+332 -169)
IA64RegisterInfo.td | 501 ++--
1 files changed, 332
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.183 - 1.184
DAGISelEmitter.h updated: 1.59 - 1.60
---
Log message:
Parse intrinsics correctly and perform type propagation. This doesn't currently
emit the code to select intrinsics, but that is next :)
---
Diffs of the
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.24 - 1.25
---
Log message:
plug the intrinsics into the patterns for movmsk*
---
Diffs of the changes: (+4 -2)
X86InstrSSE.td |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index:
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.184 - 1.185
---
Log message:
fix 80 column violations
---
Diffs of the changes: (+6 -5)
DAGISelEmitter.cpp | 11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
Index:
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.14 - 1.15
---
Log message:
Added ldmxcsr intrinsic.
---
Diffs of the changes: (+6 -1)
Intrinsics.td |7 ++-
1 files changed, 6 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Intrinsics.td
diff -u
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.15 - 1.16
---
Log message:
ldmxcsr is a SSE instruction.
---
Diffs of the changes: (+5 -6)
Intrinsics.td | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
Index: llvm/include/llvm/Intrinsics.td
diff -u
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.25 - 1.26
---
Log message:
Added LDMXCSR
---
Diffs of the changes: (+7 -0)
X86InstrSSE.td |7 +++
1 files changed, 7 insertions(+)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u
Changes in directory llvm/lib/Target/Sparc:
SparcRegisterInfo.td updated: 1.30 - 1.31
---
Log message:
D'oh - should be even numbered.
---
Diffs of the changes: (+15 -15)
SparcRegisterInfo.td | 30 +++---
1 files changed, 15 insertions(+), 15 deletions(-)
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.204 - 1.205
---
Log message:
fix inverted conditional
---
Diffs of the changes: (+2 -2)
SelectionDAGISel.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index:
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.185 - 1.186
DAGISelEmitter.h updated: 1.60 - 1.61
---
Log message:
Change approach so that we get codegen for free for intrinsics. With this,
intrinsics that don't take pointer arguments now work. For example, we can
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.129 - 1.130
X86ISelLowering.h updated: 1.41 - 1.42
X86InstrInfo.cpp updated: 1.46 - 1.47
X86InstrSSE.td updated: 1.26 - 1.27
---
Log message:
Support for scalar to vector with zero extension.
---
Diffs of the changes:
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.16 - 1.17
---
Log message:
X86 SSE1 arithmetic and logical operation intrinsics.
---
Diffs of the changes: (+135 -0)
Intrinsics.td | 135 ++
1 files changed, 135
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.17 - 1.18
---
Log message:
X86 SSE1 comparison intrinsics.
---
Diffs of the changes: (+216 -0)
Intrinsics.td | 216 ++
1 files changed, 216 insertions(+)
Index:
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.27 - 1.28
---
Log message:
Added CVTSS2SI.
---
Diffs of the changes: (+5 -0)
X86InstrSSE.td |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.18 - 1.19
---
Log message:
X86 SSE1 conversion operations intrinsics.
---
Diffs of the changes: (+34 -1)
Intrinsics.td | 35 ++-
1 files changed, 34 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/X86:
X86InstrMMX.td updated: 1.7 - 1.8
---
Log message:
Added CVTTPS2PI.
---
Diffs of the changes: (+8 -0)
X86InstrMMX.td |8
1 files changed, 8 insertions(+)
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.130 - 1.131
X86InstrSSE.td updated: 1.28 - 1.29
---
Log message:
Added 128-bit packed integer subtraction.
---
Diffs of the changes: (+26 -0)
X86ISelLowering.cpp |3 +++
X86InstrSSE.td | 23
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.19 - 1.20
---
Log message:
X86 SSE1 SIMD load intrinsics (movhps, movlps, and movups).
---
Diffs of the changes: (+21 -4)
Intrinsics.td | 25 +
1 files changed, 21 insertions(+), 4 deletions(-)
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.20 - 1.21
---
Log message:
X86 SSE1 SIMD store intrinsics.
---
Diffs of the changes: (+17 -0)
Intrinsics.td | 17 +
1 files changed, 17 insertions(+)
Index: llvm/include/llvm/Intrinsics.td
diff -u
Changes in directory llvm/lib/Target:
TargetSelectionDAG.td updated: 1.57 - 1.58
---
Log message:
Add new intrinsic node definitions for tblgen use
---
Diffs of the changes: (+12 -0)
TargetSelectionDAG.td | 12
1 files changed, 12 insertions(+)
Index:
Changes in directory llvm/test/Regression/CodeGen/X86:
vec_zexts2v.ll added (r1.1)
---
Log message:
Added a scalar to vector with zero extension testcase
---
Diffs of the changes: (+21 -0)
vec_zexts2v.ll | 21 +
1 files changed, 21 insertions(+)
Index:
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
vec_spat.ll updated: 1.1 - 1.2
---
Log message:
New tests for vsplti*
---
Diffs of the changes: (+15 -0)
vec_spat.ll | 15 +++
1 files changed, 15 insertions(+)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.161 - 1.162
PPCISelLowering.cpp updated: 1.110 - 1.111
PPCISelLowering.h updated: 1.32 - 1.33
PPCInstrInfo.td updated: 1.207 - 1.208
---
Log message:
Codegen things like:
int -1, int -1, int -1, int -1
and
int 65537,
Changes in directory llvm/include/llvm:
Intrinsics.h updated: 1.39 - 1.40
---
Log message:
Add a programatic interface to intrinsic names.
---
Diffs of the changes: (+5 -0)
Intrinsics.h |5 +
1 files changed, 5 insertions(+)
Index: llvm/include/llvm/Intrinsics.h
diff -u
Changes in directory llvm/lib/VMCore:
Function.cpp updated: 1.104 - 1.105
---
Log message:
Implement Intrinsic::getName
---
Diffs of the changes: (+11 -0)
Function.cpp | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/lib/VMCore/Function.cpp
diff -u
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.35 - 1.36
---
Log message:
#include Intrinsics.h into all dag isels
---
Diffs of the changes: (+1 -0)
AlphaISelDAGToDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index:
Changes in directory llvm/lib/Target/Sparc:
SparcISelDAGToDAG.cpp updated: 1.89 - 1.90
---
Log message:
#include Intrinsics.h into all dag isels
---
Diffs of the changes: (+1 -0)
SparcISelDAGToDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index:
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.38 - 1.39
---
Log message:
#include Intrinsics.h into all dag isels
---
Diffs of the changes: (+1 -0)
IA64ISelDAGToDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index:
Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.56 - 1.57
---
Log message:
#include Intrinsics.h into all dag isels
---
Diffs of the changes: (+1 -0)
X86ISelDAGToDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.176 - 1.177
README.txt updated: 1.81 - 1.82
---
Log message:
#include Intrinsics.h into all dag isels
---
Diffs of the changes: (+8 -0)
PPCISelDAGToDAG.cpp |1 +
README.txt |7 +++
2 files
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.22 - 1.23
---
Log message:
Add support for __builtin_altivec_vnmsubfp
---
Diffs of the changes: (+3 -0)
Intrinsics.td |3 +++
1 files changed, 3 insertions(+)
Index: llvm/include/llvm/Intrinsics.td
diff -u
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.td updated: 1.208 - 1.209
---
Log message:
Add support for __builtin_altivec_vnmsubfp /vmaddfp
---
Diffs of the changes: (+5 -0)
PPCInstrInfo.td |5 +
1 files changed, 5 insertions(+)
Index:
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.23 - 1.24
---
Log message:
Add a bunch of simple altivec intrinsics
---
Diffs of the changes: (+36 -1)
Intrinsics.td | 37 -
1 files changed, 36 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/include/llvm:
Intrinsics.td updated: 1.24 - 1.25
---
Log message:
remove extraneous lets
---
Diffs of the changes: (+1 -208)
Intrinsics.td | 209 --
1 files changed, 1 insertion(+), 208 deletions(-)
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.td updated: 1.32 - 1.33
---
Log message:
add all supported formats to the vector register file
---
Diffs of the changes: (+1 -1)
PPCRegisterInfo.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.111 - 1.112
PPCInstrInfo.td updated: 1.209 - 1.210
---
Log message:
Add some basic patterns for other datatypes
---
Diffs of the changes: (+12 -10)
PPCISelLowering.cpp |6 ++
PPCInstrInfo.td | 16
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td added (r1.1)
PPCInstrInfo.td updated: 1.210 - 1.211
---
Log message:
Move all Altivec stuff out into a new PPCInstrAltivec.td file.
Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector
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