Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.231 -> 1.232
---
Log message:
Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI
instruction.
---
Diffs of the changes: (+4 -1)
PPCISelDAGToDAG.cpp |5 -
1 files changed, 4 insert
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.230 -> 1.231
PPCISelLowering.cpp updated: 1.274 -> 1.275
PPCISelLowering.h updated: 1.65 -> 1.66
---
Log message:
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.229 -> 1.230
---
Log message:
Fix a bug which caused us to never be able to use signed comparisons for
equality comparisons of a constant. This allows us to codegen the 'sintzero'
loop in PR1288: http://llvm.org/PR128
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.227 -> 1.228
PPCInstr64Bit.td updated: 1.33 -> 1.34
---
Log message:
Reduce number of instructions to load 64-bit constants.
---
Diffs of the changes: (+75 -42)
PPCISelDAGToDAG.cpp | 75 ++
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.220 -> 1.221
PPCInstrInfo.td updated: 1.263 -> 1.264
---
Log message:
add patterns for ppc32 preinc stores. ppc64 next.
---
Diffs of the changes: (+22 -7)
PPCISelDAGToDAG.cpp |8
PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.219 -> 1.220
PPCISelLowering.cpp updated: 1.226 -> 1.227
PPCInstr64Bit.td updated: 1.27 -> 1.28
PPCInstrInfo.td updated: 1.260 -> 1.261
---
Log message:
fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.218 -> 1.219
---
Log message:
remove a ton of custom selection logic no longer needed
---
Diffs of the changes: (+7 -145)
PPCISelDAGToDAG.cpp | 152 ++--
1 files c
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.217 -> 1.218
---
Log message:
allow the offset of a preinc'd load to be the low-part of a global. This
produces this clever code:
_millisecs:
lis r2, ha16(_Time.1182)
lwzu r3, lo16(_Time.1182)(r2)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.216 -> 1.217
PPCISelLowering.cpp updated: 1.222 -> 1.223
PPCInstr64Bit.td updated: 1.22 -> 1.23
PPCInstrFormats.td updated: 1.82 -> 1.83
---
Log message:
implement preinc support for r+i loads on ppc64
---
Diffs of t
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.215 -> 1.216
PPCISelLowering.cpp updated: 1.221 -> 1.222
PPCInstrInfo.td updated: 1.254 -> 1.255
---
Log message:
add an initial cut at preinc loads for ppc32. This is broken for ppc64
(because the 64-bit reg target v
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.214 -> 1.215
---
Log message:
Match tblegen changes.
---
Diffs of the changes: (+12 -9)
PPCISelDAGToDAG.cpp | 21 -
1 files changed, 12 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/P
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.213 -> 1.214
PPCISelLowering.cpp updated: 1.218 -> 1.219
PPCISelLowering.h updated: 1.54 -> 1.55
---
Log message:
Refactor all the addressing mode selection stuff into the isel lowering
class, where it can be used for
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.211 -> 1.212
---
Log message:
fix miscompilation of llvm.isunordered, where we branched on the opposite
condition. This fixes miscompilation of Olden/bh and many others.
---
Diffs of the changes: (+2 -2)
PPCISelD
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.210 -> 1.211
PPCInstrInfo.td updated: 1.241 -> 1.242
README.txt updated: 1.99 -> 1.100
---
Log message:
Fold AND and ROTL more often
---
Diffs of the changes: (+62 -62)
PPCISelDAGToDAG.cpp | 66 +
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.209 -> 1.210
---
Log message:
Improve PPC64 equality comparisons like PPC32 comparisons.
---
Diffs of the changes: (+31 -3)
PPCISelDAGToDAG.cpp | 34 +++---
1 files changed, 31 insert
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.208 -> 1.209
README.txt updated: 1.96 -> 1.97
---
Log message:
Two improvements:
1. Codegen this comparison:
if (X == 0x8000)
as:
cmplwi cr0, r3, 32768
bne cr0, LBB1_2 ;cond_next
instead of:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.206 -> 1.207
---
Log message:
Do not use getTargetNode() and SelectNodeTo() which takes more than 3
SDOperand arguments. Use the variants which take an array and number instead.
---
Diffs of the changes: (+41 -43)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.205 -> 1.206
---
Log message:
SelectNodeTo now returns a SDNode*.
---
Diffs of the changes: (+20 -20)
PPCISelDAGToDAG.cpp | 40
1 files changed, 20 insertions(+), 20 delet
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.204 -> 1.205
---
Log message:
Select() no longer require Result operand by reference.
---
Diffs of the changes: (+8 -10)
PPCISelDAGToDAG.cpp | 18 --
1 files changed, 8 insertions(+), 10 deletions
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.203 -> 1.204
---
Log message:
Match tblgen changes.
---
Diffs of the changes: (+68 -53)
PPCISelDAGToDAG.cpp | 121 +---
1 files changed, 68 insertions(+), 53 deletio
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.202 -> 1.203
---
Log message:
Fix PowerPC/2006-08-15-SelectionCrash.ll and simplify selection code.
---
Diffs of the changes: (+63 -93)
PPCISelDAGToDAG.cpp | 156 +-
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.201 -> 1.202
---
Log message:
Match tablegen changes.
---
Diffs of the changes: (+32 -53)
PPCISelDAGToDAG.cpp | 85 +++-
1 files changed, 32 insertions(+), 53 delet
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.200 -> 1.201
---
Log message:
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is kn
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.199 -> 1.200
---
Log message:
Match tablegen isel changes.
---
Diffs of the changes: (+50 -101)
PPCISelDAGToDAG.cpp | 151 +---
1 files changed, 50 insertions(+), 10
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.198 -> 1.199
---
Log message:
Remove InFlightSet hack. No longer needed.
---
Diffs of the changes: (+0 -1)
PPCISelDAGToDAG.cpp |1 -
1 files changed, 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToD
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.197 -> 1.198
---
Log message:
Remove NodeDepth
---
Diffs of the changes: (+1 -6)
PPCISelDAGToDAG.cpp |7 +--
1 files changed, 1 insertion(+), 6 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.196 -> 1.197
PPCAsmPrinter.cpp updated: 1.183 -> 1.184
---
Log message:
shrink libllvmgcc.dylib another 25K
---
Diffs of the changes: (+4 -2)
PPCAsmPrinter.cpp |3 ++-
PPCISelDAGToDAG.cpp |3 ++-
2 files
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.195 -> 1.196
PPCInstr64Bit.td updated: 1.16 -> 1.17
---
Log message:
Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)
---
Diffs of the changes: (+5 -6)
PPCISelDAGToDAG.cpp |9 +
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.194 -> 1.195
---
Log message:
Fix ppc64 jump tables
---
Diffs of the changes: (+2 -1)
PPCISelDAGToDAG.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDA
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.193 -> 1.194
---
Log message:
Fix variable shadowing issue
---
Diffs of the changes: (+1 -2)
PPCISelDAGToDAG.cpp |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISel
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.192 -> 1.193
PPCISelLowering.cpp updated: 1.192 -> 1.193
PPCInstrInfo.td updated: 1.234 -> 1.235
---
Log message:
Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but
doesn't work right).
---
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.191 -> 1.192
---
Log message:
Work around a nasty tblgen bug where it doesn't add operands for varargs
nodes correctly.
---
Diffs of the changes: (+157 -0)
PPCISelDAGToDAG.cpp | 157 ++
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.190 -> 1.191
---
Log message:
Fix build failure of povray
---
Diffs of the changes: (+2 -0)
PPCISelDAGToDAG.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.189 -> 1.190
---
Log message:
Fix Benchmarks/MallocBench/cfrac
---
Diffs of the changes: (+2 -0)
PPCISelDAGToDAG.cpp |2 ++
1 files changed, 2 insertions(+)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.188 -> 1.189
---
Log message:
Assert if InflightSet is not cleared after instruction selecting a BB.
---
Diffs of the changes: (+1 -0)
PPCISelDAGToDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/li
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.187 -> 1.188
---
Log message:
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
non-deterministic behavior.
---
Diffs of the changes: (+2 -0)
PPCISelDAGToDAG.cpp |2 ++
1 files change
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.186 -> 1.187
PPCISelLowering.cpp updated: 1.179 -> 1.180
PPCISelLowering.h updated: 1.49 -> 1.50
PPCInstrInfo.td updated: 1.219 -> 1.220
---
Log message:
Make PPC call lowering more aggressive, making the isel matching
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.185 -> 1.186
PPCISelLowering.cpp updated: 1.178 -> 1.179
PPCInstrInfo.td updated: 1.218 -> 1.219
---
Log message:
Switch PPC over to a call-selection model where the lowering code creates
the copyto/fromregs instead of
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.184 -> 1.185
PPCISelLowering.cpp updated: 1.176 -> 1.177
---
Log message:
implement passing/returning vector regs to calls, at least non-varargs calls.
---
Diffs of the changes: (+54 -29)
PPCISelDAGToDAG.cpp | 7
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.183 -> 1.184
---
Log message:
Fix PowerPC/2006-05-12-rlwimi-crash.ll
Nate, please verify that if InsertMask is 0, rlwimi shouldn't be used.
This fixes the crash and causes no PPC testsuite regressions.
---
Diffs of
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.182 -> 1.183
README.txt updated: 1.87 -> 1.88
---
Log message:
Fold more shifts into inserts, and update the README
---
Diffs of the changes: (+34 -20)
PPCISelDAGToDAG.cpp | 39 +++---
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.181 -> 1.182
README.txt updated: 1.86 -> 1.87
---
Log message:
Update some stuff now that the new rlwimi code has gone in
---
Diffs of the changes: (+0 -70)
PPCISelDAGToDAG.cpp |1
README.txt | 69
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.180 -> 1.181
---
Log message:
New rlwimi implementation, which is superior to the old one. There are
still a couple missed optimizations, but we now generate all the possible
rlwimis for multiple inserts into the same
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.178 -> 1.179
PPCISelLowering.cpp updated: 1.140 -> 1.141
PPCInstrInfo.td updated: 1.214 -> 1.215
---
Log message:
Add VRRC select support
---
Diffs of the changes: (+8 -2)
PPCISelDAGToDAG.cpp |5 -
PPCISel
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.177 -> 1.178
PPCISelLowering.cpp updated: 1.113 -> 1.114
PPCISelLowering.h updated: 1.34 -> 1.35
PPCInstrAltivec.td updated: 1.9 -> 1.10
PPCInstrInfo.td updated: 1.211 -> 1.212
---
Log message:
Codegen vector predicate
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.176 -> 1.177
README.txt updated: 1.81 -> 1.82
---
Log message:
#include Intrinsics.h into all dag isels
---
Diffs of the changes: (+8 -0)
PPCISelDAGToDAG.cpp |1 +
README.txt |7 +++
2 files c
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.175 -> 1.176
---
Log message:
Like the comment says, prefer to use the implicit add done by [r+r] addressing
modes than emitting an explicit add and using a base of r0. This implements
Regression/CodeGen/PowerPC/mem-r
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.174 -> 1.175
PPCAsmPrinter.cpp updated: 1.159 -> 1.160
---
Log message:
Add support for "ri" addressing modes where the immediate is a 14-bit field
which is shifted left two bits before use. Instructions like STD use
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.173 -> 1.174
---
Log message:
With Evan's latest tblgen patch, this code is obsolete, thanks Evan!
---
Diffs of the changes: (+0 -16)
PPCISelDAGToDAG.cpp | 16
1 files changed, 16 deletions(-)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.172 -> 1.173
---
Log message:
Handle constant addresses more efficiently, folding the low bits into the
disp field of the load/store if possible. This compiles
CodeGen/PowerPC/load-constant-addr.ll to:
_test:
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.171 -> 1.172
---
Log message:
reenable this hack, the tblgen version isn't quite ready
---
Diffs of the changes: (+16 -0)
PPCISelDAGToDAG.cpp | 16
1 files changed, 16 insertions(+)
Index: llv
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.170 -> 1.171
PPCInstrInfo.td updated: 1.197 -> 1.198
---
Log message:
Use tblgen'd VECTOR_SHUFFLE selection code.
---
Diffs of the changes: (+2 -19)
PPCISelDAGToDAG.cpp | 16
PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.169 -> 1.170
PPCISelLowering.cpp updated: 1.103 -> 1.104
PPCInstrInfo.td updated: 1.196 -> 1.197
---
Log message:
Add support for generating vspltw, instead of a vperm instruction with a
constant pool load. This gene
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.167 -> 1.168
---
Log message:
Save/restore VRSAVE once per function, not once per block.
---
Diffs of the changes: (+52 -39)
PPCISelDAGToDAG.cpp | 91 +---
1 files
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.166 -> 1.167
---
Log message:
Fix an off by one error that caused PPC LLC failures last night.
---
Diffs of the changes: (+1 -1)
PPCISelDAGToDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Inde
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.164 -> 1.165
PPCInstrInfo.td updated: 1.181 -> 1.182
PPCRegisterInfo.cpp updated: 1.43 -> 1.44
PPCRegisterInfo.td updated: 1.29 -> 1.30
---
Log message:
For functions that use vector registers, save VRSAVE, mark used
r
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.160 -> 1.161
---
Log message:
Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668:
http://llvm.cs.uiuc.edu/PR668 .
---
Diffs of the changes: (+59 -18)
PPCISelDAGToDAG.cpp | 77
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.159 -> 1.160
---
Log message:
Implement selection of inline asm memory operands
---
Diffs of the changes: (+29 -0)
PPCISelDAGToDAG.cpp | 29 +
1 files changed, 29 insertions(+)
Inde
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.158 -> 1.159
PPCInstrInfo.td updated: 1.176 -> 1.177
---
Log message:
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
signi
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.157 -> 1.158
---
Log message:
If the false case is the current basic block, then this is a self loop.
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, inver
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.156 -> 1.157
---
Log message:
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
---
Diffs of the changes: (+79 -68)
PPCISelDAGToDAG.cpp | 147 +++
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.155 -> 1.156
---
Log message:
Change Select() from
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
---
Diffs of the changes: (+133 -80)
PPCISelDAGToDAG.cpp | 213 ++
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.154 -> 1.155
---
Log message:
Complex pattern isel code shouldn't select nodes.
---
Diffs of the changes: (+9 -9)
PPCISelDAGToDAG.cpp | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
I
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.153 -> 1.154
---
Log message:
Use SelectRoot() as entry of any tblgen based isel.
---
Diffs of the changes: (+2 -1)
PPCISelDAGToDAG.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.152 -> 1.153
PPCISelLowering.cpp updated: 1.73 -> 1.74
PPCISelLowering.h updated: 1.17 -> 1.18
---
Log message:
Use PPCISD::CALL instead of ISD::CALL
---
Diffs of the changes: (+11 -6)
PPCISelDAGToDAG.cpp |3 +
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.150 -> 1.151
PPCISelLowering.cpp updated: 1.66 -> 1.67
---
Log message:
Use the default impl of DYNAMIC_STACKALLOC, allowing us to delete some code.
---
Diffs of the changes: (+4 -41)
PPCISelDAGToDAG.cpp | 38 --
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.148 -> 1.149
---
Log message:
remove dead code
---
Diffs of the changes: (+2 -25)
PPCISelDAGToDAG.cpp | 27 ++-
1 files changed, 2 insertions(+), 25 deletions(-)
Index: llvm/lib/Target/
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.149 -> 1.150
---
Log message:
these cases are autogenerated
---
Diffs of the changes: (+0 -28)
PPCISelDAGToDAG.cpp | 28
1 files changed, 28 deletions(-)
Index: llvm/lib/Target/Pow
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.147 -> 1.148
---
Log message:
Fix a compile crash building MultiSource/Applications/d with the new front-end.
The PPC backend was generating random shift counts in this case, due to an
uninitialized variable.
---
Dif
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.145 -> 1.146
PPCISelLowering.cpp updated: 1.51 -> 1.52
PPCISelLowering.h updated: 1.12 -> 1.13
PPCInstrFormats.td updated: 1.62 -> 1.63
PPCInstrInfo.td updated: 1.162 -> 1.163
PPCRegisterInfo.td updated: 1.27 -> 1.28
--
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.142 -> 1.143
---
Log message:
This is handled by the autogen'd code
---
Diffs of the changes: (+0 -1)
PPCISelDAGToDAG.cpp |1 -
1 files changed, 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.c
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.141 -> 1.142
---
Log message:
Remove a now unused statistic.
---
Diffs of the changes: (+0 -1)
PPCISelDAGToDAG.cpp |1 -
1 files changed, 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.140 -> 1.141
PPCInstrInfo.td updated: 1.158 -> 1.159
---
Log message:
Use the new predicate support that Evan Cheng added to remove some code
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.139 -> 1.140
PPCISelLowering.cpp updated: 1.49 -> 1.50
PPCInstrInfo.td updated: 1.153 -> 1.154
---
Log message:
Add support for TargetConstantPool nodes to the dag isel emitter, and use
them in the PPC backend, to simp
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.138 -> 1.139
---
Log message:
Silence another annoying GCC warning
---
Diffs of the changes: (+1 -1)
PPCISelDAGToDAG.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/P
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.137 -> 1.138
---
Log message:
The basic fneg cases are already autogen'd
---
Diffs of the changes: (+2 -4)
PPCISelDAGToDAG.cpp |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
Index: llvm/lib/Targ
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.134 -> 1.135
---
Log message:
Make sure these get added into the codegenmap when appropriate
---
Diffs of the changes: (+5 -4)
PPCISelDAGToDAG.cpp |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.133 -> 1.134
---
Log message:
Fix a regression caused by a patch earlier today
---
Diffs of the changes: (+2 -1)
PPCISelDAGToDAG.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/lib/Ta
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.132 -> 1.133
---
Log message:
Use a getCopyToReg() variant to generate a flaggy CopyToReg node.
---
Diffs of the changes: (+2 -8)
PPCISelDAGToDAG.cpp | 10 ++
1 files changed, 2 insertions(+), 8 deletion
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.131 -> 1.132
---
Log message:
SelectNodeTo now returns N. Use it instead of return N directly.
---
Diffs of the changes: (+81 -108)
PPCISelDAGToDAG.cpp | 189 ++--
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.130 -> 1.131
---
Log message:
First chunk of actually generating vector code for packed types. These
changes allow us to generate the following code:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.129 -> 1.130
PPCISelLowering.cpp updated: 1.42 -> 1.43
README.txt updated: 1.38 -> 1.39
---
Log message:
Enable global address legalization, fixing a todo and allowing the removal
of some code. This exposes the implic
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.128 -> 1.129
---
Log message:
Teach the selector to fold lo(g) into load instruction immediate fields
---
Diffs of the changes: (+8 -0)
PPCISelDAGToDAG.cpp |8
1 files changed, 8 insertions(+)
Index
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.127 -> 1.128
PPCISelLowering.cpp updated: 1.40 -> 1.41
PPCISelLowering.h updated: 1.9 -> 1.10
PPCInstrInfo.td updated: 1.140 -> 1.141
---
Log message:
Add an initial hack at legalizing GlobalAddress into the appropriat
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.126 -> 1.127
PPCISelLowering.cpp updated: 1.39 -> 1.40
---
Log message:
When lowering direct calls, lower them to use a targetglobaladress directly
instead of a globaladdress. This has no effect on the generated code
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.124 -> 1.125
---
Log message:
Don't emit "32" for unordered comparison
---
Diffs of the changes: (+4 -2)
PPCISelDAGToDAG.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.123 -> 1.124
---
Log message:
add a hack to get code with ordered comparisons working. This hack is
tracked as PR642: http://llvm.cs.uiuc.edu/PR642
---
Diffs of the changes: (+12 -12)
PPCISelDAGToDAG.cpp | 24
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.122 -> 1.123
PPCInstrInfo.td updated: 1.137 -> 1.138
---
Log message:
add support for branch on ordered/unordered.
---
Diffs of the changes: (+21 -0)
PPCISelDAGToDAG.cpp | 17 +
PPCInstrInfo.td
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.121 -> 1.122
PPCInstrInfo.td updated: 1.136 -> 1.137
---
Log message:
autogen undef
---
Diffs of the changes: (+6 -11)
PPCISelDAGToDAG.cpp |8
PPCInstrInfo.td |9 ++---
2 files changed, 6
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.120 -> 1.121
PPCInstrInfo.td updated: 1.134 -> 1.135
---
Log message:
Autogen fsel
---
Diffs of the changes: (+6 -14)
PPCISelDAGToDAG.cpp | 12
PPCInstrInfo.td |8 ++--
2 files changed,
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.119 -> 1.120
PPCInstrInfo.td updated: 1.133 -> 1.134
---
Log message:
Autogen a few new ppc-specific nodes
---
Diffs of the changes: (+11 -15)
PPCISelDAGToDAG.cpp | 12
PPCInstrInfo.td | 14 ++
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.118 -> 1.119
---
Log message:
The dag isel generator generates this now
---
Diffs of the changes: (+0 -32)
PPCISelDAGToDAG.cpp | 32
1 files changed, 32 deletions(-)
Index: llv
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.117 -> 1.118
---
Log message:
Be a bit more paranoid about calling SelectNodeTo
---
Diffs of the changes: (+11 -7)
PPCISelDAGToDAG.cpp | 18 +++---
1 files changed, 11 insertions(+), 7 deletions(-)
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.116 -> 1.117
---
Log message:
Fix a couple of minor bugs. The first fixes povray, the second fixes things
if the dag combiner isn't run
---
Diffs of the changes: (+9 -3)
PPCISelDAGToDAG.cpp | 12 +---
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