Mersenne: V20.1.1 P-1 Factoring

2000-03-24 Thread Hoogendoorn, Sander
The folowing exponents where factored by P-1, but why are the bounds so different? The first had a chance of 1.77% and the other two about 3.7% to find a factor . UID: sanderh/PC, M5542549 completed P-1, B1=7, B2=7, WW1: 8F7EF481 UID: sanderh/PC, M5542723 completed P-1, B1=6,

Mersenne: V20 beta for Linux

2000-03-24 Thread George Woltman
Hi all, As requested, I've ported the v20 beta to Linux. Please let me know of any problems. You can download it from ftp://entropia.com/gimps/v20/mprime.tgz or ftp://entropia.com/gimps/v20/sprime.tgz Regards, George _

Mersenne: (no subject)

2000-03-24 Thread EWMAYER
There's previously been several posts discussing the performance penalty one suffers when running multiple LL tests on a multiprocessor system with a single shared system bus. It would be interesting to see whether this penalty could be alleviated in a reasonably cost-effective fashion through

RE: Mersenne: L2 Cache size

2000-03-24 Thread Aaron Blosser
There's previously been several posts discussing the performance penalty one suffers when running multiple LL tests on a multiprocessor system with a single shared system bus. It would be interesting to see whether this penalty could be alleviated in a reasonably cost-effective fashion through

RE: Mersenne: (no subject)

2000-03-24 Thread Willmore, David
There's previously been several posts discussing the performance penalty one suffers when running multiple LL tests on a multiprocessor system with a single shared system bus. It would be interesting to see whether this penalty could be alleviated in a reasonably cost-effective fashion

RE: Mersenne: L2 Cache size

2000-03-24 Thread Willmore, David
And dont the K6-III and Athlon support an L3 design, using slower memory of course, but dedicated to each CPU so eliminating bus contention? Of course, the K6-III doesn't do SMP, but the Athlon supports it, doesn't it? Are there any SMP motherboards out there yet for the Athlon? The

RE: Mersenne: L2 Cache size

2000-03-24 Thread Aaron Blosser
The Athlon not only supports SMP, but it does it the, IMHO, Right Way(tm). They use a point to point bus between the processor and the core logic. Hence, a SMP Athlon system has no shared bus. Each processor gets a pipe to the core logic and it has however many pipes to memory/IO that it wants.

Re: Memory bus congestion (Was: Mersenne: (no subject))

2000-03-24 Thread Brian J. Beesley
On 24 Mar 00, at 15:44, [EMAIL PROTECTED] wrote: I suspect for LL tests in the ~10M range, this happy medium may be as 'small' as 1-2MB. Are PC systems with L2 caches in this size range available? If so, how much of a premium does one pay for the extra cache? Ernst, your Mlucas program has a

Mersenne: Responding To Several Queries About Quantum Computing:

2000-03-24 Thread Stefan Struiker
TeamG: For some of the latest of the latest on QC, see the link: http://www.wired.com/news/technology/0,1282,35121,00.html There is also the book THE FEYNMAN PROCESSOR, in paperback, by G.J. Milburn, for an overview. Regards, Stefanovic

Re: Mersenne: L2 Cache size

2000-03-24 Thread John R Pierce
I do wonder what the speeds would be like for Prime95/NTPrime on a 1MB vs. 2MB Xeon... Anyone have the chance to test that out? I just got my hands on a dual P3-Xeon 600MHz 256kB cache 133Mhz bus machine at work, running Linux. I'll have to play with some benchmarking next week. -jrp