George wrote:
One correction to my previous post. I said that the latency to
access the L1 data cache was 2 clocks. This is correct for integer
instructions only. For floating point and SSE2 instructions the latency
is 6 clocks! Interestingly, the L2 cache latency is 7 clocks for
For those interested, I have a machine capable of running the simulator if
you need something tested or measured. Contact me by personal email.
-Original Message-
From: Henk Stokhorst [SMTP:[EMAIL PROTECTED]]
Sent: Friday, October 06, 2000 1:22 PM
To: [EMAIL PROTECTED]
Subject:
Hello, all.
I'm curious if anyone has any preliminary performance figures for Athlon
processors on the new crop of DDR MBs. If noone has any data, I guess I'll
have to go out and buy one. :)
Cheers,
David
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All benchmarks say is that "It's good for *this* application". I've heard
that it speeds up mersenne calculations on some MBs. Now, that's nice, but
if it doesn't speed it up enough vs its cost. That's the question.
I'm just going to hold my breath for DDR-SDRAM. Cheaper, faster, better
I only DC with my Alphas--heck, I only have *two* machines (out of 8) doing
first time LL. :) Don't get me wrong, I'd like to find a new mersenne
prime, but I feel the DCs are underrated in importance. And since this
project is 'vote with your CPU', I am. :)
Thanks for the suggestion. Ernst
If we only had some great P-1 code for the Alpha... Ernst? :)
-Original Message-
From: Stefan Struiker [SMTP:[EMAIL PROTECTED]]
Sent: Friday, June 09, 2000 1:43 PM
To: Willmore, David (VS Central)
Cc: 'Nathan Russell'; [EMAIL PROTECTED]
Subject: Re: Mersenne: What's
Yeah, the manual pages are apparently offline. Will they be back online
soon? I have a machine about to 'go dry' (500MHZ Alpha EV6).
Help.
-Original Message-
From: Barry Stokes [SMTP:[EMAIL PROTECTED]]
Sent: Tuesday, June 06, 2000 4:03 PM
To: [EMAIL PROTECTED]
Subject:
