IA64 is really VLIW (very long instruction word), which is quite different
than traditional sequential RISC. It requires the compiler to do a LOT of
massively parallel pipeline scheduling to achieve optimal results. HP has
a
leg up on this compiler technology as IA64 is based on their
On Thu, Aug 19, 1999 at 05:39:59PM -0700, John R Pierce wrote:
The assembler (micro?) coder had to
keep track of which parts of what execution unit would take how long to do
each instruction, and not rely on results before they were ready. To keep
the machine actually humming along at even close
From: Simon Burge [SMTP:[EMAIL PROTECTED]]
From what I understand of Merced, compiler technology is going to be the
problem. It's probably not unreasonable to expect large performance
increases as the intelligence of compilers (especially the "free"
compilers like gcc and egcs) catches up
I imagine you could significantly speed up the code by keeping
much of the
data in register. REG-REG operations take a lot less time than
a REG-MEM
operation. Should be delicious.
From what I understand of Merced, compiler technology is going to be the
problem. It's probably not
As for the compilers, remember that RISC type architecture is nothing
really
new...and EPIC type stuff has been around a while. There are already
compilers for other systems that contain much of the brains to do the
optimizations already...they just need to get those smarts moved over to
