Re: Mersenne: L2 Cache size

2000-03-24 Thread John R Pierce
> I do wonder what the speeds would be like for Prime95/NTPrime on a 1MB vs. > 2MB Xeon... Anyone have the chance to test that out? I just got my hands on a dual P3-Xeon 600MHz 256kB cache 133Mhz bus machine at work, running Linux. I'll have to play with some benchmarking next week. -jrp ___

RE: Mersenne: L2 Cache size

2000-03-24 Thread Aaron Blosser
>The Athlon not only supports SMP, but it does it the, IMHO, Right Way(tm). >They use a point to point bus between the processor and the core logic. >Hence, a SMP Athlon system has no shared bus. Each processor gets >a pipe to >the core logic and it has however many pipes to memory/IO that it wan

RE: Mersenne: L2 Cache size

2000-03-24 Thread Willmore, David
> And dont the K6-III and Athlon support an L3 design, using slower memory > of > course, but dedicated to each CPU so eliminating bus contention? Of > course, > the K6-III doesn't do SMP, but the Athlon supports it, doesn't it? Are > there any SMP motherboards out there yet for the Athlon? > T

RE: Mersenne: L2 Cache size

2000-03-24 Thread Aaron Blosser
>There's previously been several posts discussing the performance penalty >one suffers when running multiple LL tests on a multiprocessor system >with a single shared system bus. It would be interesting to see >whether this >penalty could be alleviated in a reasonably cost-effective fashion throug