---
src/glsl/nir/glsl_to_nir.cpp | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index af758ce..a471a86 100644
--- a/src/glsl/nir/glsl_to_nir.cpp
+++ b/src/glsl/nir/glsl_to_nir.cpp
@@ -932,11 +932,8 @@
On Monday, June 01, 2015 03:14:26 PM Abdiel Janulgue wrote:
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each binding table offset in
the binding table pool is
On Monday, June 01, 2015 03:14:28 PM Abdiel Janulgue wrote:
When hardware-generated binding tables are enabled, use the hw-generated
binding table format when uploading binding table state.
Normally, the CS will will just consume the binding table pointer commands
as pipelined state. When
On Tuesday, June 02, 2015 12:58:29 AM Kenneth Graunke wrote:
As I mentioned in my reply to patch 3, I think you need some sort of
did the buffer fill up? check. Perhaps make a function to reserve
space, advancing next_offset and returning the offset to use:
static uint32_t
---
src/glsl/nir/nir_lower_atomics.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir_lower_atomics.c b/src/glsl/nir/nir_lower_atomics.c
index f6f8902..0457de6 100644
--- a/src/glsl/nir/nir_lower_atomics.c
+++ b/src/glsl/nir/nir_lower_atomics.c
@@ -109,7 +109,7
On Monday, June 01, 2015 03:14:24 PM Abdiel Janulgue wrote:
v2: Simplify HW binding table bit definitions and magic constants (Topi)
v3: Add Broadwell support.
Cc: kristian.h.kristen...@intel.com
Cc: topi.pohjolai...@intel.com
Cc: kenn...@whitecape.org
Reviewed-by: Topi Pohjolainen
On Tue, Jun 02, 2015 at 11:09:31AM -0700, Anuj Phogat wrote:
and change the name to brw_miptree_choose_tiling().
V3: Remove redundant function parameters. (Topi)
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
Comment made by
Series LGTM.
Reviewed-by: Brian Paul bri...@vmware.com
On 06/02/2015 01:23 PM, Matt Turner wrote:
Both were introduced at the same time. I'm not sure why we needed two.
---
src/mesa/program/ir_to_mesa.cpp | 2 +-
src/mesa/program/prog_instruction.c | 10 +-
On Thu, May 28, 2015 at 11:35 AM, Neil Roberts n...@linux.intel.com wrote:
Previously when setting up the sample instruction for an indirect
sampler the vec4 backend was directly passing the pseudo opcode's
src0. However this isn't actually set to a valid register because
instead the MRF
Appears to have been last used by the i965 driver (removed by commit
098acf6c).
---
src/mesa/program/prog_instruction.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/mesa/program/prog_instruction.h
b/src/mesa/program/prog_instruction.h
index 3ada857..3518f6c 100644
---
It was 2 bits to accommodate SATURATE_PLUS_MINUS_ONE (removed by commit
09b566e1). A similar change was made to TGSI recently in commit
e1c4e8aa.
Reducing the size from 2 bits to 1 reduces the size of the bit fields
from 17 bits to 16, which is a much nicer number.
---
Both were introduced at the same time. I'm not sure why we needed two.
---
src/mesa/program/ir_to_mesa.cpp | 2 +-
src/mesa/program/prog_instruction.c | 10 +-
src/mesa/program/prog_instruction.h | 14 +++---
src/mesa/program/program_parse.y| 6 +++---
4 files changed,
and change the name to brw_miptree_choose_tiling().
V3: Remove redundant function parameters. (Topi)
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
Comment made by Topi on patch 02/22 is fixed in V3 of this patch.
From: Roland Scheidegger srol...@vmware.com
Pretty trivial, fixes the issue that we're expected to be able to blit
stencil surfaces (as the blit just relies on util blitter code which needs
stencil export to do it).
2 piglits skip-pass, 11 fail-pass
---
On 06/01/2015 07:39 AM, Jose Fonseca wrote:
On 01/06/15 14:20, Brian Paul wrote:
---
src/gallium/auxiliary/draw/draw_llvm.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/auxiliary/draw/draw_llvm.c
b/src/gallium/auxiliary/draw/draw_llvm.c
index b9e55af..885c27c 100644
This state tracker implements NVIDIA PerfKit 3.0.1 which is currently
only available on Windows 7+ for desktop graphics cards. A Linux/Android
implementation is provided by NVIDIA but only for NVIDIA Tegra K1.
This Gallium state tracker is loosely based on the VDPAU tracker and since
it uses the
Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
src/util/list.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/util/list.h b/src/util/list.h
index fb566f5..c782ef5 100644
--- a/src/util/list.h
+++ b/src/util/list.h
@@ -116,12 +116,21 @@ static inline void
Signed-off-by: Samuel Pitoiset samuel.pitoi...@gmail.com
---
src/gallium/drivers/nouveau/nv30/nv30_query.c | 3 ---
src/util/list.h | 3 +++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_query.c
Hello,
A series I started a long time ago but now I need some feedbacks. :-)
This state tracker implements NVIDIA PerfKit 3.0.1 which is currently
only available on Windows 7+ for desktop graphics cards. A Linux/Android
implementation is provided by NVIDIA but only for NVIDIA Tegra K1.
This
On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texcompress.c | 22 ++
src/mesa/main/teximage.c| 28
On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/glformats.c | 29 +
1 file changed, 29 insertions(+)
diff --git
On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
v2: alphabetize the extensions.
remove OES ASTC extension.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/extensions.c | 2 ++
On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texcompress.c | 114
1 file changed, 114 insertions(+)
Previously we were leaving this at the default of 64K, which meets the
spec but is too small for some real uses. The hardware can handle up to
128M.
User was complaining about this on freenode ##OpenGL today.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
On Tue, Jun 2, 2015 at 5:22 PM, Chris Forbes chr...@ijw.co.nz wrote:
Previously we were leaving this at the default of 64K, which meets the
spec but is too small for some real uses. The hardware can handle up to
128M.
User was complaining about this on freenode ##OpenGL today.
Does he know
From: Roland Scheidegger srol...@vmware.com
Pretty trivial, fixes the issue that we're expected to be able to blit
stencil surfaces (as the blit just relies on util blitter code which needs
stencil export to do it).
2 piglits skip-pass, 11 fail-pass
v2: prettify, keep different stencil ref value
Buffers with Yf/Ys tiling end up using meta upload / download
paths or the blitter for cases where they used tiled_memcpy paths
in case of Y tiling. This has exposed some bugs in meta path. To
avoid any piglit regressions on SKL this patch keeps the Yf/Ys
tiling disabled at the moment.
V3: Make
On 3 June 2015 at 05:52, srol...@vmware.com wrote:
From: Roland Scheidegger srol...@vmware.com
Looks good to me,
Reviewed-by: Dave Airlie airl...@redhat.com
Pretty trivial, fixes the issue that we're expected to be able to blit
stencil surfaces (as the blit just relies on util blitter code
Some hardware reads only the low 16-bits even if the type is UD, but
other hardware like Cherryview can't handle this.
Fixes spec@arb_gpu_shader5@execution@sampler_array_indexing@fs-simple on
Cherryview.
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
1 file changed, 1 insertion(+), 1
Patch sets the alignments for texture and renderbuffer surfaces.
V3: Make changes inside horizontal_alignment() and
vertical_alignment() (Topi)
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
Cc: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/mesa/drivers/dri/i965/gen8_surface_state.c
On Tue, Jun 2, 2015 at 4:04 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers.
It can be later turned on for other tiling patterns (X,Y) too.
V3: Flush in between sequential fast copy blits.
Fix src/dst alignment
This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers.
It can be later turned on for other tiling patterns (X,Y) too.
V3: Flush in between sequential fast copy blits.
Fix src/dst alignment requirements.
Make can_fast_copy_blit() helper.
Use ffs(), is_power_of_two()
On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
v2: remove extra newline.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/format_info.py | 2 ++
src/mesa/main/formats.c | 28
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
Cc: Ben Widawsky b...@bwidawsk.net
---
Patch can be squashed with 17/22. I kept it separate for easy review.
src/mesa/drivers/dri/i965/intel_blit.c | 93 ++
1 file changed, 61 insertions(+), 32 deletions(-)
diff
Reviewed-by: Matt Turner matts...@gmail.com
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
After discussion on IRC, this seems reasonable to me. Unfortunate that
CHV is fussy.
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Wed, Jun 3, 2015 at 1:24 PM, Matt Turner matts...@gmail.com wrote:
Some hardware reads only the low 16-bits even if the type is UD, but
other hardware like
I'm very confused here. It seems pretty clear that since the command has been
introduced with support for MOCS, MOCS lives at bit 8 of dword 0 for all
constant buffers. The error has existed since forever AFAICT.
No piglit regressions or fixes:
On Tuesday, June 02, 2015 08:07:50 PM Ben Widawsky wrote:
I'm very confused here. It seems pretty clear that since the command has been
introduced with support for MOCS, MOCS lives at bit 8 of dword 0 for all
constant buffers. The error has existed since forever AFAICT.
No piglit regressions
On Wednesday, June 03, 2015 12:22:43 PM Chris Forbes wrote:
Previously we were leaving this at the default of 64K, which meets the
spec but is too small for some real uses. The hardware can handle up to
128M.
User was complaining about this on freenode ##OpenGL today.
Signed-off-by: Chris
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 28a19bd..902f239 100644
---
lower_phis_to_scalar() pass recurses the instruction dependence graph to
determine if all the sources of a given instruction are scalarizable.
To prevent cycles, it temporary marks the phi instruction before recursing in,
then updates the entry with the resulting value. However, it does not
On 02/06/15 13:30, Tapani Pälli wrote:
Patch fixes special cases with gl_VertexID and sets all builtin
variables locations as '-1' as specified by the extension spec.
Fixes ES 3.1 conformance test failure:
ES31-CTS.program_interface_query.input-built-in
Signed-off-by: Tapani Pälli
On 06/02/2015 01:42 PM, Eduardo Lima Mitev wrote:
lower_phis_to_scalar() pass recurses the instruction dependence graph to
determine if all the sources of a given instruction are scalarizable.
To prevent cycles, it temporary marks the phi instruction before recursing in,
then updates the entry
Both of these look good and are:
Reviewed-by: Thomas Helland thomashellan...@gmail.com
2015-06-02 11:37 GMT+02:00 Timothy Arceri t_arc...@yahoo.com.au:
---
src/glsl/nir/glsl_to_nir.cpp | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp
On 06/02/2015 11:25 AM, Kenneth Graunke wrote:
On Tuesday, June 02, 2015 12:58:29 AM Kenneth Graunke wrote:
As I mentioned in my reply to patch 3, I think you need some sort of
did the buffer fill up? check. Perhaps make a function to reserve
space, advancing next_offset and returning the
Actually, having said that I think it would make more sense to change
the line to:
return brw-gen = 9 ? j * 4 : j;
The 4 that it was returning for Gen9 is supposed to represent the block
height and I don't think there's any reason to hard-code it seeing as we
are now querying the block
On 06/02/2015 11:05 AM, Kenneth Graunke wrote:
On Monday, June 01, 2015 03:14:24 PM Abdiel Janulgue wrote:
v2: Simplify HW binding table bit definitions and magic constants (Topi)
v3: Add Broadwell support.
Cc: kristian.h.kristen...@intel.com
Cc: topi.pohjolai...@intel.com
Cc:
Both are
Reviewed-by: Connor Abbott cwabbo...@gmail.com
On Tue, Jun 2, 2015 at 5:37 AM, Timothy Arceri t_arc...@yahoo.com.au wrote:
---
src/glsl/nir/glsl_to_nir.cpp | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp
Patch fixes special cases with gl_VertexID and sets all builtin
variables locations as '-1' as specified by the extension spec.
Fixes ES 3.1 conformance test failure:
ES31-CTS.program_interface_query.input-built-in
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
---
https://bugs.freedesktop.org/show_bug.cgi?id=90817
Jon TURNEY jon.tur...@dronecode.org.uk changed:
What|Removed |Added
CC|
https://bugs.freedesktop.org/show_bug.cgi?id=90817
--- Comment #4 from Tom Hughes t...@compton.nu ---
Created attachment 116243
-- https://bugs.freedesktop.org/attachment.cgi?id=116243action=edit
Output of glxinfo run remotely with patch
--
You are receiving this mail because:
You are the QA
https://bugs.freedesktop.org/show_bug.cgi?id=90817
--- Comment #3 from Tom Hughes t...@compton.nu ---
Created attachment 116242
-- https://bugs.freedesktop.org/attachment.cgi?id=116242action=edit
Patch to loosen checking of visuals
--
You are receiving this mail because:
You are the QA
On 06/02/2015 09:31 AM, Kenneth Graunke wrote:
On Monday, June 01, 2015 03:14:30 PM Abdiel Janulgue wrote:
This is needed since kernel doesn't support RS context save and
restore on BDW yet. So manually disable hw-generated binding tables
when done using it in the batch. Otherwise the GPU
https://bugs.freedesktop.org/show_bug.cgi?id=90817
Bug ID: 90817
Summary: swrast fails to load with certain remote X servers
Product: Mesa
Version: 10.5
Hardware: Other
OS: All
Status: NEW
Severity:
https://bugs.freedesktop.org/show_bug.cgi?id=90817
--- Comment #1 from Tom Hughes t...@compton.nu ---
Created attachment 116240
-- https://bugs.freedesktop.org/attachment.cgi?id=116240action=edit
Output of glxinfo run locally on the X server
--
You are receiving this mail because:
You are the
https://bugs.freedesktop.org/show_bug.cgi?id=90817
--- Comment #2 from Tom Hughes t...@compton.nu ---
Created attachment 116241
-- https://bugs.freedesktop.org/attachment.cgi?id=116241action=edit
Output of glxinfo run remotely without patch
--
You are receiving this mail because:
You are the
Reviewed-by: Jason Ekstrand ja...@jlekstrand.net
On Tue, Jun 2, 2015 at 2:35 AM, Timothy Arceri t_arc...@yahoo.com.au wrote:
---
src/glsl/nir/nir_lower_atomics.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir_lower_atomics.c
Good work on finding this!
Reviewed-by: Jason Ekstrand jason.ekstr...@intel.com
On Tue, Jun 2, 2015 at 4:42 AM, Eduardo Lima Mitev el...@igalia.com wrote:
lower_phis_to_scalar() pass recurses the instruction dependence graph to
determine if all the sources of a given instruction are
On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
This is necesary to initialize the gl_texture_image struct.
From the KHR_texture_compression_astc_ldr spec:
Added to Section 3.8.6, Compressed Texture Images
Add the
On Tuesday, June 02, 2015 03:23:35 PM Abdiel Janulgue wrote:
On 06/02/2015 09:31 AM, Kenneth Graunke wrote:
On Monday, June 01, 2015 03:14:30 PM Abdiel Janulgue wrote:
This is needed since kernel doesn't support RS context save and
restore on BDW yet. So manually disable hw-generated
Hello,
I am looking to participate in the X.org Evoc program this holiday and I
wish to know if anyone is willing to mentor my Project
https://docs.google.com/document/d/1Y5flvgsJg5s6XUfTP955qKDbhG0ldXBCjGd-YROtTtM/edit.
Looks like one of my potential mentors will not be predisposed to
assist
On Monday, June 01, 2015 03:14:25 PM Abdiel Janulgue wrote:
This is passed on the kernel to enable the resource streamer enable bit
on MI_BATCHBUFFER_START
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
On Monday, June 01, 2015 03:14:30 PM Abdiel Janulgue wrote:
This is needed since kernel doesn't support RS context save and
restore on BDW yet. So manually disable hw-generated binding tables
when done using it in the batch. Otherwise the GPU would no longer
accept software binding tables
On Monday, June 01, 2015 03:14:27 PM Abdiel Janulgue wrote:
Unlike normal software binding tables where the driver has to manually
generate and fill a binding table array which are then uploaded to the
hardware, the resource streamer instead presents the driver with an option
to fill out slots
https://bugs.freedesktop.org/show_bug.cgi?id=90797
--- Comment #2 from Tapani Pälli lem...@gmail.com ---
Created attachment 116229
-- https://bugs.freedesktop.org/attachment.cgi?id=116229action=edit
patch to fix the issue
this fixes the issue, will have to test with different override
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