On Tue, May 3, 2016 at 3:28 PM, Francisco Jerez wrote:
> Matt Turner writes:
>
>> Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on
>> Gen >= 8 platforms. This patch avoids the GPU hangs, but does not
>> implement a full work around for the restriction (dispatch_width == 16
On Tue, May 03, 2016 at 05:24:02PM +0100, Daniel Stone wrote:
> On 3 May 2016 at 14:52, Daniel Vetter wrote:
> > Having read the thread I think fixing up the validation part on the
> > compositor side would be the correct fix short term for this. That will
> > keep all options open for the future
total instructions in shared programs: 8508434 -> 8505467 (-0.03%)
instructions in affected programs: 84569 -> 81602 (-3.51%)
helped: 231
total cycles in shared programs: 64154656 -> 64105302 (-0.08%)
cycles in affected programs: 524474 -> 475120 (-9.41%)
helped: 183
HURT: 48
total spills in shar
On Tue, May 3, 2016 at 6:16 PM, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> From: Connor Abbott
>>
>> Work based on registers read/written instead of dispatch_width, so that
>> the interferences are added for 64-bit sources/destinations as well.
>> ---
>> src/mesa/drivers/dr
From: Neil Roberts
Adds an optimisation pass which recognises the LD sampler message type
when the LOD parameter is either a constant zero or not given and
replaces it with the LD_LZ message type. This is the same but the LOD
is hardcoded to zero and doesn't need to be in the message. This can
be
total instructions in shared programs: 8522159 -> 8505846 (-0.19%)
instructions in affected programs: 746750 -> 730437 (-2.18%)
helped: 3159
total cycles in shared programs: 64374090 -> 64119396 (-0.40%)
cycles in affected programs: 9699070 -> 9444376 (-2.63%)
helped: 2205
HURT: 719
total spills
The next patch will add support for recognizing sample_lz, whose lod
argument is in a different location in the payload. This patch
generalizes the function to handle that (and renames it opt_sample_lz
because sample_lz is a much more important thing to recognize).
---
src/mesa/drivers/dri/i965/br
Patch 2 and 3 are:
Reviewed-by: Eduardo Lima Mitev
I barely know about coccinelle scripts so I will let others look at
first patch.
Thanks
Eduardo
On 05/04/2016 06:15 AM, Thomas Hindoe Paaboel Andersen wrote:
> ---
> src/mesa/main/readpix.c | 3 +--
> src/mesa/main/texgetimage.c | 3 +--
>
Good catch!
Reviewed-by: Eduardo Lima Mitev
On 05/04/2016 05:48 AM, Thomas Hindoe Paaboel Andersen wrote:
> The assert was null checking dest_arr_parent twice. The intention
> seems to be to check both dest_ and src_.
>
> Added in d3636da9
> ---
> v2:
> Fix the assert rather than checking bot
The kernel is now more strict with the class ids it exposes, so we need
to check the G98 and MCP89 classes as well as the GT215 class. This
effectively caused us to decide there were no decoding capabilities on
newer kernel for VP3 chips.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9525
Instead of using the LOAD_PAYLOAD instruction (emitted through the
emit_transpose() helper that is no longer useful and this commit
removes) which had to be marked force_writemask_all in some cases,
emit a series of moves to apply proper channel enable signals to the
destination. Until now lower_s
Jordan Justen writes:
> On 2016-05-03 05:21:49, Samuel Iglesias Gonsálvez wrote:
>> Hello,
>>
>> This series adds the final bits to support arb_gpu_shader_fp64 in the
>> i965 scalar backend for BDW+ hardware. It sits on top of the previous
>> series we sent last week [0] and which is going throu
---
src/gallium/drivers/freedreno/freedreno_resource.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c
b/src/gallium/drivers/freedreno/freedreno_resource.c
index 99affc4..4455818 100644
--- a/src/gallium/drivers/freedreno/fr
Adds a coccinelle dir for semantic patches. The first patch here
just removes null checks before calling free.
To create a patch call e.g.:
spatch --sp-file null-check-before-free.cocci --dir ../src > patch
---
coccinelle/null-check-before-free.cocci | 6 ++
1 file changed, 6 insertions(+)
c
---
src/mesa/main/readpix.c | 3 +--
src/mesa/main/texgetimage.c | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
index 882d863..1cb06c7 100644
--- a/src/mesa/main/readpix.c
+++ b/src/mesa/main/readpix.c
@@ -608,8 +608,7
The assert was null checking dest_arr_parent twice. The intention
seems to be to check both dest_ and src_.
Added in d3636da9
---
v2:
Fix the assert rather than checking both in the if(). Hat tip to Ilia.
src/compiler/nir/nir_lower_var_copies.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
On Tue, 2016-05-03 at 20:43 -0400, Tom Stellard wrote:
> On Mon, May 02, 2016 at 01:11:18AM -0400, Jan Vesely wrote:
> >
> > From: Jan Vesely
> >
> > reserve buffer id 2
> >
> >
> > Signed-off-by: Jan Vesely
> > ---
> > needs llvm patches to be of use:
> > https://github.com/jvesely/llvm/tree
Add pthreadstubs to avoid pulling in full pthreads library. GBM will be the
first user.
Signed-off-by: Rob Herring
---
v2:
- new patch
configure.ac | 4
1 file changed, 4 insertions(+)
diff --git a/configure.ac b/configure.ac
index 023110e..f854f6a 100644
--- a/configure.ac
+++ b/configur
This adds map and unmap functions to GBM utilizing the DRIimage extension
mapImage/unmapImage functions or existing internal mapping for dumb
buffers. Unlike prior attempts, this version provides a region to map and
usage flags for the mapping. The operation follows the same semantics as
the galliu
Add mapImage and unmapImage functions to DRIimage extension for mapping
and unmapping DRIimages for CPU access. The caller provides the region of
the image to map and is returned a pointer to the beginning of the region
and the stride (which could be different from the original).
Signed-off-by: Ro
In order to use libgbm for gralloc, add it to the Android build.
Signed-off-by: Rob Herring
---
v2:
- move out gallium lib loading changes
Android.mk | 1 +
src/gbm/Android.mk | 44
2 files changed, 45 insertions(+)
create mode 100644 src/g
GBM needs the same special gallium_dri.so loading as EGL for Android, so
copy over the same hunk from the EGL code.
Signed-off-by: Rob Herring
---
v2:
- new patch, moved from Android build support
src/gbm/backends/dri/gbm_dri.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/gb
In preparation to add public map/unmap functions, rename the existing
gbm_dri_bo_{map,unmap} functions to indicate that they are only for dumb
buffers.
Signed-off-by: Rob Herring
---
v2:
- moved into new patch
src/gbm/backends/dri/gbm_dri.c| 4 ++--
src/gbm/backends/dri/gbm_driint.h | 4 ++-
Implement support for mapImage/unmapImage functions in version 12 of the
DRIimage extension.
Signed-off-by: Rob Herring
---
v2:
- Make READ flag optional
src/gallium/state_trackers/dri/dri2.c | 43 ++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a
Move the defining of DEFAULT_DRIVER_DIR path to a common location so both
EGL and GBM can use it.
Signed-off-by: Rob Herring
---
v2:
- new patch
Android.common.mk | 7 +++
src/egl/Android.mk | 7 ---
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/Android.common.mk b/And
This series adds map and unmap functions to GBM. These are needed to
provide a device independent buffer allocation interface to Android's
gralloc.
Open questions:
- Need to flush context on unmap?
- Need fences for gralloc lockAsync support?
Major changes from v1[1]:
- Further split up patches
-
In preparation to add Android build support, split out the source file
lists to Makefile.sources
Signed-off-by: Rob Herring
---
v2:
- fix missing Makefile.sources include
- remove spurious whitespace change
src/gbm/Makefile.am | 12
src/gbm/Makefile.sources | 12
On Tue, May 3, 2016 at 4:54 PM, Francisco Jerez
wrote:
> Jason Ekstrand writes:
>
> > On Tue, May 3, 2016 at 4:24 PM, Jason Ekstrand
> wrote:
> >
> >>
> >>
> >> On Tue, May 3, 2016 at 4:18 PM, Kenneth Graunke
> >> wrote:
> >>
> >>> On Tuesday, May 3, 2016 3:00:26 PM PDT Jason Ekstrand wrote:
>
On Mon, May 02, 2016 at 01:11:18AM -0400, Jan Vesely wrote:
> From: Jan Vesely
>
> reserve buffer id 2
>
>
> Signed-off-by: Jan Vesely
> ---
> needs llvm patches to be of use:
> https://github.com/jvesely/llvm/tree/eg-const
>
> passes program-scope-arrays piglit and fixes all builtin function
On Tue, May 3, 2016 at 5:21 AM, Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:
> From: Iago Toral Quiroga
>
> We were not accounting for reg_suboffset in the check for the start
> of the region. This meant that would allow copy-propagation even if
> the dst wrote to sub_regoffset 4 and
On 2016-05-03 05:21:55, Samuel Iglesias Gonsálvez wrote:
> From: Iago Toral Quiroga
>
> We were not accounting for reg_suboffset in the check for the start
> of the region. This meant that would allow copy-propagation even if
> the dst wrote to sub_regoffset 4 and our source read from
> sub_regof
Jason Ekstrand writes:
> On Tue, May 3, 2016 at 4:24 PM, Jason Ekstrand wrote:
>
>>
>>
>> On Tue, May 3, 2016 at 4:18 PM, Kenneth Graunke
>> wrote:
>>
>>> On Tuesday, May 3, 2016 3:00:26 PM PDT Jason Ekstrand wrote:
>>> > There are a few different fixups that we have to do for texture
>>> > des
The series is
Reviewed-by: Matt Turner
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Rob Herring writes:
> On Mon, Apr 25, 2016 at 7:42 AM, Daniel Stone wrote:
>> Hi,
>>
>> On 22 April 2016 at 19:12, Eric Anholt wrote:
>>> I think this needs a longer comment to explain what the interface does:
>>>
>>> "Returns a map of the specified region of a __DRIimage for the specified
>>>
There are a couple of cycle count changes in shader-db, but it's
basically a wash.
However, with the Broadwell scalar TCS backend enabled, many
Shadow of Mordor shaders benefit from this patch. Because we don't
batch up output writes for TCS, vec4 outputs might not have all
components defined. M
Normally, we expect SIMD8 shaders to be more instructions than SIMD4x2
shaders, as it takes four instructions to operate on a vec4, rather than
a single instruction. However, the benefit is that it can process 8
objects per shader thread instead of 2.
Surprisingly, the shader-db statistics show a
shader-db statistics on Broadwell:
total instructions in shared programs: 8963409 -> 8962455 (-0.01%)
instructions in affected programs: 60858 -> 59904 (-1.57%)
helped: 318
HURT: 0
total cycles in shared programs: 71408022 -> 71406276 (-0.00%)
cycles in affected programs: 398416 -> 396670 (-0.44%
This better reflects what it does. I plan to add other ALU
optimizations as well, so the old name would be confusing.
In preparation for that, also move the file comments about csels
above the opt_undef_csel function, and delete the ones about there
not being other optimizations.
Signed-off-by:
According to Timothy, using program_string_id == 0 to identify the
passthrough TCS is going to be problematic for his shader cache work.
So, change it to strcmp() the name at visitor creation time.
Cc: timothy.arc...@collabora.com
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw
On Tue, May 3, 2016 at 4:24 PM, Jason Ekstrand wrote:
>
>
> On Tue, May 3, 2016 at 4:18 PM, Kenneth Graunke
> wrote:
>
>> On Tuesday, May 3, 2016 3:00:26 PM PDT Jason Ekstrand wrote:
>> > There are a few different fixups that we have to do for texture
>> > destinations that re-arrange channels,
On Tue, May 3, 2016 at 4:18 PM, Kenneth Graunke
wrote:
> On Tuesday, May 3, 2016 3:00:26 PM PDT Jason Ekstrand wrote:
> > There are a few different fixups that we have to do for texture
> > destinations that re-arrange channels, fix hardware vs. API mismatches,
> or
> > just shrink the result to
On 2016-05-03 05:21:54, Samuel Iglesias Gonsálvez wrote:
> From: Iago Toral Quiroga
>
> The current code ignores the suboffet in the instruction's source
> and just uses the one from the constant. This is not correct
> when the instruction's source is accessing the constant with a
> different typ
On Tuesday, May 3, 2016 3:00:26 PM PDT Jason Ekstrand wrote:
> There are a few different fixups that we have to do for texture
> destinations that re-arrange channels, fix hardware vs. API mismatches, or
> just shrink the result to fit in the NIR destination. These were all being
> done in a somew
Samuel Iglesias Gonsálvez writes:
> From: Connor Abbott
>
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 729c7a0..45afd1a 100644
> --
Should the subject say something about not allowing a type size
change?
-Jordan
On 2016-05-03 05:21:53, Samuel Iglesias Gonsálvez wrote:
> From: Iago Toral Quiroga
>
> When source modifiers are present and the types of the source and
> the entry's source are different, there are certain cases i
Samuel Iglesias Gonsálvez writes:
> From: Connor Abbott
>
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index ac170d5..729c7a0 100644
> --- a/
On 2016-05-03 05:21:52, Samuel Iglesias Gonsálvez wrote:
> From: Iago Toral Quiroga
>
> Specifically, consider the size of the data type of the operand to compute
> the number of registers written.
> ---
> src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 2 +-
> 1 file changed, 1 insertio
From: Robert Foss
The return variable was not set for failure paths.
It has now been changed to VK_ERROR_INITIALIZATION_FAILED
for failure paths.
Coverity: 1358944
Signed-off-by: Robert Foss
---
src/intel/vulkan/anv_wsi_wayland.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
d
From: Robert Foss
Make sure that memory allocated is free'd.
Previously only the contents of the variable
galliumvm was free'd, not the actual memory
it points to.
Coverity: 1358907
Signed-off-by: Robert Foss
---
src/gallium/drivers/swr/swr_shader.cpp | 1 +
1 file changed, 1 insertion(+)
dif
Matt Turner writes:
> Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on
> Gen >= 8 platforms. This patch avoids the GPU hangs, but does not
> implement a full work around for the restriction (dispatch_width == 16
> is an imperfect proxy).
>
Sounds like for a proper fix we co
On Mon, Apr 25, 2016 at 7:42 AM, Daniel Stone wrote:
> Hi,
>
> On 22 April 2016 at 19:12, Eric Anholt wrote:
>> I think this needs a longer comment to explain what the interface does:
>>
>> "Returns a map of the specified region of a __DRIimage for the specified
>> usage.
>>
>> flags must always
Samuel Iglesias Gonsálvez writes:
> From: Connor Abbott
>
> Work based on registers read/written instead of dispatch_width, so that
> the interferences are added for 64-bit sources/destinations as well.
> ---
> src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 67
> ---
>
The fs_visitor::emit_texture helper originated when we still had both NIR
and IR visitors for the FS backend. Since the old visitor was removed,
emit_texture serves no real purpose beyond arbitrarily splitting
heavily-linked code across two functions.
---
src/mesa/drivers/dri/i965/brw_fs.h
This is where we handle texop_texture_samples so it makes things more
consistent.
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 40 +++-
1 file changed, 19 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i96
We are no longer using anything from GLSL IR in the FS backend.
---
src/mesa/drivers/dri/i965/brw_fs.h | 1 -
src/mesa/drivers/dri/i965/brw_link.cpp | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
inde
There are a few different fixups that we have to do for texture
destinations that re-arrange channels, fix hardware vs. API mismatches, or
just shrink the result to fit in the NIR destination. These were all being
done in a somewhat haphazard manner. This commit replaces all of the
shuffling with
Add a more comprehensive validateUsage() call, checking that the tiling
mode for the __DRIimage.
Signed-off-by: Daniel Stone
Cc: Daniel Vetter
---
src/mesa/drivers/dri/i965/intel_screen.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/sr
This will be used so we can implement a better validateUsage, which
takes neither a screen nor a context.
Signed-off-by: Daniel Stone
Cc: Daniel Vetter
---
src/mesa/drivers/dri/i965/intel_image.h | 2 ++
src/mesa/drivers/dri/i965/intel_screen.c | 22 --
2 files changed, 18
On 03/05/16 22:10, Brian Paul wrote:
If we fail to create a context in the VMware driver we call this function
unconditionally to free a bunch of bit vectors. Instead of asserting on
a null pointer, just no-op.
---
src/gallium/auxiliary/util/u_bitmask.c | 8
1 file changed, 4 inserti
If we fail to create a context in the VMware driver we call this function
unconditionally to free a bunch of bit vectors. Instead of asserting on
a null pointer, just no-op.
---
src/gallium/auxiliary/util/u_bitmask.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/
Oops,
Reviewed-by: Dave Airlie
On 4 May 2016 at 07:01, Mark Janes wrote:
> This prevents a crash when a NULL src is passed with a non-NULL length.
>
> fixes: dEQP-GLES31.functional.debug.object_labels.query_length_only
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95252
>
> Signed-o
This prevents a crash when a NULL src is passed with a non-NULL length.
fixes: dEQP-GLES31.functional.debug.object_labels.query_length_only
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95252
Signed-off-by: Mark Janes
---
src/mesa/main/objectlabel.c | 7 ---
1 file changed, 4 inser
From: Dave Airlie
This fixes both:
GL43-CTS.khr_debug.receiveing_messages
GL43-CTS.khr_debug.groups
which reported off by ones.
Signed-off-by: Dave Airlie
---
src/mesa/main/debug_output.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/debug_output.c b/src/me
On Tue, May 3, 2016 at 4:38 PM, Thomas H.P. Andersen wrote:
>
>
> On Tue, May 3, 2016 at 9:46 PM, Ilia Mirkin wrote:
>>
>> On Tue, May 3, 2016 at 3:32 PM, Thomas Hindoe Paaboel Andersen
>> wrote:
>> > It seems that the intention was to check both for null as they are
>> > dereferenced immediatel
On Tue, May 3, 2016 at 9:46 PM, Ilia Mirkin wrote:
> On Tue, May 3, 2016 at 3:32 PM, Thomas Hindoe Paaboel Andersen
> wrote:
> > It seems that the intention was to check both for null as they are
> > dereferenced immediately after.
> >
> > Added in d3636da9
> > ---
> > src/compiler/nir/nir_lowe
Jason Ekstrand writes:
> From: Connor Abbott
Reviewed-by: Eric Anholt
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On Tue, May 03, 2016 at 02:38:39PM +0100, Daniel Stone wrote:
> This commit broke Weston/KMS, and presumably also xf86-video-modesetting.
>
> In order to use Y-tiled buffers, the kernel requires the tiling mode to
> be explicitly named through the I915_FORMAT_MOD_Y_TILED AddFB2 modifier;
> it disa
Brian Paul writes:
> On 05/02/2016 06:15 PM, Ilia Mirkin wrote:
>> I know I've been sticking commas at the end of enums left and right
>> for the past several years, and haven't heard any complaints. The nice
>> thing about the trailing comma is that you avoid having to change
>> unrelated lines
On Tue, May 3, 2016 at 3:46 PM, Kenneth Graunke wrote:
> On Tuesday, May 3, 2016 3:13:26 PM PDT Connor Abbott wrote:
>> On Tue, May 3, 2016 at 2:52 PM, Kenneth Graunke
> wrote:
>> > On Friday, April 29, 2016 1:29:34 PM PDT Samuel Iglesias Gonsálvez wrote:
>> >> From: Connor Abbott
>> >>
>> >> Wo
On Fri, Apr 29, 2016 at 4:29 AM, Samuel Iglesias Gonsálvez
wrote:
> From: Connor Abbott
>
> Work based on registers read/written instead of dispatch_width, so that
> the interferences are added for 64-bit sources/destinations as well.
> ---
> src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 6
On Tuesday, May 3, 2016 3:13:26 PM PDT Connor Abbott wrote:
> On Tue, May 3, 2016 at 2:52 PM, Kenneth Graunke
wrote:
> > On Friday, April 29, 2016 1:29:34 PM PDT Samuel Iglesias Gonsálvez wrote:
> >> From: Connor Abbott
> >>
> >> Work based on registers read/written instead of dispatch_width, so
On Tue, May 3, 2016 at 3:32 PM, Thomas Hindoe Paaboel Andersen
wrote:
> It seems that the intention was to check both for null as they are
> dereferenced immediately after.
>
> Added in d3636da9
> ---
> src/compiler/nir/nir_lower_var_copies.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-
On Tue, May 3, 2016 at 3:13 PM, Connor Abbott wrote:
> On Tue, May 3, 2016 at 2:52 PM, Kenneth Graunke wrote:
>> On Friday, April 29, 2016 1:29:34 PM PDT Samuel Iglesias Gonsálvez wrote:
>>> From: Connor Abbott
>>>
>>> Work based on registers read/written instead of dispatch_width, so that
>>> t
Tested-by: Mark Janes
Matt Turner writes:
> Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on
> Gen >= 8 platforms. This patch avoids the GPU hangs, but does not
> implement a full work around for the restriction (dispatch_width == 16
> is an imperfect proxy).
>
> Evidentl
It seems that the intention was to check both for null as they are
dereferenced immediately after.
Added in d3636da9
---
src/compiler/nir/nir_lower_var_copies.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_lower_var_copies.c
b/src/compiler/nir/nir_lowe
On Tue, May 3, 2016 at 2:52 PM, Kenneth Graunke wrote:
> On Friday, April 29, 2016 1:29:34 PM PDT Samuel Iglesias Gonsálvez wrote:
>> From: Connor Abbott
>>
>> Work based on registers read/written instead of dispatch_width, so that
>> the interferences are added for 64-bit sources/destinations as
Other than patches 37, 56, and ones you agreed to drop, the series is:
Reviewed-by: Kenneth Graunke
I think you can go ahead and land all except those, and we can land
new solutions for those problems afterwards.
We still need to fix the horiz_offset problem, and I think Curro's
subscript() help
On Friday, April 29, 2016 1:29:34 PM PDT Samuel Iglesias Gonsálvez wrote:
> From: Connor Abbott
>
> Work based on registers read/written instead of dispatch_width, so that
> the interferences are added for 64-bit sources/destinations as well.
> ---
> src/mesa/drivers/dri/i965/brw_fs_reg_allocate
On Monday, April 25, 2016 9:08:38 AM PDT Samuel Iglesias Gonsálvez wrote:
> From: "Juan A. Suarez Romero"
>
> When computing the offset in the uniform storage table, take into account
> the size multiplier so double precision matrices are handled correctly.
>
> Signed-off-by: Juan A. Suarez Rome
On 2016-05-03 05:21:51, Samuel Iglesias Gonsálvez wrote:
> From: Iago Toral Quiroga
>
> We should not offset into them based on the relative offset of
> our source and the destination of the instruction we are copy
> propagating from, so we don't turn this:
>
> mov(16) vgrf6:F, vgrf7+0.0<0>:F
>
On Tuesday, May 3, 2016 12:09:33 PM PDT Samuel Iglesias Gonsálvez wrote:
>
> On 02/05/16 23:50, Mark Janes wrote:
> > Samuel Iglesias Gonsálvez writes:
> >
> >> Hello,
> >>
> >> This patch series continues adding arb_gpu_shader_fp64 support to
> >> the Intel driver. Specifically, this targets the
On Monday, May 2, 2016 6:48:18 PM PDT Francisco Jerez wrote:
> This only works if reg.stride == 0 or 1, we need to honour the stride of
> the original register (e.g. by doing reg.stride *= stride) or you'll end
> up taking components not part of the region given as argument. It gets
> messy with A
On 2016-05-03 05:21:50, Samuel Iglesias Gonsálvez wrote:
> From: Iago Toral Quiroga
>
> This can happen if the register already has a non-zero subreg_offset
> when byte_offset() is called.
> ---
> src/mesa/drivers/dri/i965/brw_ir_fs.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a
On 2016-05-03 05:21:49, Samuel Iglesias Gonsálvez wrote:
> Hello,
>
> This series adds the final bits to support arb_gpu_shader_fp64 in the
> i965 scalar backend for BDW+ hardware. It sits on top of the previous
> series we sent last week [0] and which is going through review at the
> moment. Spec
Hi,
On 3 May 2016 at 14:52, Daniel Vetter wrote:
> On Mon, Feb 01, 2016 at 12:48:52PM +0900, Michel Dänzer wrote:
>> As I said before, looking at intel_validate_usage, I suspect the latter.
>
> Just jumping in here, but it's correct atm. Well if we ignore a recent bug
> to enable Y-tiling where m
---
.../drivers/swr/rasterizer/jitter/builder_misc.cpp | 105 +
1 file changed, 24 insertions(+), 81 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp
index 486dad8..3a304ec 100644
Avoid % operator, since we know that curVertex is always incrementing.
---
src/gallium/drivers/swr/rasterizer/core/pa.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/pa.h
b/src/gallium/drivers/swr/rasterizer/core/pa.h
index d3ed279
Fix static code analysis errors found by coverity on Linux
---
.../drivers/swr/rasterizer/common/swr_assert.h | 50 +++---
src/gallium/drivers/swr/rasterizer/core/arena.h| 16 +++
2 files changed, 52 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/swr/r
---
src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
index ba1096d..42b1c3e 100644
--- a/src/gallium/drivers/swr/rasterize
---
src/gallium/drivers/swr/rasterizer/core/frontend.cpp | 5 -
src/gallium/drivers/swr/rasterizer/jitter/JitManager.h | 7 ---
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
b/src/gallium/drivers/swr/rasterizer/core/f
---
.../drivers/swr/rasterizer/common/simdintrin.h | 20 +
.../drivers/swr/rasterizer/core/backend.cpp| 26 +-
src/gallium/drivers/swr/rasterizer/core/backend.h | 7 --
3 files changed, 31 insertions(+), 22 deletions(-)
diff --git a/src/galliu
Fix windows in 32-bit mode when hyperthreading is disabled on Xeons.
Some support for asymmetric processor topologies.
---
.../drivers/swr/rasterizer/core/threads.cpp| 64 --
1 file changed, 47 insertions(+), 17 deletions(-)
diff --git a/src/gallium/drivers/swr/raster
Smallish changes this time around, some changes that hopefully
start improving coverity's opinion of the rasterizer, and a small
performance tweak.
Tim Rowley (11):
swr: [rasterizer] Whitespace cleanup and misc changes
swr: [rasterizer core] Fix threadviz support in buckets
swr: [rasterizer
Storing color hot tile to 8bit w-major stencil format.
---
src/gallium/drivers/swr/rasterizer/memory/StoreTile.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/memory/StoreTile.cpp
b/src/gallium/drivers/swr/rasterizer/memory/StoreTile.
---
src/gallium/drivers/swr/rasterizer/common/os.h | 1 +
src/gallium/drivers/swr/rasterizer/jitter/blend_jit.h | 1 -
src/gallium/drivers/swr/rasterizer/jitter/jit_api.h | 1 -
src/gallium/drivers/swr/rasterizer/scripts/templates/knobs.template |
---
.../drivers/swr/rasterizer/common/formats.cpp | 25 --
.../drivers/swr/rasterizer/common/formats.h| 1 +
.../drivers/swr/rasterizer/core/format_traits.h| 22 +++
3 files changed, 41 insertions(+), 7 deletions(-)
diff --git a/src/gallium/dr
Need to do lazy eval of the threadviz knob since order of globals
is undefined.
---
src/gallium/drivers/swr/rasterizer/common/rdtsc_buckets.cpp | 12
src/gallium/drivers/swr/rasterizer/common/rdtsc_buckets.h | 12 +---
src/gallium/drivers/swr/rasterizer/core/rdtsc_core.cpp
On Tue, 2016-05-03 at 13:50 +0100, Jose Fonseca wrote:
> On 02/05/16 06:15, Jan Vesely wrote:
> >
> > From: Jan Vesely
> >
> > Signed-off-by: Jan Vesely
> > ---
> > src/gallium/auxiliary/util/u_blitter.c| 10 +-
> > src/gallium/auxiliary/util/u_cpu_detect.c | 2 +-
> >
On Tue, May 3, 2016 at 10:52 AM, Leo Liu wrote:
> Stacking frames is for driver that's capable to do dual instances
> encoding. Such feature is not enabled for B frames currently.
>
> Signed-off-by: Leo Liu
> Cc: "11.1 11.2"
Reviewed-by: Alex Deucher
> ---
> src/gallium/state_trackers/omx/vi
On Tue, May 3, 2016 at 9:56 AM, Daniel Vetter wrote:
> On Mon, May 02, 2016 at 06:44:34AM -0400, Rob Clark wrote:
>> On Mon, May 2, 2016 at 2:15 AM, Michel Dänzer wrote:
>> > On 25.04.2016 21:36, Daniel Stone wrote:
>> >> On 20 April 2016 at 00:32, Rob Clark wrote:
>> >>> On Tue, Apr 19, 2016 at
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