[Mesa-dev] [PATCH 08/10] i965/fs: Calculate the (un)spill block size correctly.

Currently the spilling code attempts to guess the scratch message block size from the dispatch width of the shader, which is plain wrong for SIMD-lowered instructions (frequently but not exclusively encountered in SIMD32 shaders) or for instructions with register region data types of size other tha

[Mesa-dev] [PATCH 07/10] i965/fs: Set exec_all on spills not matching the channel layout of the instruction.

This prevents the application of an incorrect channel mask by the scratch write instruction for spilled variables that don't have an exact one-to-one correspondence between channels of the variable and 32-bit components of the scratch write instruction. --- src/mesa/drivers/dri/i965/brw_fs_reg_all

[Mesa-dev] [PATCH 09/10] i965/fs: Allow spilling of non-contiguous registers.

This should be working fine now. --- src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 21 ++--- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index ff40c42..d6

[Mesa-dev] [PATCH 03/10] i965/fs: Apply execution controls from the instruction to scratch messages.

Until now the execution controls (e.g. channel group, force_writemask_all, exec_size) of the instruction had been completely ignored by spilling, even though that can lead to a mismatch between the channel mask applied to the contents of the (un)spilled memory and the GRF source or destination of t

[Mesa-dev] [PATCH 10/10] i965/fs: Mark UBO uniform pull constant loads as force_writemask_all.

This lets the rest of the backend know that the uniform pull constant load opcodes don't respect channel enables -- Without this the register allocator has no way to know that the return payload of a pull constant load is not per-channel and spills of the destination will be broken under non-unifor

[Mesa-dev] [PATCH 05/10] i965/fs: Move scratch block size calculation into the caller of emit_(un)spill.

This makes emit_(un)spill even more stupid by removing the logic that decides what execution size each scratch read or write send message should have and instead relying on the caller to specify an appropriate execution size via the builder argument. This makes sense because the caller will need t

[Mesa-dev] [PATCH 00/12] i965/fs: Spilling fixes.

This series fixes the FS register spilling code to apply correct channel masks to the spilled data regardless of the datatype and execution controls of the generating instruction, which is especially important for instructions manipulating data of type size other than 32 bit (e.g. FP64) or instruct

[Mesa-dev] [PATCH 01/10] i965/fs: Factor out calculation of the block of MRFs reserved for spilling.

And as we're at it fix the calculation to allocate a larger block of registers for 32-wide dispatch. --- src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 54 +++ 1 file changed, 45 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp

[Mesa-dev] [PATCH 04/10] i965/fs: Make emit_spill/unspill static functions taking builder as argument.

This seems cleaner than exposing an implementation detail of brw_fs_reg_allocate.cpp to the world, and will give the caller control over the instruction execution flags (e.g. force_writemask_all) that are applied to the scratch read and write instructions. --- src/mesa/drivers/dri/i965/brw_fs.h

[Mesa-dev] [PATCH 02/10] i965/fs: Fix signedness of local variables and arguments of emit_(un)spill.

To avoid some some spurious warnings about comparison signedness in the following commits. --- src/mesa/drivers/dri/i965/brw_fs.h| 4 ++-- src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 12 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mesa/d

[Mesa-dev] [PATCH 06/10] i965/fs: Set exec_all on unspills.

This makes sure that unspills restore the exact contents of the variable in scratch space into the GRF without applying channel masking, which is incorrect under control flow for things like message headers or vectors of heterogeneous types that don't properly respect channel boundaries. --- src/m

Re: [Mesa-dev] [PATCH 1/5] glsl: fix location and component packing validation on patchs

On Tue, 2016-05-17 at 13:29 +1000, Dave Airlie wrote: > On 17 May 2016 at 13:19, Timothy Arceri > wrote: > > > > These varyings have a separate location domain from per-vertex > > varyings > > and need to be handled separately. > I hit a crash in here hacking on CTS this morning (I was force > en

Re: [Mesa-dev] [PATCH] i965/fs: Add an allow_spilling flag to brw_compile_fs

Jason Ekstrand writes: > On May 16, 2016 6:44 PM, "Francisco Jerez" wrote: >> >> Jason Ekstrand writes: >> >> > This allows us to disable spilling for blorp shaders since blorp state >> > setup doesn't handle spilling. Without this, blorp faisl hard if you > run >> > with INTEL_DEBUG=spill. >>

Re: [Mesa-dev] [PATCH 1/5] glsl: fix location and component packing validation on patchs

On 17 May 2016 at 13:19, Timothy Arceri wrote: > These varyings have a separate location domain from per-vertex varyings > and need to be handled separately. I hit a crash in here hacking on CTS this morning (I was force enabling enhanced_layouts for lols). This series looks good to me. Reviewe

[Mesa-dev] [PATCH 4/5] glsl: include per-patch varyings when generating reserved slot bitfield

--- src/compiler/glsl/link_varyings.cpp | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/compiler/glsl/link_varyings.cpp b/src/compiler/glsl/link_varyings.cpp index 5a99f0c..0a54559 100644 --- a/src/compiler/glsl/link_varyings.cpp +++ b/src/compiler/glsl/link_va

[Mesa-dev] [PATCH 3/5] glsl: don't incorrectly eliminate patches with explicit locations

These varying have a separate location domain from per-vertex varyings and need to be handled separately. --- src/compiler/glsl/linker.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp index bf30b82..70c6317 100644

[Mesa-dev] [PATCH 2/5] glsl: remove remainings tabs in link_varyings.cpp

--- src/compiler/glsl/link_varyings.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/glsl/link_varyings.cpp b/src/compiler/glsl/link_varyings.cpp index 572aba9..5a99f0c 100644 --- a/src/compiler/glsl/link_varyings.cpp +++ b/src/compiler/glsl/link_varyings.c

[Mesa-dev] [PATCH 5/5] glsl: make reserved_varying_slot() static

--- src/compiler/glsl/link_varyings.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/glsl/link_varyings.cpp b/src/compiler/glsl/link_varyings.cpp index 0a54559..c60ee97 100644 --- a/src/compiler/glsl/link_varyings.cpp +++ b/src/compiler/glsl/link_varyings.cpp @

[Mesa-dev] [PATCH 1/5] glsl: fix location and component packing validation on patchs

These varyings have a separate location domain from per-vertex varyings and need to be handled separately. --- src/compiler/glsl/link_varyings.cpp | 3 ++- src/compiler/shader_enums.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/compiler/glsl/link_varyings.cpp

Re: [Mesa-dev] [PATCH] i965/fs: Add an allow_spilling flag to brw_compile_fs

On May 16, 2016 6:44 PM, "Francisco Jerez" wrote: > > Jason Ekstrand writes: > > > This allows us to disable spilling for blorp shaders since blorp state > > setup doesn't handle spilling. Without this, blorp faisl hard if you run > > with INTEL_DEBUG=spill. > > > > Cc: Curro > > Reviewed-by: F

Re: [Mesa-dev] [PATCH 10/11] i965: Allow creating planar YUV __DRIimages

On Wed 11 May 2016, Kristian Høgsberg wrote: > From: Kristian Høgsberg Kristensen > > Lift the resctriction we had before and allow creation of images with > multiple planes. We still require all the planes to be within the same > bo. > --- > src/mesa/drivers/dri/i965/intel_screen.c | 33 >

Re: [Mesa-dev] [PATCH 07/11] i965: Create multiple miptrees for planar YUV images

On Wed 11 May 2016, Kristian Høgsberg wrote: > From: Kristian Høgsberg Kristensen > > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 ++ > src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 +++ > src/mesa/drivers/dri/i965/intel_tex_image.c | 49 > ++- > src/

Re: [Mesa-dev] [PATCH 06/11] i965: Refactor intel_set_texture_image_bo() to create_mt_for_dri_image()

On Wed 11 May 2016, Kristian Høgsberg wrote: > From: Kristian Høgsberg Kristensen > > This function now only creates the mt and we then call > intel_set_texture_image_mt() in intel_image_target_texture_2d() to set > it for the texture image. > --- > src/mesa/drivers/dri/i965/intel_tex_image.c |

[Mesa-dev] [PATCH v3 7/9] gbm: rename gbm_dri_bo_{map, unmap} to gbm_dri_bo_{map, unmap}_dumb

In preparation to add public map/unmap functions, rename the existing gbm_dri_bo_{map,unmap} functions to indicate that they are only for dumb buffers. Signed-off-by: Rob Herring --- v3: - Add missing rename in platform_drm.c src/egl/drivers/dri2/platform_drm.c | 8 src/gbm/backends/dr

Re: [Mesa-dev] [PATCH] mesa/st: add support for NIR as possible driver IR

On Mon, May 16, 2016 at 2:50 PM, Rob Clark wrote: > On Wed, Apr 20, 2016 at 9:40 PM, Eric Anholt wrote: >> Rob Clark writes: >> >>> diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp >>> b/src/mesa/state_tracker/st_glsl_to_nir.cpp >>> new file mode 100644 >>> index 000..c15c537 >>> ---

[Mesa-dev] [Bug 95431] [llvmpipe] [softpipe] piglit layout-location-named-block regression

https://bugs.freedesktop.org/show_bug.cgi?id=95431 Timothy Arceri changed: What|Removed |Added Resolution|--- |DUPLICATE Status|NEW

Re: [Mesa-dev] [PATCH] glsl: Check that layout is non-null before dereferencing.

On Mon, 2016-05-16 at 14:51 -0700, Matt Turner wrote: > It's checked everywhere else. Maybe is_interface implies layout is > non-null. Likely not worth it. Yeah is should only be null for structs. If it shuts up Coverity: Reviewed-by: Timothy Arceri > > Found by Coverity (CID 1358495). > --- >

Re: [Mesa-dev] [PATCH] i965/fs: Add an allow_spilling flag to brw_compile_fs

Jason Ekstrand writes: > This allows us to disable spilling for blorp shaders since blorp state > setup doesn't handle spilling. Without this, blorp faisl hard if you run > with INTEL_DEBUG=spill. > > Cc: Curro Reviewed-by: Francisco Jerez > --- > src/intel/vulkan/anv_pipeline.c

[Mesa-dev] [PATCH 00/18] swr: update rasterizer

Mostly small cleanups this round. Tim Rowley (18): swr: [rasterizer core] use parens to disambiguate operator precedence swr: [rasterizer common] foreground win32 assert dialog swr: [rasterizer common] portable threadviz buckets swr: [rasterizer core] utility function for getenv swr: [ra

[Mesa-dev] [PATCH 07/18] swr: [rasterizer core] removed tabs that snuck in

--- src/gallium/drivers/swr/rasterizer/core/pa.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/pa.h b/src/gallium/drivers/swr/rasterizer/core/pa.h index eb8403c..c98ea14 100644 --- a/src/gallium/drivers/swr/rasterizer/core/pa.h

[Mesa-dev] [PATCH 09/18] swr: [rasterizer common] warning cleanup

--- src/gallium/drivers/swr/rasterizer/common/os.h | 4 1 file changed, 4 insertions(+) diff --git a/src/gallium/drivers/swr/rasterizer/common/os.h b/src/gallium/drivers/swr/rasterizer/common/os.h index 675fe42..df7daa6 100644 --- a/src/gallium/drivers/swr/rasterizer/common/os.h +++ b/src/g

[Mesa-dev] [PATCH 18/18] swr: [rasterizer] utility functions for shared libs

--- src/gallium/drivers/swr/rasterizer/core/utils.h| 65 +- .../drivers/swr/rasterizer/jitter/jit_api.h| 1 + 2 files changed, 64 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/utils.h b/src/gallium/drivers/swr/rasterizer/core/

[Mesa-dev] [PATCH 05/18] swr: [rasterizer core] OSX cleanup

--- src/gallium/drivers/swr/rasterizer/core/frontend.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp index c13280e..6bb9b12 100644 --- a/src/gallium/drivers/swr/ra

[Mesa-dev] [PATCH 14/18] swr: [rasterizer core] clang cleanups

Move a MultisampleTrait static from header to cpp as clang seemed to get confused with some specializations in the header vs some in cpp. --- src/gallium/drivers/swr/rasterizer/core/format_types.h | 2 ++ src/gallium/drivers/swr/rasterizer/core/multisample.cpp | 5 +++-- src/gallium/drivers/swr/r

[Mesa-dev] [PATCH 11/18] swr: [rasterizer] rename _aligned_malloc to AlignedMalloc

--- src/gallium/drivers/swr/rasterizer/common/os.h | 19 +-- src/gallium/drivers/swr/rasterizer/core/api.cpp | 16 src/gallium/drivers/swr/rasterizer/core/arena.h | 4 ++-- src/gallium/drivers/swr/rasterizer/core/frontend.cpp | 8 src/gal

[Mesa-dev] [PATCH 08/18] swr: [rasterizer common] gcc/clang cleanup

--- src/gallium/drivers/swr/rasterizer/common/os.h | 8 1 file changed, 8 insertions(+) diff --git a/src/gallium/drivers/swr/rasterizer/common/os.h b/src/gallium/drivers/swr/rasterizer/common/os.h index 7bfc66f..675fe42 100644 --- a/src/gallium/drivers/swr/rasterizer/common/os.h +++ b/s

[Mesa-dev] [PATCH 06/18] swr: [rasterizer core] cygwin cleanup

--- .../drivers/swr/rasterizer/core/threads.cpp| 60 ++ 1 file changed, 38 insertions(+), 22 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/threads.cpp b/src/gallium/drivers/swr/rasterizer/core/threads.cpp index 0b57a3f..17bf616 100644 --- a/src/gal

[Mesa-dev] [PATCH 10/18] swr: [rasterizer jitter] rename MEMCPY function to MEMCOPY

--- src/gallium/drivers/swr/rasterizer/jitter/scripts/gen_llvm_ir_macros.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/swr/rasterizer/jitter/scripts/gen_llvm_ir_macros.py b/src/gallium/drivers/swr/rasterizer/jitter/scripts/gen_llvm_ir_macros.py index

[Mesa-dev] [PATCH 02/18] swr: [rasterizer common] foreground win32 assert dialog

--- src/gallium/drivers/swr/rasterizer/common/swr_assert.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/swr/rasterizer/common/swr_assert.cpp b/src/gallium/drivers/swr/rasterizer/common/swr_assert.cpp index 0bffd2c..49587d0 100644 --- a/src/gallium/driv

[Mesa-dev] [PATCH 17/18] swr: [rasterizer jitter] fix assert in AVX implementation of MASKLOADD

llvm changed the mask type to vector of ints with 3.8. --- src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp b/src/gallium/drivers/swr/rasterizer/jitter

[Mesa-dev] [PATCH 15/18] swr: [rasterizer jitter] add instancing to non-gather fetch path

--- .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 42 +++--- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp b/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp index 42b1c3e..58cafb5 100644 --- a/

[Mesa-dev] [PATCH 16/18] swr: [rasterizer core] apply KNOB_TOSS_DRAW to more functions

--- src/gallium/drivers/swr/rasterizer/core/api.cpp | 20 1 file changed, 20 insertions(+) diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp b/src/gallium/drivers/swr/rasterizer/core/api.cpp index 9d6f250..8e0c1e1 100644 --- a/src/gallium/drivers/swr/rasterizer/co

[Mesa-dev] [PATCH 01/18] swr: [rasterizer core] use parens to disambiguate operator precedence

--- src/gallium/drivers/swr/rasterizer/core/frontend.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp index 0834610..c13280e 100644 --- a/src/gallium/drivers/swr/rast

[Mesa-dev] [PATCH 13/18] swr: [rasterizer core] clang override for _mm_undefined*

Not supported in older xcode versions. --- src/gallium/drivers/swr/rasterizer/core/utils.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/swr/rasterizer/core/utils.h b/src/gallium/drivers/swr/rasterizer/core/utils.h index 1c4780a..bf53c69 100644 --- a/src/

[Mesa-dev] [PATCH 03/18] swr: [rasterizer common] portable threadviz buckets

Output with slashes instead of backslashes for unix/linux. --- src/gallium/drivers/swr/rasterizer/common/rdtsc_buckets.cpp | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/common/rdtsc_buckets.cpp b/src/gallium/drivers/swr/raste

[Mesa-dev] [PATCH 12/18] swr: [rasterizer common] OSX cleanups

--- src/gallium/drivers/swr/rasterizer/common/os.h | 9 - src/gallium/drivers/swr/rasterizer/common/rdtsc_buckets.cpp | 2 +- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/common/os.h b/src/gallium/drivers/swr/rasterizer/com

[Mesa-dev] [PATCH 04/18] swr: [rasterizer core] utility function for getenv

--- src/gallium/drivers/swr/rasterizer/core/utils.h | 17 + 1 file changed, 17 insertions(+) diff --git a/src/gallium/drivers/swr/rasterizer/core/utils.h b/src/gallium/drivers/swr/rasterizer/core/utils.h index e3c534d..1c4780a 100644 --- a/src/gallium/drivers/swr/rasterizer/core/

[Mesa-dev] [Bug 95005] Unreal engine demos segfault after shader compilation error with OpenGL 4.3

https://bugs.freedesktop.org/show_bug.cgi?id=95005 --- Comment #9 from Dave Airlie --- https://patchwork.freedesktop.org/patch/87530/ https://patchwork.freedesktop.org/patch/87532/ Proposed fixes for both bugs. -- You are receiving this mail because: You are on the CC list for the bug.___

[Mesa-dev] [PATCH] glsl: handle same struct redeclaration

From: Dave Airlie This works around a bug in older version of UE4, where a shader defines the same structure twice. Although we aren't sure this is correct GLSL (it most likely isn't) there are enough UE4 based things out there we should deal with this. This drops the error to a warning if the s

Re: [Mesa-dev] [PATCH] i965: enable ARB_shader_precision

On Monday, May 16, 2016 3:11:12 PM PDT Alejandro Piñeiro wrote: > At this moment the documentation says: > GL_ARB_shader_precision DONE (all drivers that support GLSL 4.10) > > On the intel drivers, GLSLVersion is being updated based on the > extensions being completed. So this patch just enable

Re: [Mesa-dev] [PATCH 00/23] anv: Format reworks

On Mon, May 16, 2016 at 12:08:05PM -0700, Jason Ekstrand wrote: > This series scratches an itch I've had in the Vulkan driver for some time. > Early on, we added a table of anv_format structs. This served a bunch of > different purposes at the same time: basic format introspection, mapping > from

Re: [Mesa-dev] [PATCH 15/23] anv/formats: Delete validate_GetPhysicalDeviceFormatProperties

On Mon, May 16, 2016 at 12:08:20PM -0700, Jason Ekstrand wrote: > All it ever did was some extra logging that was useful when initially > bringing up Dota2. We don't need it anymore. Acked-by: Nanley Chery > --- > src/intel/vulkan/anv_formats.c | 10 -- > 1 file changed, 10 deletions(-

Re: [Mesa-dev] [PATCH 14/23] anv/image: Use aspects for computing full usage

On Mon, May 16, 2016 at 12:08:19PM -0700, Jason Ekstrand wrote: > --- > src/intel/vulkan/anv_image.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c > index 704ca9f..792645d 100644 > --- a/src/intel/vulkan

Re: [Mesa-dev] [PATCH 11/23] anv/copy: Use the linear format from the image for the buffer block size

On Mon, May 16, 2016 at 12:08:16PM -0700, Jason Ekstrand wrote: > Because the buffer is exposed to the user, the block size is defined to > always exactly be the size of the actual vulkan format. This is the same > size (it had better be) as the linaer image format. s/linaer/linear/ > --- > src

Re: [Mesa-dev] [PATCH 08/23] anv/copy: Use the color_surf from the image to get the block size

On Mon, May 16, 2016 at 12:08:13PM -0700, Jason Ekstrand wrote: > --- > src/intel/vulkan/anv_meta_copy.c | 29 - > 1 file changed, 20 insertions(+), 9 deletions(-) > > diff --git a/src/intel/vulkan/anv_meta_copy.c > b/src/intel/vulkan/anv_meta_copy.c > index 372333e..

Re: [Mesa-dev] [PATCH 07/23] anv: Change render_pass_attachment.format to a VkFormat

On Mon, May 16, 2016 at 12:08:12PM -0700, Jason Ekstrand wrote: > --- > src/intel/vulkan/anv_cmd_buffer.c | 9 ++--- > src/intel/vulkan/anv_pass.c | 2 +- > src/intel/vulkan/anv_private.h| 2 +- > 3 files changed, 8 insertions(+), 5 deletions(-) With respect to the commit title, the

Re: [Mesa-dev] [PATCH 04/23] anv/image: Add an aspects field

On Mon, May 16, 2016 at 12:08:09PM -0700, Jason Ekstrand wrote: > This makes several checks easier and allows us to avoid calling > anv_format_for_vk_format in a number of cases. > --- > src/intel/vulkan/anv_image.c | 3 +++ > src/intel/vulkan/anv_private.h | 3 ++- > src/intel/vulkan/ge

[Mesa-dev] [PATCH] glsl/linker: attempt to match anonymous structures at link

From: Dave Airlie This is my attempt at fixing at least one of the UE4 bugs with GL4.3. If we are doing intrastage matching and hit anonymous structs, then we should do a record comparison instead of using the names. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95005 Signed-off-by: Da

[Mesa-dev] [Bug 95434] Rendercheck suite has low pass rate after new test cases were added

https://bugs.freedesktop.org/show_bug.cgi?id=95434 Kenneth Graunke changed: What|Removed |Added QA Contact|mesa-dev@lists.freedesktop. |intel-gfx-bugs@lists.freede

[Mesa-dev] [PATCH 2/2] i965: Make brw_reg_from_fs_reg() halve exec_size when compressed.

In a5d7e144eaf43fee37e6ff9e2de194407087632b, Connor generalized the exec_size halving code to handle more cases. As part of this, he made it not halve anything if the region accessed falls completely in a single register. Unfortunately, it started producing some invalid regions: -add(16) g6<1>F

[Mesa-dev] [PATCH 1/2] i965: Move compression decisions before brw_reg_from_fs_reg().

brw_reg_from_fs_reg() needs to know whether the instruction will be compressed or not. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95370 Signed-off-by: Kenneth Graunke Cc: Connor Abbott Cc: Francisco Jerez Cc: Matt Turner --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 52

Re: [Mesa-dev] [PATCH] glsl: produce a linker error for a subroutine uniform with no functions.

On Fri, 2016-05-06 at 11:38 +1000, Dave Airlie wrote: > From: Dave Airlie > > If a subroutine uniform is declared with no functions backing it, > that isn't legal, so we should fail to link. > > Fixes: > GL43-CTS.shader_subroutine.subroutine_uniform_wo_matching_subroutines > > Signed-off-by: Da

Re: [Mesa-dev] [PATCH v2 13/14] radeonsi: Process multiple patches per threadgroup.

On Mon, May 16, 2016 at 10:15 PM, Marek Olšák wrote: > On Fri, May 13, 2016 at 3:37 AM, Bas Nieuwenhuizen > wrote: >> Using more than 1 wave per threadgroup does increase performance >> generally. Not using too many patches per threadgroup also >> increases performance. Both catalyst and amdgpu-

Re: [Mesa-dev] [PATCH 11/11] dri: Add YVU formats

Kristian (1), (2): thanks, I will try the latest patches (3): sorry, this is not specific to YUV sampling patches. I believe this problem has always been there. On Mon, May 16, 2016 at 4:33 PM, Kristensen, Kristian H wrote: > On Mon, May 16, 2016 at 4:21 PM, Haixia Shi wrote: >> Kristian >> >>

Re: [Mesa-dev] [PATCH 3/3] nir/validate: dump annotated shader with error msgs

On Mon, May 16, 2016 at 12:54 PM, Rob Clark wrote: > From: Rob Clark > > Log all the errors, and at the end dump the shader w/ error annotations > to make it easier to see where the problems are. > > Signed-off-by: Rob Clark > Reviewed-by: Eduardo Lima Mitev > --- > src/compiler/nir/nir_valida

Re: [Mesa-dev] Mesa 11.3.0/12.0.0 release plan

On Saturday, May 14, 2016 4:05:17 PM PDT Emil Velikov wrote: > Gents am I missing something or not many of the fp64/va64 patches have > landed yet ? The proposed branchpoint is a week away, so I'd like to > hear your thoughts on how long you think is going to take to land the > work. > > Thanks >

Re: [Mesa-dev] [PATCH v2 12/14] radeonsi: Use barrier instructions for TCS barriers.

On Mon, May 16, 2016 at 7:48 PM, Marek Olšák wrote: > NAK. The barrier is never needed with tessellation, because every > patch always fits into a single wave and there is no patch splitting > between waves. > > Marek OK. I don't see any optimization barrier before loading the tess factors thoug

[Mesa-dev] [PATCH] Added pbuffer hooks for surfaceless platform

This change enables the creation of pbuffer surfaces on the surfaceless platform. v3: Going back to single-buffered pbuffer plus additional code review changes --- src/egl/drivers/dri2/egl_dri2.h | 7 +- src/egl/drivers/dri2/platform_surfaceless.c | 213 +++-

Re: [Mesa-dev] [PATCH] glsl: use enum glsl_interface_packing in more places.

On Wed, 2016-05-11 at 10:50 +1000, Dave Airlie wrote: > From: Dave Airlie > > Although the glsl_types.h stores this in a bitfield, > we should hide that from everyone else. Hide the cast > in an accessor method and use the enum everywhere. > > This makes things a bit nicer in gdb, and improves t

Re: [Mesa-dev] [PATCH 11/11] dri: Add YVU formats

Kristian While testing these we found several NULL pointer access and deadlock problems with the YUV patches. I have uploaded a few proposed fixes, can you take a look? (1) i965: fix NULL pointer access in intel_image_target_texture_2d If image->planar_format is NULL we need to fall back to invok

[Mesa-dev] [Bug 95434] Rendercheck suite has low pass rate after new test cases were added

https://bugs.freedesktop.org/show_bug.cgi?id=95434 Jairo Miramontes changed: What|Removed |Added Assignee|mesa-dev@lists.freedesktop. |kaveh.na...@intel.com

[Mesa-dev] [Bug 95434] Rendercheck suite has low pass rate after new test cases were added

https://bugs.freedesktop.org/show_bug.cgi?id=95434 Bug ID: 95434 Summary: Rendercheck suite has low pass rate after new test cases were added Product: Mesa Version: unspecified Hardware: Other OS: Linux (All

Re: [Mesa-dev] [PATCH 3/3] i965: Delete redundant extension enables

On Monday, May 16, 2016 12:24:23 PM PDT Ian Romanick wrote: > From: Ian Romanick > > A nearly identical block already exists in the gen >= 6 block above. > > Signed-off-by: Ian Romanick > --- > src/mesa/drivers/dri/i965/intel_extensions.c | 9 - > 1 file changed, 9 deletions(-) > > di

[Mesa-dev] vc4 Android build broken

Eric, The commit d36b28402f542 ("vc4: Reuse QPU disasm's cond flags in QIR.") breaks on Android builds (using clang) with this error: external/mesa3d/src/gallium/drivers/vc4/vc4_qpu_disasm.c:349:33: error: format string is not a string literal (potentially insecure) [-Werror,-Wformat-security]

Re: [Mesa-dev] [PATCH] spirv: Properly size the src[] array.

On Mon, May 16, 2016 at 12:50 PM, Matt Turner wrote: > Operations like nir_op_bitfield_insert have four arguments, leading to > memory corruption. > > Found by Coverity (CID 1358582). > --- > src/compiler/spirv/spirv_to_nir.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git

Re: [Mesa-dev] [PATCH] Added pbuffer hooks for surfaceless platform

Hi Chad, Yes, we are running dEQP on the surfaceless platform. The front-buffered pbuffer approach mostly works, though with a double-buffered pbuffer or back-buffered pbuffer + the pastebin changes we do pass an additional 70 GLES3 tests. It is probably best to follow what X11 does to avoid bre

Re: [Mesa-dev] [PATCH 0/5] anv: Port L3 cache programming from i965

On Wed, May 11, 2016 at 4:22 PM, Jordan Justen wrote: > git://people.freedesktop.org/~jljusten/mesa anv-l3-v1 > > This series is related to this bug: > > https://bugs.freedesktop.org/show_bug.cgi?id=94468 > > Since we have a work-around for that bug currently, this doesn't fix > it. It does allow

Re: [Mesa-dev] GL4.5 or bust...

On 17 May 2016 at 07:24, Ian Romanick wrote: > On 05/15/2016 01:32 PM, Dave Airlie wrote: >> So I said this on irc over the weekend and it seemed like we had some >> consensus on holding off 12.0 until we could announce 4.5 on some >> hardware. This assumes the FP64 stuff is going in at least. >>

[Mesa-dev] [PATCH] glsl: Check that layout is non-null before dereferencing.

It's checked everywhere else. Maybe is_interface implies layout is non-null. Likely not worth it. Found by Coverity (CID 1358495). --- src/compiler/glsl/ast_to_hir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_h

[Mesa-dev] [PATCH] egl/dri2: Don't check return result of mtx_unlock().

Coverity (CID 1358496) warns that the cleanup code doesn't unlock the mutex (which is arguably kind of stupid, since the only case that can happen is when mtx_unlock() failed!). But, mtx_unlock() isn't going to fail -- the mutex was locked by this thread just a few lines above it. --- src/egl/driv

[Mesa-dev] [PATCH] i965/fs: Add an allow_spilling flag to brw_compile_fs

This allows us to disable spilling for blorp shaders since blorp state setup doesn't handle spilling. Without this, blorp faisl hard if you run with INTEL_DEBUG=spill. Cc: Curro --- src/intel/vulkan/anv_pipeline.c | 3 ++- src/mesa/drivers/dri/i965/brw_blorp.c |

Re: [Mesa-dev] [PATCH 03/39] llvmpipe: Fix overflow for 32 bits available memory computation

On Sun, May 15, 2016 at 5:45 AM, Axel Davy wrote: > And cap to 2 GB on 32 bits. > > Fixes https://bugs.freedesktop.org/show_bug.cgi?id=94561 > > Signed-off-by: Axel Davy > --- > src/gallium/auxiliary/os/os_misc.c | 2 +- > src/gallium/drivers/llvmpipe/lp_screen.c | 5 + > 2 files chang

Re: [Mesa-dev] GL4.5 or bust...

On 05/15/2016 01:32 PM, Dave Airlie wrote: > So I said this on irc over the weekend and it seemed like we had some > consensus on holding off 12.0 until we could announce 4.5 on some > hardware. This assumes the FP64 stuff is going in at least. > > So I decided to roll out the proposal here, which

Re: [Mesa-dev] [PATCH] scons: gallium: link against nir as needed

On 16/05/16 18:55, Emil Velikov wrote: From: Emil Velikov ... otherwise we'll produce uncomplete binaries with introduction of NIR as alternative IR with next commits. Signed-off-by: Emil Velikov --- Hi Rob, A slightly different patch which seems to work fine on Linux and Windows [1] based

Re: [Mesa-dev] [PATCH 03/17] gallium: add NIR as a possible IR

On 09/05/16 20:33, Rob Clark wrote: From: Rob Clark Signed-off-by: Rob Clark Reviewed-by: Roland Scheidegger Reviewed-by: Marek Olšák --- src/gallium/include/pipe/p_defines.h | 1 + src/gallium/include/pipe/p_screen.h | 9 + src/gallium/include/pipe/p_state.h | 6 ++ 3 fi

Re: [Mesa-dev] [PATCH v2 14/14] radeonsi: Allow TES distribution between shader engines.

On Fri, May 13, 2016 at 3:37 AM, Bas Nieuwenhuizen wrote: > Setting 028B6C_DISTRIBUTION_MODE to a non-zero value and > either setting 028B6C_NUM_DS_WAVES_PER_SIMD to a non-zero > value or storing a zero control word hang my card. NUM_DS_WAVES_PER_SIMD must be 0 if distribution is enabled. With m

Re: [Mesa-dev] [PATCH v2 01/13] vl/dri3: add DRI3 support and implement create and destroy

On 05/16/2016 05:02 PM, Jose Fonseca wrote: On 16/05/16 21:59, Leo Liu wrote: Thanks Jose. How to trigger SCons build? From Mesa top of dir, just do scons on a Linux machine. You can also easily build MinGW target doing 'scons platform=windows' but for that you need mingw crosspiler

[Mesa-dev] [AppVeyor] mesa master #1257 completed

Build mesa 1257 completed Commit cf010de6ee by Jose Fonseca on 5/16/2016 8:46 PM: vl/dri: Move the DRI3 check out of sources include into C.\n\nFixes SCons build.\n\nTrivial. Built locally with SCons and autotools. Configure your notification prefere

Re: [Mesa-dev] [PATCH v2 01/13] vl/dri3: add DRI3 support and implement create and destroy

On 16/05/16 21:59, Leo Liu wrote: Thanks Jose. How to trigger SCons build? From Mesa top of dir, just do scons on a Linux machine. You can also easily build MinGW target doing 'scons platform=windows' but for that you need mingw crosspiler packages for your Linux distruibution. Jose

Re: [Mesa-dev] [PATCH v2 01/13] vl/dri3: add DRI3 support and implement create and destroy

Thanks Jose. How to trigger SCons build? Thanks, Leo On 05/16/2016 04:52 PM, Jose Fonseca wrote: On 16/05/16 21:43, Jose Fonseca wrote: On 12/05/16 18:13, Leo Liu wrote: required functions into place for implementation, create screen with device fd returned from X server, also bail out to DR

Re: [Mesa-dev] [PATCH v2 01/13] vl/dri3: add DRI3 support and implement create and destroy

On 16/05/16 21:43, Jose Fonseca wrote: On 12/05/16 18:13, Leo Liu wrote: required functions into place for implementation, create screen with device fd returned from X server, also bail out to DRI2 with certain conditions. v2: -organize the error out path (Axel) -squash previous patch 1 an

Re: [Mesa-dev] [PATCH v2 01/13] vl/dri3: add DRI3 support and implement create and destroy

On 12/05/16 18:13, Leo Liu wrote: required functions into place for implementation, create screen with device fd returned from X server, also bail out to DRI2 with certain conditions. v2: -organize the error out path (Axel) -squash previous patch 1 and 2 into one (Emil) Signed-off-by: Leo

[Mesa-dev] [AppVeyor] mesa master #1256 failed

Build mesa 1256 failed Commit 5e2072c711 by Leo Liu on 4/26/2016 3:23 PM: st/vdpau: add dri3 support\n\nSigned-off-by: Leo Liu \nReviewed-by: Alex Deucher \nReviewed-by: Christian König Configure your notification preferences ___

Re: [Mesa-dev] GL4.5 or bust...

On 16 May 2016 at 18:54, Kristian Høgsberg wrote: > On Mon, May 16, 2016 at 1:43 AM, Emil Velikov > wrote: >> Hi all, >> >> On 16 May 2016 at 01:32, Ilia Mirkin wrote: >>> On Sun, May 15, 2016 at 8:25 PM, Martin Peres wrote: On 16/05/16 02:55, Jason Ekstrand wrote: > On May 15, 2016 2

Re: [Mesa-dev] [PATCH 3/3] gallium: push offset down to driver

On Mon, May 16, 2016 at 3:53 PM, Emil Velikov wrote: > On 15 May 2016 at 12:34, Stanimir Varbanov > wrote: >> Push offset down to drivers when importing dmabuf. This is needed >> to more fully support EGL_EXT_image_dma_buf_import when a non-zero >> offset is specified. >> > How did you test this

Re: [Mesa-dev] [PATCH v2 13/14] radeonsi: Process multiple patches per threadgroup.

On Fri, May 13, 2016 at 3:37 AM, Bas Nieuwenhuizen wrote: > Using more than 1 wave per threadgroup does increase performance > generally. Not using too many patches per threadgroup also > increases performance. Both catalyst and amdgpu-pro seem to > use 40 patches as their maximum, but I haven't

Re: [Mesa-dev] [PATCH 2/2] i965: Enable GL_ARB_ES3_1_compatibility.

On Mon, May 16, 2016 at 4:00 PM, Dave Airlie wrote: > On 17 May 2016 at 05:58, Ilia Mirkin wrote: >> On Mon, May 16, 2016 at 3:51 PM, Dave Airlie wrote: >>> On 13 May 2016 at 11:31, Kenneth Graunke wrote: There are almost no tests in any test suite, but what little I've found seems to

Re: [Mesa-dev] [PATCH 2/3] st/dri: cleanup image_from_fd/dma_buf paths

On 16 May 2016 at 19:43, Emil Velikov wrote: > Hi Stanimir, > > On 15 May 2016 at 12:34, Stanimir Varbanov > wrote: >> Signed-off-by: Stanimir Varbanov >> --- >> src/gallium/state_trackers/dri/dri2.c | 75 >> ++- >> 1 file changed, 39 insertions(+), 36 deletion

Re: [Mesa-dev] [PATCH] swr: fix swr linkage so that static llvm works

Hi Tim, On 16 May 2016 at 19:31, Tim Rowley wrote: > --- > src/gallium/drivers/swr/Makefile.am | 11 ++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/src/gallium/drivers/swr/Makefile.am > b/src/gallium/drivers/swr/Makefile.am > index 6915aae..0a5ff19 100644 > --- a

Re: [Mesa-dev] [PATCH 2/2] i965: Enable GL_ARB_ES3_1_compatibility.

On 17 May 2016 at 05:58, Ilia Mirkin wrote: > On Mon, May 16, 2016 at 3:51 PM, Dave Airlie wrote: >> On 13 May 2016 at 11:31, Kenneth Graunke wrote: >>> There are almost no tests in any test suite, but what little I've found >>> seems to work. Ilia believes everything is in place. >>> >>> Signe

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