On Wed, 2016-10-26 at 13:13 -0700, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> >
> > In a later patch we want to change the semantics of offset() to be
> > in terms
> > of SIMD width and scalar channels so it is consistent with the
> > definition
> > of the same helper in the scalar
https://bugs.freedesktop.org/show_bug.cgi?id=98343
Tapani Pälli changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=98339
Tapani Pälli changed:
What|Removed |Added
Resolution|--- |FIXED
Status|ASSIGNED
Ported from radeonsi.
---
v2: Fix a typo pointed out by Roland Scheidegger.
src/amd/vulkan/radv_device.c | 30 +++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 512d366..d6efc3f 100644
-
On Thursday 27 October 2016, Roland Scheidegger wrote:
> On 10/26/2016 06:02 PM, Fredrik Höglund wrote:
> > Ported from radeonsi.
> > ---
> > src/amd/vulkan/radv_device.c | 30 +++---
> > 1 file changed, 27 insertions(+), 3 deletions(-)
> >
> > diff --git a/src/amd/vulkan/r
On Wednesday, October 26, 2016 10:42:32 AM PDT Francisco Jerez wrote:
> Daniel Vetter writes:
>
> > On Tue, Oct 25, 2016 at 11:16:56AM -0700, Francisco Jerez wrote:
> >> Kenneth Graunke writes:
> >>
> >> > If the kernel advertises a new enough command parser version, then we
> >> > can just ass
On Wed, Oct 26, 2016 at 11:23 PM, Ian Romanick wrote:
> From: Ian Romanick
>
> The bit-size of the sources and the bit-size of the destinations is
> almost always the same for instructions that can have variable sizes.
> The exception is shift instructions. We can have shift instructions
> where
On Wed, Oct 26, 2016 at 10:52 PM, Ian Romanick wrote:
> On 10/26/2016 03:04 PM, Connor Abbott wrote:
>> On Tue, Oct 25, 2016 at 8:59 PM, Ian Romanick wrote:
>>> From: Ian Romanick
>>>
>>> The shift operations are a little weird. NIR expects both operands to
>>> have the same size, but the shift
From: Ian Romanick
The bit-size of the sources and the bit-size of the destinations is
almost always the same for instructions that can have variable sizes.
The exception is shift instructions. We can have shift instructions
where the destination and the first source are (matching) 8-, 16-, 32-,
From: Ian Romanick
The shift operations are a little weird. NIR expects both operands to
have the same size, but the shift count operand is always 32-bits in
GLSL. Upconvert to make the rest of NIR happy, and we'll assume the
driver back-end will do something sensible.
v2: Don't up-convert the
On 10/26/2016 06:02 PM, Fredrik Höglund wrote:
Ported from radeonsi.
---
src/amd/vulkan/radv_device.c | 30 +++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 512d366..9184308 100644
---
On Wed, Oct 26, 2016 at 3:47 PM, Nanley Chery wrote:
> On Thu, Oct 06, 2016 at 03:21:54PM -0700, Nanley Chery wrote:
> > Provides an FPS increase of ~30% on the Sascha triangle and multisampling
> > demos.
>
> After attempting to enable fast depth clears in more areas, I noticed
> something possi
On Wed, Oct 26, 2016 at 2:06 PM, Matt Turner wrote:
> On Wed, Oct 26, 2016 at 2:00 PM, Jason Ekstrand
> wrote:
> > On Oct 26, 2016 12:51 PM, "Matt Turner" wrote:
> >>
> >> ---
> >> src/intel/Makefile.genxml.am | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/sr
On 10/26/2016 03:04 PM, Connor Abbott wrote:
> On Tue, Oct 25, 2016 at 8:59 PM, Ian Romanick wrote:
>> From: Ian Romanick
>>
>> The shift operations are a little weird. NIR expects both operands to
>> have the same size, but the shift count operand is always 32-bits in
>> GLSL. Upconvert to mak
On 10/26/2016 01:43 PM, Matt Turner wrote:
> On Tue, Oct 25, 2016 at 5:59 PM, Ian Romanick wrote:
>> From: Dave Airlie
>>
>> As for the double code, but using the 64-bit integer conversions.
>>
>> v2 (idr): Remove some spurious u2i() and i2u() operations when packing
>> and unpacking, repectively
On 10/26/2016 01:45 PM, Matt Turner wrote:
> On Tue, Oct 25, 2016 at 5:59 PM, Ian Romanick wrote:
>> From: Dave Airlie
>>
>> These are all the allowed 64-bit functions from ARB_gpu_shader_int64
>> spec.
>>
>> v2: restrict int64/double functions better.
>>
>> Signed-off-by: Dave Airlie
>> Reviewe
On 10/26/2016 02:25 AM, Iago Toral wrote:
> On Tue, 2016-10-25 at 17:59 -0700, Ian Romanick wrote:
>> From: Ian Romanick
>>
>> If the user did not request full linking, link the shader with the
>> built-in functions, inline them, and eliminate them. Previous to
>> this
>> you'd see all these call
On 10/26/2016 01:37 PM, Matt Turner wrote:
> On Tue, Oct 25, 2016 at 5:59 PM, Ian Romanick wrote:
>> From: Dave Airlie
>>
>> This adds support to call the new operations on conversions.
>>
>> Signed-off-by: Dave Airlie
>> Reviewed-by: Ian Romanick
>> ---
>> src/compiler/glsl/ast_function.cpp |
On 26/10/16 08:07 PM, Andy Furniss wrote:
>
> The bad = Starting with DRI3 (which is default) I still get trashed
> rendering full screen. Windowed including re-sizing seems OK.
>
> I use Fluxbox window manager, which does not use compositing -
> IIRC this has historically shown some ddx DRI2/3 is
From: Ian Romanick
This just makes the output of the standalone compiler a little more
compact.
v2: Fix indexing typo noticed by Iago. Move the add_neg_to_sub_visitor
to it's own header file. Add a unit test that exercises the visitor.
Both the neg_a_plus_b and neg_a_plus_neg_b tests reproduce
To be squashed with previous patch
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 3 +--
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp| 5 +
3 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/src/mesa/dr
From: Kenneth Graunke
---
src/compiler/shader_enums.h | 1 +
src/mesa/main/config.h | 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h
index 74055df..bb9f53d 100644
--- a/src/compiler/shader_enums.h
+++ b/src/compile
These new helpers will be used in nir_gather_info.c in the following patch.
---
src/compiler/nir_types.cpp | 18 ++
src/compiler/nir_types.h | 3 +++
2 files changed, 21 insertions(+)
diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp
index d145813..5b04e18 10
This takes us one step closer to being able to drop the GLSL IR
optimisation passes during linking in favour of the NIR passes.
---
src/mesa/drivers/dri/i965/brw_link.cpp | 2 --
src/mesa/drivers/dri/i965/brw_program.c | 2 ++
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mes
This takes us one step closer to being able to drop the GLSL IR
optimisation passes during linking in favour of the NIR passes.
Patch 4 has *not* been tested on Vulkan I've asked Mark to setup a branch
for me to run the Vulkan CTS with but don't have it yet.
Patch 6 needs to be squashed with 5 be
From: Kenneth Graunke
I want this function for nir_gather_info(), and realized it's basically
the same as the ones in nir_lower_io().
Signed-off-by: Kenneth Graunke
---
src/compiler/nir/nir.h | 2 ++
src/compiler/nir/nir_lower_io.c | 33 +++--
2 files chan
This is based on the code from the GLSL IR pass however unlike the GLSL IR
pass it also supports arrays of arrays.
As well as implementing the logic from the GLSL IR pass we add some
additional intrinsic cases to catch more system values.
---
src/compiler/nir/nir_gather_info.c | 262 +
On Wed, 2016-10-26 at 20:19 -0400, Ilia Mirkin wrote:
> On Wed, Oct 26, 2016 at 8:08 PM, Timothy Arceri
> wrote:
> >
> > On Wed, 2016-10-26 at 22:51 +1100, Timothy Arceri wrote:
> > >
> > > On Wed, 2016-10-26 at 13:13 +0300, Tapani Pälli wrote:
> > > >
> > > >
> > > > Hi;
> > > >
> > > > On 1
Ported from radeonsi.
---
src/amd/vulkan/radv_device.c | 30 +++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 512d366..9184308 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulk
On 10/26/2016 01:20 PM, Matt Turner wrote:
> On Tue, Oct 25, 2016 at 5:59 PM, Ian Romanick wrote:
>> +
>
> These comments were placeholders for unimplemented extensions, until
> recently when people began adding them before the actual extension
> with that number. I think the comment should be dr
On 10/26/2016 01:42 PM, Matt Turner wrote:
> On Tue, Oct 25, 2016 at 5:59 PM, Ian Romanick wrote:
>> From: Dave Airlie
>>
>> This adds 64-bit integer support to some AST and IR operations where
>> it is needed.
>>
>> Signed-off-by: Dave Airlie
>> Reviewed-by: Ian Romanick
>> ---
>> src/compile
Advertise two device local memory heaps; one that is host visible
and one that is not.
This makes it possible for clients to tell how much host visible
vs. non-host visible memory is available.
---
src/amd/vulkan/radv_device.c | 15 ++-
src/amd/vulkan/radv_radeon_
On 10/26/2016 02:46 AM, Iago Toral wrote:
> On Tue, 2016-10-25 at 17:59 -0700, Ian Romanick wrote:
>> From: Ian Romanick
>>
>> For many expressions, this is different from the printable name. The
>> printable name for ir_binop_add is "+", but we want "add". This is
>> needed for ir_builder_print
On Wed, Oct 26, 2016 at 8:08 PM, Timothy Arceri
wrote:
> On Wed, 2016-10-26 at 22:51 +1100, Timothy Arceri wrote:
>> On Wed, 2016-10-26 at 13:13 +0300, Tapani Pälli wrote:
>> >
>> > Hi;
>> >
>> > On 10/26/2016 11:27 AM, Tapani Pälli wrote:
>> > >
>> > >
>> > >
>> > >
>> > > On 10/26/2016 11:21 AM,
On Wed, 2016-10-26 at 22:51 +1100, Timothy Arceri wrote:
> On Wed, 2016-10-26 at 13:13 +0300, Tapani Pälli wrote:
> >
> > Hi;
> >
> > On 10/26/2016 11:27 AM, Tapani Pälli wrote:
> > >
> > >
> > >
> > >
> > > On 10/26/2016 11:21 AM, Timothy Arceri wrote:
> > > >
> > > >
> > > > On Wed, 2016-
This allows the post-processor to easily detect the API thread and to
process frame information. The frame information is needed to
optimized how data is processed from worker threads.
---
src/gallium/drivers/swr/rasterizer/archrast/events.proto | 8
src/gallium/drivers/swr/raste
Add frontend dependency concept in the DRAW_CONTEXT, which
allows serialization of frontend work if necessary.
---
src/gallium/drivers/swr/rasterizer/core/api.cpp | 3 +++
src/gallium/drivers/swr/rasterizer/core/context.h | 3 ++-
src/gallium/drivers/swr/rasterizer/core/threads.cpp | 14 ++
Used in abandoned all-or-nothing approach to converting to AVX512
---
.../drivers/swr/rasterizer/common/simdintrin.h | 633 -
.../drivers/swr/rasterizer/core/format_types.h | 189 --
src/gallium/drivers/swr/rasterizer/core/knobs.h| 5 -
src/gallium/drivers/swr
Used for common code reuse and simplification
---
.../drivers/swr/rasterizer/core/backend.cpp| 561 -
src/gallium/drivers/swr/rasterizer/core/backend.h | 150 +-
2 files changed, 351 insertions(+), 360 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/c
---
.../rasterizer/scripts/templates/ar_eventhandlerfile_h.template| 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
a/src/gallium/drivers/swr/rasterizer/scripts/templates/ar_eventhandlerfile_h.template
b/src/gallium/drivers/swr/rasterizer/scripts/templates/ar_eventhan
On Tue, 2016-10-25 at 17:53 +0200, Juan A. Suarez Romero wrote:
> When checking if a type contains doubles, integers, samples, etc. we
> check if the current type is a record or array, but not if it is an
> interface.
>
> This commit also inspects if the type is an interface.
>
> It fixes spec/ar
On Thu, Oct 06, 2016 at 03:21:54PM -0700, Nanley Chery wrote:
> Provides an FPS increase of ~30% on the Sascha triangle and multisampling
> demos.
After attempting to enable fast depth clears in more areas, I noticed
something possibly worth sharing. Most of the performance gain from this
patch is
On Wed, 2016-10-26 at 17:40 +0300, Andres Gomez wrote:
> On Wed, 2016-10-26 at 11:47 +1100, Timothy Arceri wrote:
>
> >
> > Did you test early_fragment_tests specifically? This is one that I
> > checked is only in merge_in_qualifier() and not merge_qualifier()
>
> AFAIK, early_fragment_tests is
On Tue, Oct 25, 2016 at 8:59 PM, Ian Romanick wrote:
> Whew! Here it is! There are four main groups to this patch series.
> All of this is available at:
>
> https://cgit.freedesktop.org/~idr/mesa/log/?h=arb_gpu_shader_int64
>
> There are some gaps in our current piglit tests. For example, I
On Tue, Oct 25, 2016 at 8:59 PM, Ian Romanick wrote:
> From: Ian Romanick
>
> Signed-off-by: Ian Romanick
> ---
> src/compiler/glsl/glsl_to_nir.cpp | 30 +++
> src/compiler/nir/nir_lower_alu_to_scalar.c | 1 +
> src/compiler/nir/nir_opcodes.py| 33
On Wed, Oct 26, 2016 at 9:37 AM, Brian Paul wrote:
> The term "client array" is a legacy thing dating back to the pre-VBO
> era when _all_ vertex arrays lived in client memory.
>
> Nowadays, it only contains vertex array state which is derived from
> gl_array_attributes and gl_vertex_buffer_bindin
This limitation was initially here because AMD_performance_monitor
doesn't allow to expose the real number of hardware counters. But
this actually really annoying when profiling with qapitrace.
Anyways, performance counters are mostly for developers and
failures are expected if you try to monitor
On Tue, Oct 25, 2016 at 8:59 PM, Ian Romanick wrote:
> From: Ian Romanick
>
> The shift operations are a little weird. NIR expects both operands to
> have the same size, but the shift count operand is always 32-bits in
> GLSL. Upconvert to make the rest of NIR happy, and we'll assume the
> driv
Tested-by: Mark Janes
Tapani Pälli writes:
> Otherwise we can end up with mismatching behavior between config and
> surface when client queries surface attributes. As example, configs
> for DRI3 do not support preserved behavior but here we were setting
> preserved behavior for pixmap and pbuff
Quoting Matt Turner (2016-10-26 14:06:02)
> On Wed, Oct 26, 2016 at 2:00 PM, Jason Ekstrand wrote:
> > On Oct 26, 2016 12:51 PM, "Matt Turner" wrote:
> >>
> >> ---
> >> src/intel/Makefile.genxml.am | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/src/intel/Makefi
So, not quite sure if this is the *correct* solution, but it is at least
*a* solution to a problem with android wallpaper vs mesa that I've been
debugging. Basically, what happens is:
EGLSurface tmpSurface = mEgl.eglCreatePbufferSurface(mEglDisplay,
mEglConfig, attribs);
mEgl.eglMakeCurren
Reviewed-by: Ilia Mirkin
On Wed, Oct 26, 2016 at 5:10 PM, Samuel Pitoiset
wrote:
> The emitter tried to emit sub instead of subr when src0 has
> actually a NEG modifier.
>
> Signed-off-by: Samuel Pitoiset
> Cc: "11.0 12.0 13.0"
> ---
> src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cp
The emitter tried to emit sub instead of subr when src0 has
actually a NEG modifier.
Signed-off-by: Samuel Pitoiset
Cc: "11.0 12.0 13.0"
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 +-
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +-
2 files changed, 2 i
On Wed, Oct 26, 2016 at 2:00 PM, Jason Ekstrand wrote:
> On Oct 26, 2016 12:51 PM, "Matt Turner" wrote:
>>
>> ---
>> src/intel/Makefile.genxml.am | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/intel/Makefile.genxml.am b/src/intel/Makefile.genxml.am
>> index 2df22
On Oct 26, 2016 12:51 PM, "Matt Turner" wrote:
>
> ---
> src/intel/Makefile.genxml.am | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/Makefile.genxml.am b/src/intel/Makefile.genxml.am
> index 2df223a..2ed2741 100644
> --- a/src/intel/Makefile.genxml.am
> +++ b/s
On Wed 26 Oct 2016, Tapani Pälli wrote:
> Otherwise we can end up with mismatching behavior between config and
> surface when client queries surface attributes. As example, configs
> for DRI3 do not support preserved behavior but here we were setting
> preserved behavior for pixmap and pbuffer.
>
On Tue, Oct 25, 2016 at 5:59 PM, Ian Romanick wrote:
> Whew! Here it is! There are four main groups to this patch series.
> All of this is available at:
>
> https://cgit.freedesktop.org/~idr/mesa/log/?h=arb_gpu_shader_int64
>
> There are some gaps in our current piglit tests. For example, I
On Tue, Oct 25, 2016 at 5:59 PM, Ian Romanick wrote:
> From: Dave Airlie
>
> These are all the allowed 64-bit functions from ARB_gpu_shader_int64
> spec.
>
> v2: restrict int64/double functions better.
>
> Signed-off-by: Dave Airlie
> Reviewed-by: Ian Romanick
> ---
> src/compiler/glsl/builtin
On Tue, Oct 25, 2016 at 5:59 PM, Ian Romanick wrote:
> From: Dave Airlie
>
> As for the double code, but using the 64-bit integer conversions.
>
> v2 (idr): Remove some spurious u2i() and i2u() operations when packing
> and unpacking, repectively, int64_t varyings.
typo: respectively
___
On Tue, Oct 25, 2016 at 5:59 PM, Ian Romanick wrote:
> From: Dave Airlie
>
> This adds 64-bit integer support to some AST and IR operations where
> it is needed.
>
> Signed-off-by: Dave Airlie
> Reviewed-by: Ian Romanick
> ---
> src/compiler/glsl/ast_to_hir.cpp | 12 ++--
> src/compil
On Tue, Oct 25, 2016 at 5:59 PM, Ian Romanick wrote:
> From: Dave Airlie
>
> This adds support to call the new operations on conversions.
>
> Signed-off-by: Dave Airlie
> Reviewed-by: Ian Romanick
> ---
> src/compiler/glsl/ast_function.cpp | 75
> ++
> src/
On Tue, Oct 25, 2016 at 5:59 PM, Ian Romanick wrote:
> +
These comments were placeholders for unimplemented extensions, until
recently when people began adding them before the actual extension
with that number. I think the comment should be dropped since int64 is
#178.
> + xmlns:xi="http://www.w
Iago Toral Quiroga writes:
> In a later patch we want to change the semantics of offset() to be in terms
> of SIMD width and scalar channels so it is consistent with the definition
> of the same helper in the scalar backend. However, some uses of offset()
> in the vec4 backend do not operate natu
Iago Toral Quiroga writes:
> So that it has the same semantics as the scalar backend implementation. The
> helper will now take a simd width (which is always 8 in vec4 mode) and step
> as many scalar components as specified by that width, respecting the size of
> the scalar channels.
> ---
> src
Iago Toral Quiroga writes:
> ---
> src/mesa/drivers/dri/i965/brw_ir_vec4.h | 46
> +
> 1 file changed, 46 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
> b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
> index a8e5f4a..ef79e33 100644
> --- a/s
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 72 ++---
1 file changed, 16 insertions(+), 56 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
index d661c00..2c6d
Iago Toral writes:
> On Thu, 2016-10-20 at 16:25 -0700, Ian Romanick wrote:
>> On 10/20/2016 12:09 AM, Iago Toral Quiroga wrote:
>> >
>> > ARB_gpu_shader_fp64 was the last piece missing. Notice that some
>> > hardware and kernel combinations do not support pipelined register
>> > writes, which a
Signed-off-by: Samuel Pitoiset
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 14 ++
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 10 +-
src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 4 ++--
3 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/src/g
The first goal is to reduce code duplication between 3d and
compute and increase readability of that area.
This refactoring also tries to reduce the number of commands
send through the pushbuffer and to not invalidate all caches
when binding new textures/samplers. Although I don't see any
improvem
---
src/intel/Makefile.genxml.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/Makefile.genxml.am b/src/intel/Makefile.genxml.am
index 2df223a..2ed2741 100644
--- a/src/intel/Makefile.genxml.am
+++ b/src/intel/Makefile.genxml.am
@@ -33,7 +33,7 @@ $(GENXML_GENERATED_
On Tue, Oct 25, 2016 at 4:36 PM, Ilia Mirkin wrote:
> On Tue, Oct 25, 2016 at 7:09 PM, Anuj Phogat wrote:
>> Signed-off-by: Anuj Phogat
>> ---
>> src/mesa/drivers/dri/i965/brw_wm.c | 4 ++--
>> src/mesa/drivers/dri/i965/gen6_wm_state.c| 5 +++--
>> src/mesa/drivers/dri/i965/gen7_w
3DSTATE_WM_CHROMAKEY isn't programmed anywhere else.
3DSTATE_WM_HZ_OP is programmed, then cleared by blorp during a
HZ op, so repeatedly clearing it after every blorp execution is
redundant.
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 -
src/mesa/drivers/dri
This packet is non-pipelined and doesn't ever change across emissions.
Signed-off-by: Nanley Chery
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 41 +++-
src/mesa/drivers/dri/i965/brw_state.h| 1 -
src/mesa/drivers/dri/i965/brw_state_upload.c | 4 ---
3 fil
While analyzing the atom emission system, I noticed some unnecessary
atoms. This series removes these atoms to avoid paying the cost of
visiting them, and simplifies the codebase a bit.
Nanley Chery (2):
i965: Program 3DSTATE_AA_LINE_PARAMETERS in upload_invariant_state
i965: Move gen8_disable
On Tue, Oct 25, 2016 at 5:14 PM, Brian Paul wrote:
> On 10/25/2016 04:09 PM, Anuj Phogat wrote:
>>
>> Signed-off-by: Anuj Phogat
>> ---
>> src/mesa/main/framebuffer.c | 7 +++
>> src/mesa/main/framebuffer.h | 3 +++
>> 2 files changed, 10 insertions(+)
>>
>> diff --git a/src/mesa/main/fra
2016-10-26 19:20 GMT+02:00 Samuel Pitoiset :
>
>
> On 10/09/2016 11:04 AM, Karol Herbst wrote:
>>
>> v2: renamed commit
>> reordered modifiers
>> add assert(dst == src2)
>>
>> Signed-off-by: Karol Herbst
>> ---
>> .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 35
>>
Daniel Vetter writes:
> On Tue, Oct 25, 2016 at 11:16:56AM -0700, Francisco Jerez wrote:
>> Kenneth Graunke writes:
>>
>> > If the kernel advertises a new enough command parser version, then we
>> > can just assume that register writes will work and not bother executing
>> > commands on the GPU
I'm definitely in favour of my first solution, ie.:
if (postRA)
return post_ra_dead(this);
On 10/09/2016 11:04 AM, Karol Herbst wrote:
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h| 2 +-
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 20
On 10/09/2016 11:04 AM, Karol Herbst wrote:
v2: renamed commit
reordered modifiers
add assert(dst == src2)
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 35 --
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/sr
You forgot to add emission for the CC flag, ie:
if (i->flagsDef >= 0)
code[1] |= 1 << 23;
Few other comments below.
On 10/09/2016 11:04 AM, Karol Herbst wrote:
v2: renamed commit
reordered modifiers
add assert(dst == src2)
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codege
https://bugs.freedesktop.org/show_bug.cgi?id=98172
Marek Olšák changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
Was missed in an earlier renaming patch.
---
src/mesa/main/varray.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index 482090f..59f1779 100644
--- a/src/mesa/main/varray.c
+++ b/src/mesa/main/varray.c
@@ -125,7 +125,8 @@ type
Init vars where declared, use const qualifiers.
---
src/mesa/main/arrayobj.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/src/mesa/main/arrayobj.c b/src/mesa/main/arrayobj.c
index aa425b8..a54889b 100644
--- a/src/mesa/main/arrayobj.c
+++ b/src/mesa/main/arrayo
The term "client array" is a legacy thing dating back to the pre-VBO
era when _all_ vertex arrays lived in client memory.
Nowadays, it only contains vertex array state which is derived from
gl_array_attributes and gl_vertex_buffer_binding. It's used by the
VBO module and some drivers.
---
src/me
To be a little more understandable.
---
src/mesa/main/api_arrayelt.c | 20 ++--
src/mesa/main/arrayobj.c | 12 ++--
src/mesa/main/attrib.c | 2 +-
src/mesa/main/bufferobj.c| 8
src/mesa/main/get.c | 12 ++--
src/
Reviewed-by: Bas Nieuwenhuizen
On Wed, Oct 26, 2016 at 3:04 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> The intrinsic engine asserts in llvm due to this,
> as we put a vec4 into a vec1, and the next instruction
> isn't expecting it.
>
> So trim the vector at the end before inserting it.
>
>
Hi,
recently, we have noticed that we are not receiving some of the mails
that we have sent to the ML.
The mails are archived, though, but we don't get the copy from the ML.
We were checking if this was a problem in our side. However, we've
checked that they don't appear either in patchwork so
I had a few qeustions in 1 and 3, but regardless patches 1-7 and 9-13 are:
Reviewed-by: Topi Pohjolainen
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mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
When a layout contains a duplicated layout-qualifier-name in a single
declaration, only the last occurrence should be taken into account.
From page 59 (page 65 of the PDF) of the GLSL 4.40 spec:
" More than one layout qualifier may appear in a single
declaration. Additionally, the same layo
Since we modified the way in which multiple repetitions of the same
layout-qualifier-name in a single declaration collapse into the
ast_type_qualifier class, we can simplify the merge_[in|out]_qualifier
APIs through removing the create_node parameter.
Signed-off-by: Andres Gomez
---
src/compiler
Consider this example:
" #version 150 core
#extension GL_ARB_shading_language_420pack: require
#extension GL_ARB_explicit_attrib_location: require
layout(location=0) out vec4 o;
layout(binding=2) layout(binding=3, std140) uniform U {
vec4 a;
} u[2];"
A
This reverts commit 4c863993780a11cea6f88fa0682796bee5794042.
The commit was erroneous because the ast_layout_expression class was
created to hold a list of values for a layout-qualifier-name which is
allowed to appear in more than one expression in the same
shader/program but not to hold differen
After the previous modifications in the merging of the
layout-qualifier-name values, we no longer push the final value in a
declaration to the global values.
This regression happens because we don't call for merging on the
right-most layout qualifier of a declaration which is also the
overriding o
Tthe GLSL parser has been simplified to check for the needed
GL_ARB_shading_language_420pack extension just when merging the
qualifiers in the proper cases.
Reviewed-by: Timothy Arceri
Signed-off-by: Andres Gomez
---
src/compiler/glsl/ast_type.cpp | 6 ++
src/compiler/glsl/glsl_parser.yy
In the case of layout-qualifier-names that can appear multiple times
in different declarations of the same shader or, even, the same
program, but that have to consistently hold the same value we are
using the ast_layout_expression class which holds a list to store all
the appearances to be able to
On Wed, 2016-10-26 at 11:47 +1100, Timothy Arceri wrote:
> Did you test early_fragment_tests specifically? This is one that I
> checked is only in merge_in_qualifier() and not merge_qualifier()
AFAIK, early_fragment_tests is the only default input layout-qualifier-
name for a fragment shader (see
On 26 October 2016 at 14:09, Erik Faye-Lund wrote:
> PYTHON_GEN is defined to the exact same thing in both
> Makefile.glsl.am and Makefile.nir.am. This makes automake complain,
> so let's lift the definition up to Makefile.am, the same way as
> MKDIR_GEN.
>
Pushed to master.
Thanks Erik.
Emil
___
https://bugs.freedesktop.org/show_bug.cgi?id=98453
--- Comment #1 from Christian König ---
Patch is Reviewed-by: Christian König .
Please also send it to the VDPAU mailing list (vd...@lists.freedesktop.org).
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You are receiving this mail because:
You are the QA Contact for the bug.___
On Wednesday, 2016-10-26 13:54:51 +0300, Tapani Pälli wrote:
> Otherwise we can end up with mismatching behavior between config and
> surface when client queries surface attributes. As example, configs
> for DRI3 do not support preserved behavior but here we were setting
> preserved behavior for pi
On Wednesday, 2016-10-26 15:09:54 +0200, Erik Faye-Lund wrote:
> PYTHON_GEN is defined to the exact same thing in both
> Makefile.glsl.am and Makefile.nir.am. This makes automake complain,
> so let's lift the definition up to Makefile.am, the same way as
> MKDIR_GEN.
>
> Signed-off-by: Erik Faye-L
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