[Mesa-dev] [v2 25/39] i965: Prepare blit engine for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_blit.c | 37 +- src/mesa/drivers/dri/i965/intel_blit.h | 13 2 files changed, 41 insertions(+), 9 deletions(-) diff --git

[Mesa-dev] [v2 26/39] i965: Prepare image validation for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 1 file changed, 12 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 3a4ac14..55f6027

[Mesa-dev] [v2 23/39] i965/blorp: Add support for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 0235681..158cf66 100644 ---

[Mesa-dev] [v2 31/39] i965/tex: Prepare image update for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_tex_image.c | 19 --- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index

[Mesa-dev] [v2 22/39] i965/miptree: Add support for resolving offsets using isl

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_misc_state.c | 12 +-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 11 ++- src/mesa/drivers/dri/i965/intel_blit.c | 8 +- src/mesa/drivers/dri/i965/intel_fbo.c|

[Mesa-dev] [v2 21/39] intel/isl/gen6/hack: Use hiz vertical alignment of 16 instead of 8

Looking PRMs (SNB, IVB) it also looks to me that the height of hiz buffer would need to be half the height of depth. How this is taken into account in i965 legacy or isl is unclear to me also. Signed-off-by: Topi Pohjolainen --- src/intel/isl/isl_gen6.c | 40

[Mesa-dev] [v2 17/39] i965: Use stored hiz surface instead of creating copy

Now the last user of intel_miptree_get_aux_isl_surf() is gone. Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 77

[Mesa-dev] [v2 18/39] intel/isl/gen6: Add offsetting support for back-to-back layouts

Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp_blit.c | 2 +- src/intel/isl/isl.c | 29 +--- src/intel/isl/isl.h | 14 ++-- src/intel/isl/isl_gen6.c | 46

[Mesa-dev] [v2 19/39] intel/isl/gen6: Add size calculator for back-to-back layouts

Signed-off-by: Topi Pohjolainen --- src/intel/isl/isl.c | 26 ++ src/intel/isl/isl.h | 6 ++ src/intel/isl/isl_gen6.c | 27 +++ 3 files changed, 51 insertions(+), 8 deletions(-) diff --git

[Mesa-dev] [v2 20/39] i965/hiz/gen6: Use isl back-to-back layout

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 11 +++- src/mesa/drivers/dri/i965/brw_tex_layout.c| 56 -- src/mesa/drivers/dri/i965/gen6_depth_state.c | 18 +++--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [v2 16/39] i965/blorp: Use hiz surface instead of creating copy

Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 25 - src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 ++ 2 files changed, 18 insertions(+), 13

[Mesa-dev] [v2 12/39] i965/miptree: Refactor ISL aux usage resolver

Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c| 4 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 47

[Mesa-dev] [v2 14/39] i965/miptree: Drop MIPTREE_LAYOUT_ACCELERATED_UPLOAD in mcs init

because buffers get unconditionally initialised by cpu writing. Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff

[Mesa-dev] [v2 13/39] i965/miptree: Use ISL for MCS layouts

Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c| 6 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 101

[Mesa-dev] [v2 15/39] i965/miptree/gen7+: Use ISL for HIZ layouts

Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c| 6 +- src/mesa/drivers/dri/i965/brw_misc_state.c | 4 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 +-

[Mesa-dev] [v2 10/39] i965/gen6: Allocate hiz directly without miptree

Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 13 +--- src/mesa/drivers/dri/i965/gen6_depth_state.c | 8 - src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 46

[Mesa-dev] [v2 11/39] i965/miptree: Refactor aux surface allocation

Reviewed-by: Jason Ekstrand (v1) Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 60 +-- 1 file changed, 39 insertions(+), 21 deletions(-) diff --git

[Mesa-dev] [v2 07/39] i965/gen6: Drop miptrees in depth/stencil offset resolvers

Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 8 src/mesa/drivers/dri/i965/brw_tex_layout.c| 19 +-- src/mesa/drivers/dri/i965/gen6_depth_state.c |

[Mesa-dev] [v2 09/39] i965/gen6/hiz: Add direct buffer size resolver

The apparent hack adding unconditionally two lines into cube maps is taken directly from align_cube(). v2: Apply the cube map hack also for non-mipmapped. But apply it only for cube-map, not for cube-map-array to keep things as they were (use mt->target == GL_TEXTURE_CUBE_MAP instead

[Mesa-dev] [v2 08/39] i965/blorp/gen6: Set aux pitch directly

dropping dependency to intel_miptree_get_aux_isl_surf(). Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git

[Mesa-dev] [v2 06/39] i965/blorp/gen6: Use on-demand stencil/hiz offset resolvers

Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 21 - 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c

[Mesa-dev] [v2 05/39] i965/gen6: Calculate hiz offset on demand

This is kept on purpose in i965. It can be moved to ISL if it is needed in vulkan. Pointers to miptrees are given solely for verification purposes. These will be dropped in following patches. Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen

[Mesa-dev] [v2 04/39] i965/gen6: Calculate stencil offset on demand

This is kept on purpose in i965. It can be moved to ISL if it is needed in vulkan. Pointers to miptrees are given solely for verification purposes. These will be dropped in following patches. Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen

[Mesa-dev] [v2 03/39] i965/blorp/gen6: Drop unnecessary stencil/hiz surf dimension adjust

Hardware state setup only needs offset and pitch and ignores the rest. Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 57 --- 1 file changed, 20

[Mesa-dev] [v2 02/39] i965/gen6: Remove dead code in hiz surface setup

In intel_hiz_miptree_buf_create() the miptree is unconditionally created with MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD. Reviewed-by: Jason Ekstrand Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_depth_state.c | 13 ++---

[Mesa-dev] [v2 01/39] i965/dbg: Add means for forcing stencil sampling using y-tiled copy

While gen >= 8 can sample w-tiled stencil surfaces just fine, this option allows testing of the legacy behavior even on gen8+. Signed-off-by: Topi Pohjolainen --- src/intel/blorp/blorp.c | 4 +++- src/intel/blorp/blorp_blit.c

[Mesa-dev] i965: Use isl for hiz and stencil

Patches 1-17 are revision that - rework hiz on gen6 to use on-demand offset calculator allowing one to drop dependency to miptree structure and - rework all auxiliary surfaces to be created against isl directly. Patches 18 and 19 introduce new surface layout in ISL. This is called

[Mesa-dev] [PATCH] glsl: rename image_* qualifiers to memory_*

It doesn't make sense to prefix them with 'image' because they are called "Memory Qualifiers" and they can be applied to members of storage buffer blocks. Signed-off-by: Samuel Pitoiset --- src/compiler/glsl/ast_function.cpp | 10 +++---

Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: remove unrequired tgsi_get_opcode_info() call

Reviewed-by: Marek Olšák Marek On Wed, May 3, 2017 at 2:48 AM, Timothy Arceri wrote: > This is already set for the instruction at initialisation. > --- > src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +- > 1 file changed, 1 insertion(+), 1

[Mesa-dev] [PATCH] i965: Set modifier for imported and duplicated images

When a buffer is being created from FD or GEM flink import, the current API makes no provision for passing modifier information along with this. Set the modifier for such images to DRM_FORMAT_MOD_INVALID. Also preserve the modifier when duplicating an image, as will be done by GBM when importing

[Mesa-dev] [PATCH] anv: anv_gem_mmap() returns MAP_FAILED as mapping error

Take it into account when checking if the mapping failed. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_allocator.c | 2 +- src/intel/vulkan/anv_image.c | 4 2 files changed, 5 insertions(+), 1 deletion(-) diff --git

Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: remove unrequired tgsi_get_opcode_info() call

Reviewed-by: Samuel Pitoiset On 05/03/2017 02:48 AM, Timothy Arceri wrote: This is already set for the instruction at initialisation. --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [Mesa-dev] [PATCH 1/2] mesa: tidy up accum.h

Reviewed-by: Samuel Pitoiset On 05/03/2017 05:38 AM, Timothy Arceri wrote: These were unused. --- src/mesa/main/accum.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mesa/main/accum.h b/src/mesa/main/accum.h index a5665c7..ede2ecc 100644 ---

Re: [Mesa-dev] [PATCH 2/2] mesa: make _mesa_accum() static

Why don't inline _mesa_acum()? Usually, we remove the '_' for static mesa functions right? On 05/03/2017 05:38 AM, Timothy Arceri wrote: --- src/mesa/main/accum.c | 104 +- src/mesa/main/accum.h | 3 -- 2 files changed, 52 insertions(+), 55

Re: [Mesa-dev] [PATCH v3 00/13] anv: Implement VK_KHX_multiview

Hi Jason Sorry that I missed this. All the changes look good to me and I have sent reviews for the patches that missed them. With this series we pass all the multiview tests. Iago On Thu, 2017-04-27 at 09:31 -0700, Jason Ekstrand wrote: > This is mostly a re-send of my earlier patches but there

Re: [Mesa-dev] [PATCH v3 14/14] anv: Trivially implement multiDrawIndirect

On Wed, 2017-05-03 at 09:04 +0200, Iago Toral wrote: > On Thu, 2017-04-27 at 09:31 -0700, Jason Ekstrand wrote: > > > > --- > >  src/intel/vulkan/anv_device.c  |  2 +- > >  src/intel/vulkan/genX_cmd_buffer.c | 56 ++ > > > >  2 files changed, 34

Re: [Mesa-dev] [PATCH v3 14/14] anv: Trivially implement multiDrawIndirect

On Thu, 2017-04-27 at 09:31 -0700, Jason Ekstrand wrote: > --- >  src/intel/vulkan/anv_device.c  |  2 +- >  src/intel/vulkan/genX_cmd_buffer.c | 56 ++ > >  2 files changed, 34 insertions(+), 24 deletions(-) > > diff --git a/src/intel/vulkan/anv_device.c >

Re: [Mesa-dev] [PATCH v3 07/14] anv: Move shader hashing to anv_pipeline

On Thu, 2017-04-27 at 09:31 -0700, Jason Ekstrand wrote: > Shader hashing is very closely related to shader > compilation.  Putting > them right next to each other in anv_pipeline makes it easier to > verify > that we're actually hashing everything we need to be hashing. Maybe add that this

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