[Mesa-dev] [PATCH] Android: fix typo in symlink for driver loading and 32 bit builds

There is typo in the mkdir command path, the correct one is $(TARGET_OUT)/$(l)/$(MESA_DRI_MODULE_REL_PATH) The other issue is in 32bit builds, because lib64 does not exist there, we can use TARGET_IS_64_BIT to refine the post install command. Fixes: a3d98ca62f ("Android: use symlinks for driver l

[Mesa-dev] [Bug 101657] strtod.c:32:10: fatal error: xlocale.h: No such file or directory

https://bugs.freedesktop.org/show_bug.cgi?id=101657 Bug ID: 101657 Summary: strtod.c:32:10: fatal error: xlocale.h: No such file or directory Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (Al

[Mesa-dev] [Bug 101656] Invalid signal timestamps with EGL_SYNC_NATIVE_FENCE_ANDROID on android

https://bugs.freedesktop.org/show_bug.cgi?id=101656 Gary Wang changed: What|Removed |Added CC||gary.c.w...@intel.com -- You are receiving

[Mesa-dev] [Bug 101656] Invalid signal timestamps with EGL_SYNC_NATIVE_FENCE_ANDROID on android

https://bugs.freedesktop.org/show_bug.cgi?id=101656 Bug ID: 101656 Summary: Invalid signal timestamps with EGL_SYNC_NATIVE_FENCE_ANDROID on android Product: Mesa Version: 17.1 Hardware: x86-64 (AMD64) OS: Al

[Mesa-dev] [Bug 101655] Explicit sync support for android

https://bugs.freedesktop.org/show_bug.cgi?id=101655 Bug ID: 101655 Summary: Explicit sync support for android Product: Mesa Version: 17.1 Hardware: Other OS: other Status: NEW Severity: normal Pr

Re: [Mesa-dev] [PATCH 3/3] glsl: disable array splitting for AoA

On 30/06/17 12:45, Timothy Arceri wrote: While it produces functioning code the pass creates worse code for arrays of arrays. See the comment added in this patch for more detail. --- src/compiler/glsl/opt_array_splitting.cpp | 26 ++ 1 file changed, 26 insertions(+)

[Mesa-dev] [PATCH v2 19/27] i965/screen: Drop get_tiled_height

It's no longer used. Reviewed-by: Topi Pohjolainen Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/intel_screen.c | 20 +++- 1 file changed, 3 insertions(+), 17 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.

[Mesa-dev] [PATCH v2 17/27] i965/screen: Use ISL for allocating image BOs

Reviewed-by: Topi Pohjolainen Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/intel_screen.c | 51 ++-- 1 file changed, 29 insertions(+), 22 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 8

[Mesa-dev] [PATCH v2 24/27] i965/screen: Support import and export of surfaces with CCS

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_screen.c | 55 +--- 1 file changed, 50 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 03226af..66fd99a 100644 --- a

[Mesa-dev] [PATCH v2 25/27] i965: Pretend that CCS modified images are two planes

From: Ben Widawsky v2: move is_aux into if block. (Jason) Use else block instead of goto (Jason) v3: Fix up logic for is_aux (Ben) Fix up size calculations and add FIXME (Ben) v4 (Jason Ekstrand): Use the aux_pitch in the image instead of calculating it Signed-off-by: Ben Widawsky Acked-by: D

[Mesa-dev] [PATCH v2 13/27] i965/miptree: Move CCS allocation into create_for_dri_image

Any form of CCS on gen9+ only works on Y-tiled images. The only caller of create_for_bo which uses Y-tiled BOs is create_for_dri_image. Reviewed-by: Topi Pohjolainen Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 25 - 1 file changed, 12 i

[Mesa-dev] [PATCH v2 23/27] intel/isl: Add a row_pitch parameter to surf_get_ccs_surf

Reviewed-by: Topi Pohjolainen Reviewed-by: Chad Versace --- src/intel/isl/isl.c | 4 +++- src/intel/isl/isl.h | 3 ++- src/intel/vulkan/anv_image.c | 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 -- 4 files chang

[Mesa-dev] [PATCH v2 27/27] i965: Advertise the CCS modifier

From: Ben Widawsky v2: Rename modifier to be more smart (Jason) FINISHME: Use the kernel's final choice for the fb modifier bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube none Read bandwidth: 603.91 MiB/s Write bandwidth: 615.28 MiB/s bwidawsk@norri

[Mesa-dev] [PATCH v2 26/27] i965/miptree: More conservatively resolve external images

Instead of always doing a full resolve, only resolve the bits that are needed. This means that we only do a partial resolve when the miptree modifier is I915_FORMAT_MOD_Y_TILED_CCS. Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i96

[Mesa-dev] [PATCH v2 21/27] i965: Support images with aux buffers

From: Ben Widawsky Previously images did not support any auxiliary compression surfaces (CCS, MCS, or HiZ). That's about to change. This patch just adds the fields to __DRIimageRec to make auxiliary surfaces possible. v2 (Jason Ekstrand): - Add an aux_pitch parameter as well as aux_offset Si

[Mesa-dev] [PATCH v2 12/27] i965: Use create_for_dri_image in intel_update_image_buffer

Reviewed-by: Topi Pohjolainen Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_context.c | 23 ++- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 53e1a85..1c7cf

[Mesa-dev] [PATCH v2 22/27] i965/miptree: Allocate mcs_buf for an image's CCS

From: Ben Widawsky This code will disable actually creating these buffers for the scanout, but it puts the allocation in place. Primarily this patch is split out for review, it can be squashed in later if preferred. v2: assert(mt->offset == 0) in ccs creation (as requested by Topi) Remove bogus

[Mesa-dev] [PATCH v2 20/27] intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCS

Reviewed-by: Topi Pohjolainen Reviewed-by: Chad Versace --- src/intel/isl/isl_drm.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c index b7a4997..db72a34 100644 --- a/src/intel/isl/isl_drm.c +++ b/src/intel/isl/isl_drm.c @@ -54,

[Mesa-dev] [PATCH v2 18/27] i965/screen: Use ISL for doing image import checks

Reviewed-by: Topi Pohjolainen Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/intel_screen.c | 32 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 10

[Mesa-dev] [PATCH v2 07/27] i965/miptree: Allocate mt earlier in update winsys

From: Ben Widawsky Later commits require intel_update_image_buffer() to have control over the miptree creation. However, intel_update_winsys_renderbuffer_miptree() currently creates it based on the given buffer object. This patch moves the creation to the caller side. Signed-off-by: Ben Widaw

[Mesa-dev] [PATCH v2 16/27] intel/isl: Add a helper to convert tilings from ISL to i915

Reviewed-by: Topi Pohjolainen Reviewed-by: Chad Versace --- src/intel/isl/isl.h | 3 +++ src/intel/isl/isl_drm.c | 25 + 2 files changed, 28 insertions(+) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 563bcfb..dd550c3 100644 --- a/src/intel/isl/isl.h

[Mesa-dev] [PATCH v2 15/27] intel/isl: Add basic modifier introspection

Reviewed-by: Topi Pohjolainen Reviewed-by: Chad Versace --- src/intel/Makefile.am | 1 + src/intel/Makefile.sources | 1 + src/intel/isl/isl.h| 22 + src/intel/isl/isl_drm.c| 59 ++ 4 files changed, 83 insertions(+)

[Mesa-dev] [PATCH v2 09/27] main/formats: Add a get_linear_format_srgb helper

--- src/mesa/main/format_fallback.py | 22 ++ src/mesa/main/formats.h | 3 +++ 2 files changed, 25 insertions(+) diff --git a/src/mesa/main/format_fallback.py b/src/mesa/main/format_fallback.py index ec86938..e797a7d 100644 --- a/src/mesa/main/format_fallback.py +++

[Mesa-dev] [PATCH v2 08/27] main/formats: Autogenerate _mesa_get_srgb_format_linear

--- src/mesa/main/format_fallback.py | 46 +++ src/mesa/main/formats.c | 117 --- 2 files changed, 46 insertions(+), 117 deletions(-) diff --git a/src/mesa/main/format_fallback.py b/src/mesa/main/format_fallback.py index e3b9916..ec86938 1

[Mesa-dev] [PATCH v2 11/27] i965/miptree: Add support for window system images to create_for_dri_image

We want to start using create_for_dri_image for all miptrees created from __DRIimage, including those which come from a window system. In order to allow for fast clears to still work on window system buffers, we need to allow for creating aux surfaces. Reviewed-by: Topi Pohjolainen Reviewed-by:

[Mesa-dev] [PATCH v2 10/27] i965/miptree: Add a colorspace parameter to create_for_dri_image

The __DRI_FORMAT enums are all UNORM but we will frequently want sRGB when creating miptrees for renderbuffers. This lets us specify. --- src/mesa/drivers/dri/i965/intel_fbo.c | 3 ++- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 24 ++-- src/mesa/drivers/dri/i965/

[Mesa-dev] [PATCH v2 14/27] i965: Add an isl_device to intel_screen

Reviewed-by: Topi Pohjolainen Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i965/intel_screen.c | 3 +++ src/mesa/drivers/dri/i965/intel_screen.h | 4 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i96

[Mesa-dev] [PATCH v2 04/27] i965/miptree: Set level_x/h in create_for_dri_image

Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 077e2ab..0d989d5 100644 --- a/src/mesa/drivers/dri/i965/intel_mipm

[Mesa-dev] [PATCH v2 05/27] i965: Use miptree_create_for_dri_image in image_target_renderbuffer_storage

This does make a tiny functional change in that we now also test for whether or not the format supports texturing and not just rendering. However, this should have no practical effect as all renderbuffers use texturable formats. Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/intel_fbo.c

[Mesa-dev] [PATCH v2 06/27] i965/miptree: Add a return for updating of winsys

From: Ben Widawsky There is nothing particularly useful to do currently if the update fails, but there is no point carrying on either. As a result, this has a behavior change. v2: Make the return type a bool (Topi) v3: Don't leak the bo if update_winsys_renderbuffer fails. (Jason) Signed-off-b

[Mesa-dev] [PATCH v2 00/27] i965: i965: Add support for I915_FORMAT_MOD_Y_TILED_CCS

This is mostly a re-send of my earlier series: https://lists.freedesktop.org/archives/mesa-dev/2017-June/159724.html The first 5 or so patches from the original series have been pushed and are not included in this re-seend. There are two new patches (8 and 9) which are new. Also, 10 is a signif

[Mesa-dev] [PATCH v2 01/27] i965: Move the DRIimage -> miptree code to intel_mipmap_tree.c

This is mostly a direct port. The only bit of refactoring that was done was to make creating a planar miptree be an early return from the non-planar case. Alternatively, we could have three functions: two helpers and a main function to just call the right helper. Making the planar case an early

[Mesa-dev] [PATCH v2 02/27] i965/miptree: Pass the offset into create_for_bo in create_for_dri_image

Reviewed-by: Chad Versace Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 9dcf5be..bdd0cd5 1

[Mesa-dev] [PATCH v2 03/27] i965/miptree: Add tile_x/y to total_width/height

This is what we do in intel_image_target_renderbuffer_storage and it makes more sense than stomping them. Because the image gets created as a 2D image with one miplevel, they should already be equal to the provided width/height. Adding the tile offset makes some sense depending on how you interpr

Re: [Mesa-dev] [PATCH 1/3] spirv: fix OpBitcast when the src and dst bitsize are different

On Thu, Jun 8, 2017 at 3:05 PM, Connor Abbott wrote: > From: Connor Abbott > > Before, we were just implementing it with a move, which is incorrect > when the source and destination have different bitsizes. To implement > it properly, we need to use the 64-bit pack/unpack opcodes. Since > glslan

Re: [Mesa-dev] [PATCH 07/14] gallium/radeon: remove RADEON_FLAG_CPU_ACCESS

On 30/06/17 04:47 AM, Marek Olšák wrote: > From: Marek Olšák > > https://lists.freedesktop.org/archives/amd-gfx/2017-June/010591.html This is premature. The discussion on amd-gfx hasn't concluded yet. -- Earthling Michel Dänzer | http://www.amd.com Libre software e

[Mesa-dev] [PATCH 3/3] glsl: disable array splitting for AoA

While it produces functioning code the pass creates worse code for arrays of arrays. See the comment added in this patch for more detail. --- src/compiler/glsl/opt_array_splitting.cpp | 26 ++ 1 file changed, 26 insertions(+) diff --git a/src/compiler/glsl/opt_array_splitt

[Mesa-dev] [PATCH 2/3] nir: fix nir_opt_copy_prop_vars() for arrays of arrays

Previous we only incremented the guide for a single dimension/wildcard. --- src/compiler/nir/nir_opt_copy_prop_vars.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/compiler/nir/nir_opt_copy_prop_vars.c b/src/compiler/nir/nir_opt_copy_prop_vars.c index 7f

[Mesa-dev] [PATCH 1/3] nir: NULL check lower_copies_to_load_store()

Allows us to disable array spliting for arrays of arrays without regressing tests such as: ES31-CTS.functional.shaders.arrays_of_arrays.return.explicit.struct_3x1x3_fragment --- src/compiler/nir/nir_lower_vars_to_ssa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compil

Re: [Mesa-dev] [PATCH 07/18] nir/spirv: Use the correct stride for non-32-bit vectors

Fixup the comment above this? On Thu, Jun 29, 2017 at 10:33 AM, Jason Ekstrand wrote: > --- > src/compiler/spirv/spirv_to_nir.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/compiler/spirv/spirv_to_nir.c > b/src/compiler/spirv/spirv_to_nir.c > index 18e3734..7a988

Re: [Mesa-dev] [PATCH 07/18] nir/spirv: Use the correct stride for non-32-bit vectors

On Thu, Jun 29, 2017 at 6:51 PM, Connor Abbott wrote: > Fixup the comment above this? > Yup. Fixed locally. > On Thu, Jun 29, 2017 at 10:33 AM, Jason Ekstrand > wrote: > > --- > > src/compiler/spirv/spirv_to_nir.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git

[Mesa-dev] [PATCH] anv: Advertise support for VK_FORMAT_R8_SRGB

Unreal Engine 4 seems to really like this format for some reason. We don't technically have the hardware format but we do have L8_SRGB. It's easy enough to fake with that and a swizzle. --- src/intel/vulkan/anv_formats.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/i

Re: [Mesa-dev] [PATCH 16/30] i965/miptree: Move CCS allocation into create_for_dri_image

On Wed, Jun 28, 2017 at 2:15 PM, Chad Versace wrote: > On Fri 16 Jun 2017, Jason Ekstrand wrote: > > Any form of CCS on gen9+ only works on Y-tiled images. The only caller > > of create_for_bo which uses Y-tiled BOs is create_for_dri_image. > > If I understand ARC++ correctly, then intel_update_

[Mesa-dev] [PATCH] glthread: get rid of unmarshal dispatch enum/table

Use function pointers to identify the unmarshalling function, which is simpler and gets rid of a lot generated code. This removes an indirection and possibly results in a slight speedup as well. --- src/mapi/glapi/gen/Makefile.am | 4 -- src/mapi/glapi/gen/gl_marshal.py | 36 ++

Re: [Mesa-dev] [PATCH 13/30] i965/miptree: Add an explicit format parameter to create_for_dri_image

On Wed, Jun 28, 2017 at 11:09 AM, Jason Ekstrand wrote: > On Wed, Jun 28, 2017 at 10:59 AM, Daniel Stone > wrote: > >> Hi, >> >> On 28 June 2017 at 16:35, Jason Ekstrand wrote: >> > On Wed, Jun 28, 2017 at 4:06 AM, Daniel Stone >> wrote: >> >> On 28 June 2017 at 02:05, Jason Ekstrand wrote: >

Re: [Mesa-dev] [PATCH 01/18] nir/spirv: Move a "}"

On Thu, Jun 29, 2017 at 2:26 PM, Lionel Landwerlin < lionel.g.landwer...@intel.com> wrote: > How did this even compile? > Because aparently C lets you put switch cases anywhere. > Should we cc stable? > I debated that. I don't think it's needed as this isn't actually a functional change. >

Re: [Mesa-dev] [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:34 PM, Rodrigo Vivi wrote: By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for reference. Cc: Anusha Srivatsa

Re: [Mesa-dev] [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus.

Reviewed-by: Clinton Taylor -Clint On 06/29/2017 02:34 PM, Rodrigo Vivi wrote: Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy of merged i915's commit e918

Re: [Mesa-dev] [PATCH 1/2] radeonsi: use a bitfield for tracking which shaders use bindless

On 30/06/17 05:59, Samuel Pitoiset wrote: This will allow to skip few partial flushes when bindless descriptors have to be re-uploaded. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/radeonsi/si_blit.c | 4 +-- src/gallium/drivers/radeonsi/si_pipe.h | 4 +-- sr

Re: [Mesa-dev] [PATCH] mesa: Avoid set comprehension.

Gahh, we're seriously still supporting 2.6 for builds? 2.6 was EOL in 2013, and 2.7 was shiny and new in 2010. It's also going to make hybridizing for 3.x incredibly painful. If possible I'd really like to not support 2.6, though I'm sure that will cause pain for the RHEL guys... Quoting Vinson Le

Re: [Mesa-dev] [PATCH 2/4] i965/miptree: Tighten up finish_mcs_write

This patch is Reviewed-by: Ian Romanick On 06/26/2017 11:49 AM, Jason Ekstrand wrote: > Multisample surfaces only have a single miplevel so there's no reason to > be passing the extra parameters around. It only leads to confusion. > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15

Re: [Mesa-dev] [PATCH 4/4] i965/miptree: Partially resolve MCS for texture views

On 06/26/2017 11:49 AM, Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +++--- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > index c94f

[Mesa-dev] [PATCH 4/4] intel: add GEN10 to IS_9XX.

From: Paulo Zanoni As far as I understand, IS_9XX should return true for it. Signed-off-by: Paulo Zanoni --- intel/intel_chipset.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 37579c6..770d21f 100644 --- a/intel/intel

[Mesa-dev] [PATCH 3/4] intel/gen10: Add missed gen10 stuff

From: Ben Widawsky This got lost on rebase, I believe Signed-off-by: Ben Widawsky --- intel/intel_bufmgr_gem.c | 2 ++ intel/intel_decode.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 45a26da..71f140f 100

[Mesa-dev] [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus.

Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is a copy of merged i915's commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.") v2: Remove PCI IDs for

[Mesa-dev] [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.

By the Spec all CNL Y skus are 2+2, i.e. GT2. This is a copy of merged i915's commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.") v2: Add kernel commit id for reference. Cc: Anusha Srivatsa Cc: Clinton Taylor Signed-off-by: Rodrigo Vivi --- intel/intel_chipset.h | 16 +++

Re: [Mesa-dev] [PATCH 01/18] nir/spirv: Move a "}"

How did this even compile? Should we cc stable? Reviewed-by: Lionel Landwerlin On 29/06/17 18:33, Jason Ekstrand wrote: It's closing a "{" at the begining of a switch case. --- src/compiler/spirv/vtn_variables.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compil

[Mesa-dev] [PATCH 2/2] radv: lways set depthbuffer using image format instead of iview format.

We have some cases where changing between depth and stencil only aspect was causing hangs. Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 4

[Mesa-dev] [PATCH 1/2] radv: Disable depth & stencil tests when the depthbuffer doesn't support it.

Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_meta_blit.c | 4 ++-- src/amd/vulkan/radv_meta_blit2d.c | 4 ++-- src/amd/vulkan/radv_meta_clear.c | 2 +- src/amd/vulkan/radv_meta_decompress.c | 2 +- src/amd/vulkan/radv_pipeline.c| 22 +- s

Re: [Mesa-dev] [PATCH 05/14] gallium/radeon: clean up r600_texture_get_handle

Reviewed-by: Samuel Pitoiset On 06/29/2017 09:47 PM, Marek Olšák wrote: From: Marek Olšák --- src/gallium/drivers/radeon/r600_texture.c | 47 +++ 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gal

Re: [Mesa-dev] [PATCH 04/14] gallium/radeon: rename RADEON_FLAG_HANDLE -> RADEON_FLAG_NO_SUBALLOC

Looks better. Reviewed-by: Samuel Pitoiset On 06/29/2017 09:47 PM, Marek Olšák wrote: From: Marek Olšák --- src/gallium/drivers/r300/r300_texture.c | 2 +- src/gallium/drivers/radeon/r600_texture.c | 2 +- src/gallium/drivers/radeon/radeon_winsys.h| 2 +- src/gallium/winsy

Re: [Mesa-dev] [PATCH 01/14] radeonsi: add a HUD query for getting an average GFX BO list size

On 06/29/2017 09:47 PM, Marek Olšák wrote: From: Marek Olšák --- src/gallium/drivers/radeon/r600_query.c | 18 ++ src/gallium/drivers/radeon/r600_query.h | 1 + src/gallium/drivers/radeon/radeon_winsys.h| 1 + src/gallium/winsys/amdgpu/drm/am

Re: [Mesa-dev] [PATCH 0/9] glsl&co: misc cleanups and improvements

Patches 1, 2, 3, and 8 are Reviewed-by: Ian Romanick I sent some comments on 5, and I'm still thinking about 4. The rest are in areas that I don't know well. On 06/26/2017 02:40 AM, Nicolai Hähnle wrote: > Hi all, > > This is a bit of a random collection of small patches. What ties them > to

Re: [Mesa-dev] [PATCH 5/9] glsl: explicitly zero out padding to gl_shader_variable bitfield

On 06/26/2017 02:40 AM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > Otherwise, the padding bits remain undefined, which leads to valgrind > errors when storing the gl_shader_variable in the disk cache. libdrm used to use VG_CLEAR() for things like this. Having explicitly sized padding fiel

[Mesa-dev] [PATCH] dri2: Sync i965_pci_ids.h from Mesa.

Copied from Mesa with no modifications. Gives us Coffee Lake and Cannon Lake PCI IDs. Cc: Kenneth Graunke Cc: Eric Anholt Signed-off-by: Rodrigo Vivi --- hw/xfree86/dri2/pci_ids/i965_pci_ids.h | 23 +++ 1 file changed, 23 insertions(+) diff --git a/hw/xfree86/dri2/pci_ids

[Mesa-dev] [PATCH 2/2] radeonsi: drop few partial flushes when uploading bindless descriptors

Only emit partial flushes when the underlying shader stages are using bindless samplers or images. This gets rid of 4% of partial flushes in the DOW3 benchmark. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/radeonsi/si_descriptors.c | 18 -- 1 file changed, 16 insertion

[Mesa-dev] [PATCH 1/2] radeonsi: use a bitfield for tracking which shaders use bindless

This will allow to skip few partial flushes when bindless descriptors have to be re-uploaded. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/radeonsi/si_blit.c | 4 +-- src/gallium/drivers/radeonsi/si_pipe.h | 4 +-- src/gallium/drivers/radeonsi/si_state_shaders.c | 3

Re: [Mesa-dev] [PATCH] vc4: Introduce XML-based packet header generation like Intel's.

On Wed, Jun 28, 2017 at 1:18 PM, Eric Anholt wrote: > I really liked this idea, as it should help with management of packet > parsing tools like the CL dump. The python script is forked off of theirs > because our packets are byte-based instead of dwords, and the changes to > do so while avoiding

[Mesa-dev] [PATCH 13/14] gallium/radeon: allow suballocating textures

From: Marek Olšák --- src/gallium/drivers/radeon/r600_buffer_common.c | 3 +++ src/gallium/drivers/radeon/r600_texture.c | 13 - 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_bu

[Mesa-dev] [PATCH 11/14] gallium/radeon: add radeon_winsys::buffer_is_suballocated

From: Marek Olšák --- src/gallium/drivers/radeon/radeon_winsys.h| 3 +++ src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 8 src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 6 ++ 3 files changed, 17 insertions(+) diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gal

[Mesa-dev] [PATCH 10/14] gallium/radeon: clean up pb_cache bucket/usage determination

From: Marek Olšák --- src/gallium/drivers/radeon/radeon_winsys.h| 20 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 21 + src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 21 + 3 files changed, 30 insertions(+), 32 deletions(-) d

[Mesa-dev] [PATCH 14/14] winsys/amdgpu: use 128KB BOs for suballocations of up to 64KB BOs

From: Marek Olšák This decreases the number of BOs, but might also increase memory usage. It's better for small textures. The gameplay is on the far right: https://people.freedesktop.org/~mareko/suballoc.svg --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 3 ++- src/gallium/winsys/amdgpu/dr

[Mesa-dev] [PATCH 12/14] gallium/radeon: generalize the function for in-place texture reallocation

From: Marek Olšák --- src/gallium/drivers/radeon/r600_texture.c | 64 +-- 1 file changed, 43 insertions(+), 21 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index e21dc37..40cb8c0 100644 --- a/src/gal

[Mesa-dev] [PATCH 06/14] gallium/radeon: disallow exports of sparse and suballocated BOs

From: Marek Olšák I think it's unsafe, because the slabs can reuse exported storage. --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 7 +++ src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 7 +++ 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/src/gallium/winsys/amdgpu/

[Mesa-dev] [PATCH 09/14] gallium/radeon: enable suballocations for VRAM with no CPU access

From: Marek Olšák --- src/gallium/drivers/radeon/radeon_winsys.h| 15 --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 3 +++ src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 3 +++ 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeon/rad

[Mesa-dev] [PATCH 07/14] gallium/radeon: remove RADEON_FLAG_CPU_ACCESS

From: Marek Olšák https://lists.freedesktop.org/archives/amd-gfx/2017-June/010591.html --- src/gallium/drivers/radeon/r600_buffer_common.c | 4 src/gallium/drivers/radeon/radeon_winsys.h | 7 +++ src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 9 + src/gallium/winsys/amdg

[Mesa-dev] [PATCH 08/14] gallium/radeon: clean up (domain, flags) <-> (slab heap) translations

From: Marek Olšák This is cleaner, and we are down to 4 slabs. --- src/gallium/drivers/radeon/radeon_winsys.h| 62 +++ src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 44 +++- src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 2 +- src/gallium/winsy

[Mesa-dev] [PATCH 05/14] gallium/radeon: clean up r600_texture_get_handle

From: Marek Olšák --- src/gallium/drivers/radeon/r600_texture.c | 47 +++ 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index c811d6a..e21dc37 100644 --- a/src/gal

[Mesa-dev] [PATCH 03/14] gallium/radeon: fix a possible crash for buffer exports

From: Marek Olšák --- src/gallium/drivers/radeon/r600_texture.c | 24 +++- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index d68587b..139ab13 100644 --- a/src/gallium/dri

[Mesa-dev] [PATCH 02/14] gallium/radeon: ignore PIPE_BIND_SHARED for buffers

From: Marek Olšák BO exports can't be predicted this way. --- src/gallium/drivers/radeon/r600_buffer_common.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c index 5336f55..342695c 100644 ---

[Mesa-dev] [PATCH 04/14] gallium/radeon: rename RADEON_FLAG_HANDLE -> RADEON_FLAG_NO_SUBALLOC

From: Marek Olšák --- src/gallium/drivers/r300/r300_texture.c | 2 +- src/gallium/drivers/radeon/r600_texture.c | 2 +- src/gallium/drivers/radeon/radeon_winsys.h| 2 +- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 6 +++--- src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 4 ++--

[Mesa-dev] [PATCH 01/14] radeonsi: add a HUD query for getting an average GFX BO list size

From: Marek Olšák --- src/gallium/drivers/radeon/r600_query.c | 18 ++ src/gallium/drivers/radeon/r600_query.h | 1 + src/gallium/drivers/radeon/radeon_winsys.h| 1 + src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 3 +++ src/gallium/winsys/amdg

[Mesa-dev] [PATCH 00/14] AMD winsys cleanups, heaps, suballocation for textures

Hi, This is mainly a cleanup series. RADEON_FLAG_CPU_ACCESS(_REQUIRED) is no longer used. CPU access can only be disallowed from now on, but it can't be enforced. See amd-gfx for more discussion. If we stay conservative, we only need 5 memory heaps, including the VRAM_GTT heap, which isn't used

[Mesa-dev] [PATCH] swr: Minor cleanup of variable usage, no functional change.

In swr_update_derived, for consistency, index buffer validation should be using the p_draw_info copy "info" rather than referencing p_draw_info. No functional change. --- src/gallium/drivers/swr/swr_state.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/driv

Re: [Mesa-dev] [PATCH v3 5/5] android: build imx-drm winsys

On 29 June 2017 at 16:35, Robert Foss wrote: > On Thu, 2017-06-29 at 15:28 +0100, Emil Velikov wrote: >> On 28 June 2017 at 22:52, Robert Foss >> wrote: >> > From: Tomeu Vizoso >> > >> > Add Android.mk for winsys/imx/drm. >> > >> > Signed-off-by: Tomeu Vizoso >> > Reviewed-by: Tapani Pälli >>

Re: [Mesa-dev] [PATCH 2/5] vc4: Switch back to using a local copy of vc4_drm.h.

On 29 June 2017 at 16:38, Eric Anholt wrote: > Emil Velikov writes: > >> Hi Eric, >> >> On 29 June 2017 at 02:15, Eric Anholt wrote: >>> Needing to get our uapi header from libdrm has only complicated things. >>> Follow intel's lead and drop our requirement for it. >>> >> UAPI: I think I may hav

Re: [Mesa-dev] [PATCH] vc4: Introduce XML-based packet header generation like Intel's.

Kenneth Graunke writes: > [ Unknown signature status ] > On Wednesday, June 28, 2017 11:18:40 AM PDT Eric Anholt wrote: >> I really liked this idea, as it should help with management of packet >> parsing tools like the CL dump. The python script is forked off of theirs >> because our packets are

Re: [Mesa-dev] [PATCH v2] intel: Move the DRM uapi headers to a non-Intel location.

On Thu, Jun 29, 2017 at 10:42 AM, Eric Anholt wrote: > I want to remove vc4's dependency on headers from libdrm as well, but > storing multiple copies of drm_fourcc.h in our tree would be silly. > > v2: Update Android.mk as well, move distcheck drm*.h references to > top-level noinst_HEADERS.

[Mesa-dev] [Bug 101614] OSMesa 17.1.3 simd16intrin build FAIL on Win/MinGW - 'expected initializer before _simd16_setzero_ps ...'

https://bugs.freedesktop.org/show_bug.cgi?id=101614 --- Comment #8 from Trevor SANDY --- MSYS2 Setup Details - FYI MSYS2 Install: • Download and install msys2-x86_64-.exe (see instructions at http://www.msys2.org/) • Install to C:\msys64 (be sure to check 'Run MSYS2 now.' on the last install dia

Re: [Mesa-dev] [PATCH 1/8] swr/rast: Split backend.cpp to improve compile time

> On Jun 28, 2017, at 3:56 AM, Emil Velikov wrote: > > On 26 June 2017 at 17:14, Rowley, Timothy O > wrote: >> >> On Jun 26, 2017, at 7:57 AM, Emil Velikov wrote: > +.INTERMEDIATE: backend.intermediate >>> I have limited experience with .INTERMEDIATE and it didn't seem to >>> bri

Re: [Mesa-dev] [PATCH v2] intel: Move the DRM uapi headers to a non-Intel location.

On Thu, Jun 29, 2017 at 11:42 AM, Eric Anholt wrote: > I want to remove vc4's dependency on headers from libdrm as well, but > storing multiple copies of drm_fourcc.h in our tree would be silly. > > v2: Update Android.mk as well, move distcheck drm*.h references to > top-level noinst_HEADERS.

Re: [Mesa-dev] [Intel-gfx] [PATCH libdrm 3/3] intel: PCI Ids for U SKU in CFL

series merged to libdrm. thanks for patches and review. On Wed, Jun 28, 2017 at 2:09 PM, Clint Taylor wrote: > > > On 06/21/2017 09:39 AM, Anusha Srivatsa wrote: >> >> Add the PCI IDs for U SKU IN CFL by following the spec. >> >> v2: Update IDs >> >> Cc: Rodrigo Vivi >> Signed-off-by: Anusha Sri

[Mesa-dev] [PATCH 12/18] nir/spirv: Compute offsets for UBOs and SSBOs up-front

Now that we have a pointer wrapper class, we can create offsets for UBOs and SSBOs up-front instead of waiting until we have the full access chain. For push constants, we still use the old mechanism because it provides us with some nice range information. --- src/compiler/spirv/vtn_private.h |

[Mesa-dev] [PATCH 16/18] nir/spirv: Stop using glsl_type for function types

We're going to want the full vtn_type available to us anyway at which point glsl_type isn't really buying us anything. --- src/compiler/spirv/spirv_to_nir.c | 23 +-- src/compiler/spirv/vtn_cfg.c | 30 +- src/compiler/spirv/vtn_private.h | 9 +

[Mesa-dev] [PATCH 15/18] nir/spirv: Beef up the type system a bit

This adds a vtn concept of base_type as well as a couple of other fields. This lets us be a tiny bit more efficient in some cases but, more importantly, it will eventually let us express things the GLSL type system can't. --- src/compiler/spirv/spirv_to_nir.c | 67 +++-

[Mesa-dev] [PATCH 17/18] nir/spirv: Use real pointer types

--- src/compiler/spirv/spirv_to_nir.c | 23 +-- src/compiler/spirv/vtn_cfg.c | 12 ++-- src/compiler/spirv/vtn_private.h | 18 ++ src/compiler/spirv/vtn_variables.c | 13 ++--- 4 files changed, 55 insertions(+), 11 deletions(-) diff --g

[Mesa-dev] [PATCH 11/18] nir/spirv: Rework the way pointers get dereferenced

This has the advantage of moving all of the "extend an access chain" code into one place. --- src/compiler/spirv/vtn_private.h | 8 ++- src/compiler/spirv/vtn_variables.c | 144 + 2 files changed, 88 insertions(+), 64 deletions(-) diff --git a/src/compiler/

[Mesa-dev] [PATCH 14/18] nir/spirv: Compact vtn_type

Use an anonymous union of structs to help keep the structure small and better organized. --- src/compiler/spirv/spirv_to_nir.c | 1 - src/compiler/spirv/vtn_private.h | 64 --- 2 files changed, 39 insertions(+), 26 deletions(-) diff --git a/src/compiler/spirv

[Mesa-dev] [PATCH 13/18] nir/spirv: Simplify type copying

--- src/compiler/spirv/spirv_to_nir.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 3d9ef76..c69cb8c 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -

[Mesa-dev] [PATCH 18/18] nir/spirv: Rework function argument setup

Now that we have proper pointer types, we can be more sensible about the way we set up function arguments and deal with the two cases of pointer vs. SSA parameters distinctly. --- src/compiler/spirv/vtn_cfg.c | 62 +--- 1 file changed, 35 insertions(+), 27 d

  1   2   >