Re: [Mesa-dev] [PATCH] i965: Extend the negative 32-bit deltas to 64-bits

Hello, Mark. I've done: Cc, Tested-by and Reviewed-by also added. On Wed, Apr 4, 2018 at 8:16 AM, Mark Janes wrote: > This patch passes Intel's CI suites. > It needs a CC for stable in the commit message. > > Tested-by: Mark Janes > > Sergii Romantsov writes: > > > Gen8+ use 48-bit address rel

[Mesa-dev] [PATCH v3] i965: Extend the negative 32-bit deltas to 64-bits

Gen8+ use 48-bit address relocations so need to extend the sign to 64-bit return value. Without it we have higher bits zeroed and missing the negavive values. Haswell and older use 32-bit deltas so are unaffected by this issue. v2: used int32_t fucntion parameter instead of explicit type convers

Re: [Mesa-dev] [PATCH] vbo: Use alloca for _vbo_draw_indirect.

Hi, > This adds uses of alloca, without a corresponding include of alloca.h. > > Perhaps something like the attached is needed? Yes, sorry! Reviewed-by: Mathias Fröhlich best Mathias ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https:

Re: [Mesa-dev] [PATCH 02/11] gallium: Use _DrawVAO for edgeflag enabled check.

Hi, On Tuesday, 3 April 2018 22:23:55 CEST Roland Scheidegger wrote: > Not a review, but these aren't gallium changes, but rather state tracker > ones, so should be st/mesa rather than gallium. > (gallium would be changes to the gallium interface.) Ok, I have changed that! Thanks! BTW I have pus

[Mesa-dev] [AppVeyor] mesa master #7373 failed

Build mesa 7373 failed Commit 41ac0b1443 by Iago Toral Quiroga on 4/2/2018 9:39 AM: compiler/spirv: set is_shadow for depth comparitor sampling opcodes\n\nFrom the SPIR-V spec, OpTypeImage:\n\n"Depth is whether or not this image is a depth image. (Note that\n w

[Mesa-dev] [Bug 105871] Discolored KDE panels after updating to Mesa 18.0 on Intel broadwell

https://bugs.freedesktop.org/show_bug.cgi?id=105871 --- Comment #2 from kamalah...@openmailbox.org --- My apologies for not including X.org version. The x.org version is 1.19.5 name of display::0 version number:11.0 vendor string:The X.Org Foundation vendor release number:11905000

[Mesa-dev] [PATCH 1/2] nir/lower_vec_to_movs: Generate the write mask early in try_coalesce

It will soon be useful to have this as a separate step. --- src/compiler/nir/nir_lower_vec_to_movs.c | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/compiler/nir/nir_lower_vec_to_movs.c b/src/compiler/nir/nir_lower_vec_to_movs.c index 8b24376..610a362

[Mesa-dev] [PATCH 2/2] nir/lower_vec_to_movs: Coalesce reg writes there are no hazards

Instead of just giving up on coalescing if the destination of the vecN is a register, we look to see if there are any hazards that would prevent us from moving the write earlier. This allows us to handle a few more cases. Shader-db results on Haswell: total instructions in shared programs: 1

Re: [Mesa-dev] [PATCH] i965: Extend the negative 32-bit deltas to 64-bits

This patch passes Intel's CI suites. It needs a CC for stable in the commit message. Tested-by: Mark Janes Sergii Romantsov writes: > Gen8+ use 48-bit address relocations so need to extend the sign > to 64-bit return value. Without it we have higher bits zeroed > and missing the negavive value

Re: [Mesa-dev] [PATCH v5 06/19] intel/isl: Add support to emit clear value address.

On Tue, Apr 3, 2018 at 9:40 PM, Pohjolainen, Topi < topi.pohjolai...@gmail.com> wrote: > On Tue, Apr 03, 2018 at 09:38:52PM -0700, Jason Ekstrand wrote: > > On Tue, Apr 3, 2018 at 8:23 PM, Pohjolainen, Topi < > > topi.pohjolai...@gmail.com> wrote: > > > > > On Tue, Apr 03, 2018 at 02:55:31PM -0700

Re: [Mesa-dev] [PATCH v5 06/19] intel/isl: Add support to emit clear value address.

On Tue, Apr 03, 2018 at 09:38:52PM -0700, Jason Ekstrand wrote: > On Tue, Apr 3, 2018 at 8:23 PM, Pohjolainen, Topi < > topi.pohjolai...@gmail.com> wrote: > > > On Tue, Apr 03, 2018 at 02:55:31PM -0700, Jason Ekstrand wrote: > > > On Tue, Apr 3, 2018 at 8:05 AM, Pohjolainen, Topi < > > > topi.pohj

Re: [Mesa-dev] [PATCH v5 06/19] intel/isl: Add support to emit clear value address.

On Tue, Apr 3, 2018 at 8:23 PM, Pohjolainen, Topi < topi.pohjolai...@gmail.com> wrote: > On Tue, Apr 03, 2018 at 02:55:31PM -0700, Jason Ekstrand wrote: > > On Tue, Apr 3, 2018 at 8:05 AM, Pohjolainen, Topi < > > topi.pohjolai...@gmail.com> wrote: > > > > > On Thu, Mar 29, 2018 at 10:58:40AM -0700

Re: [Mesa-dev] Status of radeonsi NIR

On 31/03/18 02:44, Benedikt Schemmer wrote: Hi all, I did some more testing with NIR and wanted to share the results. https://github.com/bendat78/mymesa/tree/mymesa2/testresults Overall it seems nir could be better than tgsi, but there are some shaders with significant regressions and I think t

Re: [Mesa-dev] [PATCH] gallium: add CAP for postprocess filters

On 04/04/18 13:22, Roland Scheidegger wrote: Am 04.04.2018 um 05:03 schrieb Timothy Arceri: On 04/04/18 12:44, Roland Scheidegger wrote: Am 04.04.2018 um 04:32 schrieb Timothy Arceri: On 04/04/18 11:58, Roland Scheidegger wrote: AFAIK these filters (and I've never looked into them) should be

[Mesa-dev] [Bug 105871] Discolored KDE panels after updating to Mesa 18.0 on Intel broadwell

https://bugs.freedesktop.org/show_bug.cgi?id=105871 --- Comment #1 from Tapani Pälli --- Please include also Xorg version. This seems very much like bug #103699. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.

Re: [Mesa-dev] [PATCH] gallium: add CAP for postprocess filters

Am 04.04.2018 um 05:03 schrieb Timothy Arceri: > On 04/04/18 12:44, Roland Scheidegger wrote: >> Am 04.04.2018 um 04:32 schrieb Timothy Arceri: >>> On 04/04/18 11:58, Roland Scheidegger wrote: AFAIK these filters (and I've never looked into them) should be transparent to hw drivers. Hence

Re: [Mesa-dev] [PATCH v5 06/19] intel/isl: Add support to emit clear value address.

On Tue, Apr 03, 2018 at 02:55:31PM -0700, Jason Ekstrand wrote: > On Tue, Apr 3, 2018 at 8:05 AM, Pohjolainen, Topi < > topi.pohjolai...@gmail.com> wrote: > > > On Thu, Mar 29, 2018 at 10:58:40AM -0700, Rafael Antognolli wrote: > > > gen10 can emit the clear color by setting it on a buffer somewhe

Re: [Mesa-dev] [PATCH] gallium: add CAP for postprocess filters

On 04/04/18 12:44, Roland Scheidegger wrote: Am 04.04.2018 um 04:32 schrieb Timothy Arceri: On 04/04/18 11:58, Roland Scheidegger wrote: AFAIK these filters (and I've never looked into them) should be transparent to hw drivers. Hence a cap bit doesn't make sense, and if it's broken we shouldn't

Re: [Mesa-dev] [PATCH] gallium: add CAP for postprocess filters

Am 04.04.2018 um 04:32 schrieb Timothy Arceri: > On 04/04/18 11:58, Roland Scheidegger wrote: >> AFAIK these filters (and I've never looked into them) should be >> transparent to hw drivers. Hence a cap bit doesn't make sense, and if >> it's broken we shouldn't just paper over this. > > I created

Re: [Mesa-dev] [PATCH] gallium: add CAP for postprocess filters

On Tue, Apr 3, 2018, 10:32 PM Timothy Arceri wrote: > On 04/04/18 11:58, Roland Scheidegger wrote: > > AFAIK these filters (and I've never looked into them) should be > > transparent to hw drivers. Hence a cap bit doesn't make sense, and if > > it's broken we shouldn't just paper over this. > > I

Re: [Mesa-dev] [PATCH] gallium: add CAP for postprocess filters

On 04/04/18 12:32, Timothy Arceri wrote: On 04/04/18 11:58, Roland Scheidegger wrote: AFAIK these filters (and I've never looked into them) should be transparent to hw drivers. Hence a cap bit doesn't make sense, and if it's broken we shouldn't just paper over this. Also just to be clear these

Re: [Mesa-dev] [PATCH] gallium: add CAP for postprocess filters

On 04/04/18 11:58, Roland Scheidegger wrote: AFAIK these filters (and I've never looked into them) should be transparent to hw drivers. Hence a cap bit doesn't make sense, and if it's broken we shouldn't just paper over this. I created a CAP because the AMD devs have no interest in supporting t

[Mesa-dev] [PATCH 13/17] radeonsi: clear up controlling the DCC MSAA level of support

From: Marek Olšák --- src/gallium/drivers/radeon/r600_texture.c | 4 ++-- src/gallium/drivers/radeonsi/si_pipe.c| 2 ++ src/gallium/drivers/radeonsi/si_pipe.h| 1 + 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/dri

[Mesa-dev] [PATCH 15/17] radeonsi: always prefetch later shaders after the draw packet

From: Marek Olšák so that the draw is started as soon as possible. --- src/gallium/drivers/radeonsi/si_cp_dma.c | 68 ++-- src/gallium/drivers/radeonsi/si_pipe.h | 2 +- src/gallium/drivers/radeonsi/si_state_draw.c | 11 - src/util/bitscan.h

[Mesa-dev] [PATCH 17/17] winsys/amdgpu: always set AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE

From: Marek Olšák There is a kernel patch that adds the new flag. --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 36 ++- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_

[Mesa-dev] [PATCH 06/17] radeonsi: don't do GFX-specific texture decompression for compute

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_blit.c | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index d9d489825f8..45770b0d9bf 100644 --- a/src/gallium/drivers

[Mesa-dev] [PATCH 14/17] radeonsi: emit shader pointers before cache flushes & waits

From: Marek Olšák This code was written with the constant engine in mind. We can simplify it now. --- src/gallium/drivers/radeonsi/si_state_draw.c | 20 +++- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium

[Mesa-dev] [PATCH 16/17] radeonsi: don't emit partial flushes at the end of IBs (v3) (revisited)

From: Marek Olšák Now draw calls from multiple IBs can be executed in parallel. v2: do emit partial flushes on SI v3: invalidate all shader caches at the beginning of IBs If we artificially limit the number of draw calls per IB to 5, we'll get a lot more IBs, leading to a lot more partial flush

[Mesa-dev] [PATCH 08/17] radeonsi: merge 2 identical if statements in si_clear

From: Marek Olšák and other cleanups --- src/gallium/drivers/radeonsi/si_clear.c | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 464b9d7ac56..8aa27b7f405 100644 --- a/src/gall

[Mesa-dev] [PATCH 11/17] radeonsi: disable TC-compat HTILE on Tonga and Iceland

From: Marek Olšák --- src/gallium/drivers/radeon/r600_texture.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 55670945b90..8d4d771155a 100644 --- a/src/gallium/drivers/radeon/r600_texture.c

[Mesa-dev] [PATCH 05/17] radeonsi: simplify generating the renderer string

From: Marek Olšák HAVE_LLVM > 0 is a tautology. --- src/gallium/drivers/radeonsi/si_get.c | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index f75c97685ce..b47b22709f2 100644

[Mesa-dev] [PATCH 09/17] radeonsi: don't flush HTILE if there is no HTILE clear

From: Marek Olšák --- src/gallium/drivers/radeonsi/si_clear.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 8aa27b7f405..cbb5e909d3a 100644 --- a/src/gallium/drivers/radeonsi/si_clear

[Mesa-dev] [PATCH 07/17] radeonsi: skip DCC render feedback checking if color writes are disabled

From: Marek Olšák The previous patch is required for this. --- src/gallium/drivers/radeonsi/si_blit.c | 5 + src/gallium/drivers/radeonsi/si_pipe.h | 17 + src/gallium/drivers/radeonsi/si_state_shaders.c | 6 +- 3 files changed, 23 insertions(+), 5 del

[Mesa-dev] [PATCH 12/17] radeonsi/gfx9: don't use the workaround for gather4 + stencil

From: Marek Olšák it doesn't seem to be needed. --- src/gallium/drivers/radeonsi/si_state.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index cd64d3bc0fb..f7560645ae9 100644

[Mesa-dev] [PATCH 02/17] ac/surface: don't set the display flag for obviously unsupported cases

From: Marek Olšák This enables the tile swizzle for some cases of the displayable micro mode, and it also fixes an addrlib assertion failure on Vega. --- src/amd/common/ac_surface.c | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_surface.

[Mesa-dev] [PATCH 10/17] radeonsi: force 2D tiling on VI only when TC-compat HTILE is really enabled

From: Marek Olšák just pass the flag that indicates it. --- src/gallium/drivers/radeon/r600_texture.c | 14 ++ 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index ae9623a829d..55670

[Mesa-dev] [PATCH 01/17] ac/surface/gfx9: request desired micro tile mode explicitly

From: Marek Olšák --- src/amd/common/ac_surface.c | 20 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 1e1641daeec..b294cd85259 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_su

[Mesa-dev] [PATCH 03/17] ac/surface: only set the display flag for 4-channel images

From: Marek Olšák --- src/amd/common/ac_surface.c| 3 ++- src/amd/common/ac_surface.h| 1 + src/amd/vulkan/radv_image.c| 1 + src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 1 + 4 files changed, 5 insertions(+), 1 deletion(-) diff --

[Mesa-dev] [PATCH 04/17] winsys/amdgpu: allow local BOs on APUs

From: Marek Olšák Local BOs ignore BO priorities, and we don't need those on APUs. --- src/amd/common/ac_gpu_info.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 0c131d0ed0c..ef0364b0534 100644 --- a/src/am

Re: [Mesa-dev] [PATCH] gallium: add CAP for postprocess filters

AFAIK these filters (and I've never looked into them) should be transparent to hw drivers. Hence a cap bit doesn't make sense, and if it's broken we shouldn't just paper over this. Roland Am 03.04.2018 um 13:38 schrieb Timothy Arceri: > For radeonsi these seem to have been somewhat broken for ove

Re: [Mesa-dev] [PATCH] nir/lower_vec_to_movs: Only coalesce if the vec had a SSA destination

On Fri, Mar 23, 2018 at 11:35 AM, Jason Ekstrand wrote: > Otherwise we may end up trying to coalesce in a case such as > > ssa_1 = fadd r1, r2 > r3.x = fneg(r2); > r3 = vec4(ssa_1, ssa_1.y, ...) > > and that would cause us to move the writes to r3 from the vec to the > fadd which would re-order th

Re: [Mesa-dev] [PATCH] st/nine: Declare lighting consts for ff shaders

Tested-by: Dieter Nützel on RX580 together with wine-staging 3.5 with LS 2015 but NOT explicitly with the mentioned shader Dieter Am 02.04.2018 18:50, schrieb Axel Davy: The lighting constants were not declared previously, but were accessed with indirect addressing, which is illegal. Fixes:

Re: [Mesa-dev] [PATCH] shader-db: Add hooks for open64 and fstat64 to intel_stub

Jason Ekstrand writes: > This gets the stub working again with meson builds of Mesa works, Reviewed-by: Scott D Phillips > --- > intel_stub.c | 51 +++ > 1 file changed, 51 insertions(+) > > diff --git a/intel_stub.c b/intel_stub.c > index aba82

Re: [Mesa-dev] [PATCH] radeonsi: skip DCC render feedback checking if color writes are disabled

Tested-by: Dieter Nützel on RX580 with glmark2, UH, UV, Blender, FreeCAD, Krita 4.0.0, KDE Plasma5 Dieter Am 02.04.2018 05:54, schrieb Marek Olšák: From: Marek Olšák --- src/gallium/drivers/radeonsi/si_blit.c | 5 + src/gallium/drivers/radeonsi/si_pipe.h | 17 +++

[Mesa-dev] [PATCH] shader-db: Add hooks for open64 and fstat64 to intel_stub

This gets the stub working again with meson builds of Mesa --- intel_stub.c | 51 +++ 1 file changed, 51 insertions(+) diff --git a/intel_stub.c b/intel_stub.c index aba82c9..ab046e5 100644 --- a/intel_stub.c +++ b/intel_stub.c @@ -40,10 +40,13 @@

Re: [Mesa-dev] [PATCH shaderdb] run: shader program file created via GetProgramBinary (v5)

On Fri, Mar 23, 2018 at 5:56 PM, Dongwon Kim wrote: > With optin '-b', shader-db now generates a shader program binary file > using GetProgramBinary(). This shader program binary can be loaded via > ProgramBinary() to be executed by an application later. Help me understand your use case. Why the

Re: [Mesa-dev] [PATCH shaderdb] run: -p option accepts hex format pci-id

On Wednesday, March 14, 2018 5:49:35 PM PDT Dongwon Kim wrote: > -p option now takes hex format pci-id of target architecture. > > Signed-off-by: Dongwon Kim > --- > run.c | 35 +-- > 1 file changed, 25 insertions(+), 10 deletions(-) I had a few more comments, bu

Re: [Mesa-dev] [PATCH v3 000/104] nir: Move to using instructions for derefs

I ran shader-db on the whole series and this is what I got on KBL: total instructions in shared programs: 15201981 -> 15231264 (0.19%) instructions in affected programs: 315139 -> 344422 (9.29%) helped: 33 HURT: 1253 This should by and large be a no-op but clearly something is amiss. I'll take a

[Mesa-dev] [Bug 103814] incorrect dust rendering in hl2 without sisched

https://bugs.freedesktop.org/show_bug.cgi?id=103814 Timothy Arceri changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

Re: [Mesa-dev] [PATCH 3/4] glsl/nir: fix variable type for image intrinsics and ubos

On 04/04/18 10:13, Jason Ekstrand wrote: . On Tue, Apr 3, 2018 at 6:21 AM, Karol Herbst > wrote: If the bindless image is passed through a struct we ended up getting the glsl_type of the struct, not the image. variable_referenced points to the declarati

Re: [Mesa-dev] [PATCH 1/4] nir/split_var_copies: handle IMAGE and SAMPLER for bindless vars

I have a very strong feeling that this isn't the only place where reading/writing IMAGE and SAMPLER variables is going to cause NIR heartburn. For example, we have special cases in nir_validate for SUBROUTINE variables and we probably need IMAGE and SAMPLER support everywhere we have SUBROUTINE pl

Re: [Mesa-dev] [PATCH 4/4] RFC nir: add support for bindless_texture images

On Tue, Apr 3, 2018 at 6:21 AM, Karol Herbst wrote: > I added another source for all image_var_* intrinsics. Drivers have to be > adjusted with this change. > > There was some discussion to add new intrinsics to handle operations on > bindless images. Maybe we can continue with this here? > > Sig

Re: [Mesa-dev] [PATCH 2/4] nir: add support for bindless_texture samplers

On Tue, Apr 3, 2018 at 6:21 AM, Karol Herbst wrote: > Signed-off-by: Karol Herbst > --- > src/compiler/glsl/glsl_to_nir.cpp | 17 +++-- > src/compiler/nir/nir.h| 1 + > src/compiler/nir/nir_print.c | 3 +++ > 3 files changed, 19 insertions(+), 2 deletions(-) > > d

Re: [Mesa-dev] [PATCH 3/4] glsl/nir: fix variable type for image intrinsics and ubos

. On Tue, Apr 3, 2018 at 6:21 AM, Karol Herbst wrote: > If the bindless image is passed through a struct we ended up getting the > glsl_type of the struct, not the image. > > variable_referenced points to the declaration of the struct, so it won't > work > for bindless images. So just drop it. >

[Mesa-dev] [Bug 105567] meson/ninja: 1. mesa/vdpau incorrect symlinks in DESTDIR and 2. Ddri-drivers-path Dvdpau-libs-path overrides DESTDIR

https://bugs.freedesktop.org/show_bug.cgi?id=105567 --- Comment #2 from LoneVVolf --- Added Jan Steffens aka Heftig to cc list, as he's the autor of the patch. Also added the release manager for 18.0 , Emil Velikov , as this bug breaks vdpau hw accelereation in stable mesa 18.0 when built with

[Mesa-dev] [Bug 105567] meson/ninja: 1. mesa/vdpau incorrect symlinks in DESTDIR and 2. Ddri-drivers-path Dvdpau-libs-path overrides DESTDIR

https://bugs.freedesktop.org/show_bug.cgi?id=105567 LoneVVolf changed: What|Removed |Added CC||emil.l.veli...@gmail.com,

[Mesa-dev] [Bug 105567] meson/ninja: 1. mesa/vdpau incorrect symlinks in DESTDIR and 2. Ddri-drivers-path Dvdpau-libs-path overrides DESTDIR

https://bugs.freedesktop.org/show_bug.cgi?id=105567 LoneVVolf changed: What|Removed |Added Priority|medium |highest Severity|normal

[Mesa-dev] [Bug 105871] Discolored KDE panels after updating to Mesa 18.0 on Intel broadwell

https://bugs.freedesktop.org/show_bug.cgi?id=105871 Bug ID: 105871 Summary: Discolored KDE panels after updating to Mesa 18.0 on Intel broadwell Product: Mesa Version: unspecified Hardware: x86-64 (AMD64) OS

Re: [Mesa-dev] [PATCH 00/14] Enable sRGB-encoded fast-clears on CannonLake

I think I've reviewed all the ones that make significant functional changes. The exception is the patch that makes us not do a fast depth clear. I think what you did is probably better but I haven't thought about it enough to be sure. I'm not sure what I think about the last several that mostly

Re: [Mesa-dev] [PATCH 12/14] i965/blorp: Also skip the fast clear if the clear color differs

Oops. This one is probably my fault. :-( Reviewed-by: Jason Ekstrand On Fri, Mar 30, 2018 at 11:12 AM, Nanley Chery wrote: > If the aux state is CLEAR and clear color value has changed, only the > surface state must be updated. The bit-pattern in the aux buffer is > exactly the same. > --- >

Re: [Mesa-dev] [PATCH 07/14] i965/meta_util: Re-enable sRGB-encoded fast-clears on CNL

2-7 are Reviewed-by: Jason Ekstrand On Fri, Mar 30, 2018 at 11:12 AM, Nanley Chery wrote: > The paths which sample with the clear color are now using a getter which > performs the sRGB decode needed to enable this fast clear. > > This path can be exercised by fast-clearing a texture, then perf

Re: [Mesa-dev] [PATCH 01/14] i965: Use the brw_context for the clear color and value setters

Yeah, brw is always better for i965 functions. Reviewed-by: Jason Ekstrand On Fri, Mar 30, 2018 at 11:12 AM, Nanley Chery wrote: > Do what all the other functions in the miptree API do. > --- > src/mesa/drivers/dri/i965/brw_blorp.c | 2 +- > src/mesa/drivers/dri/i965/brw_clear.c

Re: [Mesa-dev] [PATCH v5 13/19] i965/blorp: Update the fast clear value buffer.

On Thu, Mar 29, 2018 at 10:58 AM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > On Gen10, whenever we do a fast clear, blorp will update the clear color > state buffer for us, as long as we set the clear color address > correctly. > > However, on a hiz clear, if the surface is already

Re: [Mesa-dev] [PATCH v5 12/19] i965: Add aux_buf variable to simplify code.

On Thu, Mar 29, 2018 at 10:58 AM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > In a follow up patch, we make use of clear_color_bo, which is in > mt->mcs_buf or mt->hiz_buf. To avoid duplicating more code that does the > same thing on both aux buffers, just use aux_buf already. > > v5

Re: [Mesa-dev] [PATCH v5 06/19] intel/isl: Add support to emit clear value address.

On Tue, Apr 3, 2018 at 8:05 AM, Pohjolainen, Topi < topi.pohjolai...@gmail.com> wrote: > On Thu, Mar 29, 2018 at 10:58:40AM -0700, Rafael Antognolli wrote: > > gen10 can emit the clear color by setting it on a buffer somewhere, and > > then adding only the address to the surface state. > > > > Thi

Re: [Mesa-dev] [PATCH v5 05/19] intel: Use Clear Color struct size.

On Thu, Mar 29, 2018 at 10:58 AM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > The size of the clear color struct (expected by the hardware) is 8 > dwords (isl_dev.ss.clear_value_state_size here). But we still need to > track the size of the clear color, used when memcopying it to/fro

Re: [Mesa-dev] [PATCH 5/5] i965/miptree: Don't gtt map from map_depthstencil

On Tue, Apr 03, 2018 at 11:53:19AM -0700, Scott D Phillips wrote: > Nanley Chery writes: > > > On Tue, Jan 09, 2018 at 11:17:02PM -0800, Scott D Phillips wrote: > >> Instead of gtt mapping, call out to other map functions (map_map > >> or map_tiled_memcpy) for the depth surface. Removes a place w

Re: [Mesa-dev] [PATCH] anv: Fix close(fd) before import issue in vkCreateDmaBufImageINTEL

Wow, good work us... Reviewed-by: Jason Ekstrand On Tue, Apr 3, 2018 at 2:21 PM, Kevin Strasser wrote: > If we close the fd before calling DRM_IOCTL_PRIME_FD_TO_HANDLE the kernel > will hit a -EBADF error. Move the close(fd) call to the end of > anv_CreateDmaBufImageINTEL(). > > Signed-off-by:

[Mesa-dev] [PATCH] anv: Fix close(fd) before import issue in vkCreateDmaBufImageINTEL

If we close the fd before calling DRM_IOCTL_PRIME_FD_TO_HANDLE the kernel will hit a -EBADF error. Move the close(fd) call to the end of anv_CreateDmaBufImageINTEL(). Signed-off-by: Kevin Strasser --- src/intel/vulkan/anv_intel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --

Re: [Mesa-dev] [PATCH] vulkan/wsi/wayland: fix leaks

Hi James, On 30 March 2018 at 16:45, James Legg wrote: > Fixes: bfa22266cd vulkan/wsi/wayland: Add support for zwp_dmabuf > CC: Daniel Stone > CC: Jason Ekstrand Wow, the cleanup hunk must have been lost in a rebase somewhere. :( At least, I think I remember writing it. Thanks a lot for the p

Re: [Mesa-dev] [PATCH 08/11] i965: perf: snapshot RPSTAT1 register

On 03/04/18 19:20, Kenneth Graunke wrote: diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c b/src/mesa/drivers/dri/i965/brw_performance_query.c index 98666759d75..7d5b44cf61d 100644 --- a/src/mesa/drivers/dri/i965/brw_performance_query.c +++ b/src/mesa/drivers/dri/i965/brw_performan

Re: [Mesa-dev] [PATCH 00/12] etnaviv: support performance monitor

Full series is tested on an i.MX6qp (GC3000) using GALLIUM_HUD to display various HW perf counters. Tested-by: Chris Healy On Sun, Mar 25, 2018 at 1:29 PM, Christian Gmeiner < christian.gmei...@gmail.com> wrote: > Starting with kernel 4.16 the etnaviv driver exports perfmon domains > and signal

Re: [Mesa-dev] [RFC] - Rewrite mesa website in Sphinx

Hi Laura, Aurelio Silves pointed me out that there is the possibility of using pandoc for the conversion of mesa html sources to rst. You can take a look here: https://pandoc.org/index.html Depending on your distribution, probably there is a package for this. Also, if there is anything else

Re: [Mesa-dev] [PATCH 02/11] gallium: Use _DrawVAO for edgeflag enabled check.

Not a review, but these aren't gallium changes, but rather state tracker ones, so should be st/mesa rather than gallium. (gallium would be changes to the gallium interface.) Roland Am 01.04.2018 um 20:13 schrieb mathias.froehl...@gmx.net: > From: Mathias Fröhlich > > Signed-off-by: Mathias Frö

[Mesa-dev] [PATCH v2 5/5] i965/miptree: Don't gtt map from map_depthstencil

Instead of gtt mapping, call out to other map functions (map_map or map_tiled_memcpy) for the depth surface. Removes a place where gtt mapping is used. v2: add level, slice to debug print (Nanley) --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 52 --- 1 file changed,

[Mesa-dev] [PATCH 0/5] 86 gtt maps

Here is a resend of the series to remove gtt maps, with the addition of using MOVNTDQA when detiling which should help if we happen to detile from a WC map. Scott D Phillips (5): i965/tiled_memcpy: ytiled_to_linear a cache line at a time i965/tiled_memcpy: inline movntdqa loads in tiled_to_lin

[Mesa-dev] [PATCH 2/5] i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear

The reference for MOVNTDQA says: For WC memory type, the nontemporal hint may be implemented by loading a temporary internal buffer with the equivalent of an aligned cache line without filling this data to the cache. [...] Subsequent MOVNTDQA reads to unread portions of the WC

[Mesa-dev] [PATCH v4 3/5] i965/miptree: Use cpu tiling/detiling when mapping

Rename the (un)map_gtt functions to (un)map_map (map by returning a map) and add new functions (un)map_tiled_memcpy that return a shadow buffer populated with the intel_tiled_memcpy functions. Tiling/detiling with the cpu will be the only way to handle Yf/Ys tiling, when support is added for those

[Mesa-dev] [PATCH 4/5] i965/miptree: Map with movntdqa for linear buffers only

Removes a place where gtt mapping is used. Reviewed-by: Nanley Chery --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 58ffe

[Mesa-dev] [PATCH 1/5] i965/tiled_memcpy: ytiled_to_linear a cache line at a time

Similar to the transformation applied to linear_to_ytiled, also align each readback from the ytiled source to a cacheline (i.e. transfer a whole cacheline from the source before moving on to the next column). This will allow us to utilize movntqda (_mm_stream_si128) in a subsequent patch to obtain

Re: [Mesa-dev] [PATCH 5/5] i965/miptree: Don't gtt map from map_depthstencil

Nanley Chery writes: > On Tue, Jan 09, 2018 at 11:17:02PM -0800, Scott D Phillips wrote: >> Instead of gtt mapping, call out to other map functions (map_map >> or map_tiled_memcpy) for the depth surface. Removes a place where >> gtt mapping is used. >> --- >> This is a bit icky, perhaps something

[Mesa-dev] [PATCH v3 104/104] nir: Remove old-school deref chain support

--- src/compiler/nir/nir.c | 269 --- src/compiler/nir/nir.h | 88 - src/compiler/nir/nir_builder.h | 68 --- src/compiler/nir/nir_clone.c| 78 src/compiler/nir/nir_deref.c

[Mesa-dev] [PATCH v3 102/104] nir: Rework lower_locals_to_regs to use deref instructions

This completely reworks the pass to support deref instructions and delete support for old deref chains --- src/compiler/nir/nir_lower_locals_to_regs.c | 186 +--- src/intel/compiler/brw_nir.c| 2 - 2 files changed, 87 insertions(+), 101 deletions(-) diff

[Mesa-dev] [PATCH v3 099/104] nir/copy_prop_vars: Re-order some logic in compare_derefs

--- src/compiler/nir/nir_opt_copy_prop_vars.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/compiler/nir/nir_opt_copy_prop_vars.c b/src/compiler/nir/nir_opt_copy_prop_vars.c index cc8f00f..dca1632 100644 --- a/src/compiler/nir/nir_opt_copy_prop_vars.c ++

[Mesa-dev] [PATCH v3 095/104] nir: Remove deref chain support from dead_variables

--- src/compiler/nir/nir_remove_dead_variables.c | 84 +--- 1 file changed, 1 insertion(+), 83 deletions(-) diff --git a/src/compiler/nir/nir_remove_dead_variables.c b/src/compiler/nir/nir_remove_dead_variables.c index cbeb954..869e080 100644 --- a/src/compiler/nir/nir_re

[Mesa-dev] [PATCH v3 096/104] nir: Remove deref chain support from split_var_copies

--- src/compiler/nir/nir_split_var_copies.c | 214 +--- 1 file changed, 4 insertions(+), 210 deletions(-) diff --git a/src/compiler/nir/nir_split_var_copies.c b/src/compiler/nir/nir_split_var_copies.c index bcd1f10..5ac1c33 100644 --- a/src/compiler/nir/nir_split_var_

[Mesa-dev] [PATCH v3 097/104] nir: Remove deref chain support from opt_undef

--- src/compiler/nir/nir_opt_undef.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/compiler/nir/nir_opt_undef.c b/src/compiler/nir/nir_opt_undef.c index 1439ca9..42524d7 100644 --- a/src/compiler/nir/nir_opt_undef.c +++ b/src/compiler/nir/nir_opt_undef.c @@ -109,7 +109,6 @@ opt_undef_stor

[Mesa-dev] [PATCH v3 103/104] HACK! nir: Disable building a couple passes

--- src/compiler/Makefile.sources | 3 --- src/compiler/nir/meson.build | 6 +++--- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources index 21b1f85..fe328ee 100644 --- a/src/compiler/Makefile.sources +++ b/src/compiler/Mak

[Mesa-dev] [PATCH v3 098/104] nir: Remove deref chain support from split_per_member_structs

--- src/compiler/nir/nir_split_per_member_structs.c | 84 + 1 file changed, 1 insertion(+), 83 deletions(-) diff --git a/src/compiler/nir/nir_split_per_member_structs.c b/src/compiler/nir/nir_split_per_member_structs.c index 98aaaca..1b4c42b 100644 --- a/src/compiler/nir/

[Mesa-dev] [PATCH v3 101/104] intel, ir3: Re-enable nir_opt_copy_prop_vars

Now that it's rewritten for deref instructions, we can turn it back on. --- src/gallium/drivers/freedreno/ir3/ir3_nir.c | 2 +- src/intel/compiler/brw_nir.c| 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c b/src/gall

[Mesa-dev] [PATCH v3 100/104] nir: Rework opt_copy_prop_vars to use deref instructions

--- src/compiler/nir/nir_opt_copy_prop_vars.c | 314 ++ 1 file changed, 145 insertions(+), 169 deletions(-) diff --git a/src/compiler/nir/nir_opt_copy_prop_vars.c b/src/compiler/nir/nir_opt_copy_prop_vars.c index dca1632..f0b5184 100644 --- a/src/compiler/nir/nir_opt_

[Mesa-dev] [PATCH v3 091/104] nir: Remove deref chain support from opt_peephole_select

--- src/compiler/nir/nir_opt_peephole_select.c | 11 --- 1 file changed, 11 deletions(-) diff --git a/src/compiler/nir/nir_opt_peephole_select.c b/src/compiler/nir/nir_opt_peephole_select.c index 608701a..8fa9911 100644 --- a/src/compiler/nir/nir_opt_peephole_select.c +++ b/src/compiler/

[Mesa-dev] [PATCH v3 093/104] nir: Remove deref chain support from lower_var_copies

--- src/compiler/nir/nir_lower_var_copies.c | 138 ++-- 1 file changed, 6 insertions(+), 132 deletions(-) diff --git a/src/compiler/nir/nir_lower_var_copies.c b/src/compiler/nir/nir_lower_var_copies.c index 62bbe50..9326d99 100644 --- a/src/compiler/nir/nir_lower_var_

[Mesa-dev] [PATCH v3 094/104] nir: Remove deref chain support from propagate_invariant

--- src/compiler/nir/nir_propagate_invariant.c | 12 +--- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/src/compiler/nir/nir_propagate_invariant.c b/src/compiler/nir/nir_propagate_invariant.c index b48b91c..a6d32b2 100644 --- a/src/compiler/nir/nir_propagate_invariant.c ++

[Mesa-dev] [PATCH v3 092/104] nir: Remove deref chain support from lower_drawpixels

--- src/compiler/nir/nir_lower_drawpixels.c | 13 - 1 file changed, 13 deletions(-) diff --git a/src/compiler/nir/nir_lower_drawpixels.c b/src/compiler/nir/nir_lower_drawpixels.c index 05131af..f7ff5c0 100644 --- a/src/compiler/nir/nir_lower_drawpixels.c +++ b/src/compiler/nir/nir_lo

[Mesa-dev] [PATCH v3 090/104] nir: Remove deref chain support from lower_tex

--- src/compiler/nir/nir_lower_tex.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c index 449b92f..1ccd253 100644 --- a/src/compiler/nir/nir_lower_tex.c +++ b/src/compiler/nir/nir_lower_tex.c @@ -124,9 +124,7 @@ get_text

[Mesa-dev] [PATCH v3 088/104] nir: Remove deref chain support from lower_wpos_ytransform

--- src/compiler/nir/nir_lower_wpos_ytransform.c | 36 1 file changed, 36 deletions(-) diff --git a/src/compiler/nir/nir_lower_wpos_ytransform.c b/src/compiler/nir/nir_lower_wpos_ytransform.c index 6212702..f6f642c 100644 --- a/src/compiler/nir/nir_lower_wpos_ytransf

[Mesa-dev] [PATCH v3 086/104] nir: Remove deref chain support from lower_system_values

--- src/compiler/nir/nir_lower_system_values.c | 26 +++--- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/src/compiler/nir/nir_lower_system_values.c b/src/compiler/nir/nir_lower_system_values.c index 5191fb3..d2c8456 100644 --- a/src/compiler/nir/nir_lower_sy

[Mesa-dev] [PATCH v3 085/104] nir: Remove deref chain support from remove_unused_varyings

--- src/compiler/nir/nir_linking_helpers.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/compiler/nir/nir_linking_helpers.c b/src/compiler/nir/nir_linking_helpers.c index 1a0cb91..85712a7 100644 --- a/src/compiler/nir/nir_linking_helpers.c +++ b/src/compiler/

[Mesa-dev] [PATCH v3 087/104] nir: Remove deref chain support from lower_wpos_center

--- src/compiler/nir/nir_lower_wpos_center.c | 11 --- 1 file changed, 11 deletions(-) diff --git a/src/compiler/nir/nir_lower_wpos_center.c b/src/compiler/nir/nir_lower_wpos_center.c index 5b68cac..b6f3529 100644 --- a/src/compiler/nir/nir_lower_wpos_center.c +++ b/src/compiler/nir/nir_

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