Re: [Mesa-dev] [PATCH 1/2] i965: Make assign_common_binding_table_offsets return void

This patch is missing to actually change the implementation in brw_shader.cpp to not return a uint32_t result. With that fixed, this patch is: Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2017-02-07 at 15:03 -0800, Jason Ekstrand wrote: > It doesn't really matter w

Re: [Mesa-dev] [PATCH V2 1/2] mesa: use PRId64/PRIu64 when printing 64-bit ints

Both patches are: Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Wed, 2017-02-08 at 12:35 +1100, Timothy Arceri wrote: > V2: actually use PRIu64 > --- >  src/mesa/main/uniform_query.cpp | 4 ++-- >  1 file changed, 2 insertions(+), 2 deletions(-) > > di

Re: [Mesa-dev] [PATCH] anv: Improve flushing around STATE_BASE_ADDRESS

a FIXME indicating this situation so we know we have not verified that this is actually needed. Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> > Reported-by: Mark Janes <mark.a.ja...@intel.com> > Tested-by: Mark Janes <mark.a.ja...@intel.com> > --- >  src/intel

Re: [Mesa-dev] [PATCH v3] i965: Prevent coverity warning

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2017-01-31 at 15:20 -0500, Robert Foss wrote: > Add assert checking that num_sources is never larger than 3. > > This prevents Coverity from concluding that the unhandled > cases of num_sources not being 0-3 are relev

Re: [Mesa-dev] [PATCH] anv/cmd_buffer: Use the proper depth input attachment surface state

utput.46 Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> > Cc: "17.0" <mesa-sta...@lists.freedesktop.org> > Cc: Iago Toral <ito...@igalia.com> > Cc: Jason Ekstrand <ja...@jlekstrand.net> > Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com&

Re: [Mesa-dev] [PATCH] anv: Advertise API version 1.0.39

FWIW, vulkan-cts seems happy. Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Thu, 2017-01-26 at 09:27 -0800, Jason Ekstrand wrote: > I'm pretty sure we've kept up with the bug fixes. > --- >  src/intel/vulkan/anv_device.c | 2 +- >  1 file changed, 1 insertion(+), 1 del

[Mesa-dev] [PATCH] anv/lower_input_attachments: honor sample index parameter to subpassLoad()

According to GL_KHR_vulkan_glsl, the signature of subpassLoad() is: gvec4 subpassLoad(gsubpassInput subpass); gvec4 subpassLoad(gsubpassInputMS subpass, int sample); So the multisampled case always receives an explicit sample index that we should use. The current implementation was ignoring

[Mesa-dev] [PATCH] spirv: handle gl_SampleMask

SPIR-V maps both gl_SampleMask and gl_SampleMaskIn to the same builtin (SampleMask). The only way to tell which one we are dealing with is to check if it is an input or an output. Fixes: dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.write.* --- I am still waiting on Jenkins to report

[Mesa-dev] [PATCH] spirv: acknowledge multisampled input attachments

This avoids tons of crashes in dEQP-VK.pipeline.multisample_shader_builtin.sample_id.* dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.* dEQP-VK.pipeline.multisample_shader_builtin.sample_position.* --- With this patch some of the tests pass, some still fail and some (from the

Re: [Mesa-dev] [PATCH 0/6] anv: Implement VK_KHR_maintenance1

I dropped a couple of minor comments on patches 1 and 3, but otherwise the series is: Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Mon, 2017-01-23 at 14:12 -0800, Jason Ekstrand wrote: > This little series implements the new VK_KHR_maintenance1 > extension.  Most >

Re: [Mesa-dev] [PATCH 3/6] anv: Report FORMAT_FEATURE_TRANSFER_SRC/DST_BIT_KHR

On Mon, 2017-01-23 at 14:12 -0800, Jason Ekstrand wrote: > As of VK_KHR_maintenance1, these are supposed to be reported for any > formats on which we support transfer operations.  For us, this is > anything that we can texture from. > --- >  src/intel/vulkan/anv_formats.c | 9 - >  1 file

Re: [Mesa-dev] [PATCH 1/6] anv: Set viewport extents correctly when height is negative

On Mon, 2017-01-23 at 14:12 -0800, Jason Ekstrand wrote: > As per VK_KHR_maintenance1, setting a negative height in the viewport > can be used to get flipped coordinates.  This is, aparently, very > useful > when porting D3D apps to Vulkan.  All we need to do to support this > is > to make sure we

Re: [Mesa-dev] [PATCH] nir/search: Use the correct bit size for integer comparisons

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Thu, 2017-01-19 at 21:47 -0800, Jason Ekstrand wrote: > The previous code always compared integers as 64-bit.  Due to > variations > in sign-extension in the code generated by nir_opt_algebraic.py, this > meant that nir_sea

Re: [Mesa-dev] [PATCH v3] mesa/main: Fix FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE for NONE attachment type

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Thu, 2017-01-19 at 11:36 -0200, Alejandro Piñeiro wrote: > When the attachment type is NONE (att->Type), > FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE should be NONE always. > > Note that technically, the current behaviour f

Re: [Mesa-dev] [PATCH] nir/algebraic: Only include nir_search_helpers once

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Wed, 2017-01-18 at 15:24 -0800, Jason Ekstrand wrote: > We were including it once per value, so probably around 10k times. > Let's not cause the compiler any more work than we have to. > --- >  src/compiler/nir/nir_algebr

Re: [Mesa-dev] [PATCH v2] mesa/main: Fix FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE for NONE attachment type

On Wed, 2017-01-18 at 16:48 -0200, Alejandro Piñeiro wrote: > When the attachment type is NONE (att->Type), > FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE should be NONE too. > > Note that technically, the current behaviour follows the spec. From > OpenGL 4.5 spec, Section 9.2.3 "Framebuffer Object

Re: [Mesa-dev] [PATCH 1/4] glsl: split DIV_TO_MUL_RCP into single- and double-precision flags

This patch is: Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Mon, 2017-01-16 at 17:20 +0100, Nicolai Hähnle wrote: > From: Nicolai Hähnle <nicolai.haeh...@amd.com> > > --- >  src/compiler/glsl/ir_optimization.h  |  4 +++- >  src/compiler/glsl/

[Mesa-dev] [PATCH] anv: set UAV coherence required bit when needed

The same we do in the OpenGL driver (comment copied from there). This is required to ensure that we execute the fragment shader stage when side-effects (such as image or ssbo stores) are present but there are no color writes. I found this while writing a test to check rendering to a framebuffer

Re: [Mesa-dev] [PATCH] mesa/main: Fix FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE for NONE attachment type

attachment type is NONE. For example, this can happens if the > attachment is FRONT_RIGHT run on monoscopic mode, as that attachment > is only available on stereo mode. Makes sense to me, assuming this is not causing regressions anywhere: Reviewed-by: Iago Toral Quiroga <ito...@igali

Re: [Mesa-dev] [PATCH] nir/i965: assert first is always less than 64

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Thu, 2017-01-12 at 12:24 +0100, Juan A. Suarez Romero wrote: > This fixes a defect detected by Coverity Scan. > --- >  src/mesa/drivers/dri/i965/brw_draw_upload.c | 1 + >  1 file changed, 1 insertion(+) > > diff --gi

Re: [Mesa-dev] [PATCH 01/11] spirv: Handle tessellation execution modes.

Patches 1-5 are: Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Sun, 2017-01-08 at 21:26 -0800, Kenneth Graunke wrote: > Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> > --- >  src/compiler/spirv/spirv_to_nir.c | 28 ++-- >  1 fil

Re: [Mesa-dev] [PATCH 02/11] spirv: Add tessellation varying and built-in support.

On Sun, 2017-01-08 at 21:26 -0800, Kenneth Graunke wrote: > We need to: > - handle the extra array level for per-vertex varyings > - handle the patch qualifier correctly > - assign varying locations > > Signed-off-by: Kenneth Graunke > --- >  

[Mesa-dev] [PATCH] spirv: fix typo in warning message

--- src/compiler/spirv/spirv_to_nir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index befee1a..2205072 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -559,7

[Mesa-dev] [PATCH] spirv: gl_PrimitiveID in the fragment shader is handled as an input

Geometry and Tessellation stages do handle this as a system value instead. Fixes: dEQP-VK.geometry.basic.primitive_id --- src/compiler/spirv/vtn_variables.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/compiler/spirv/vtn_variables.c

Re: [Mesa-dev] [PATCH] isl: render target cube maps should be handled as 2D images, not cubes

ng anything... > > Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> > > On Jan 6, 2017 05:42, "Iago Toral Quiroga" <ito...@igalia.com> wrote: > > This fixes layered rendering Vulkan CTS tests with cube (arrays). > > We > > also do

[Mesa-dev] [PATCH] isl: render target cube maps should be handled as 2D images, not cubes

This fixes layered rendering Vulkan CTS tests with cube (arrays). We also do this in the GL driver, see this code from gen8_depth_state.c for example: case GL_TEXTURE_CUBE_MAP_ARRAY: case GL_TEXTURE_CUBE_MAP: /* The PRM claims that we should use BRW_SURFACE_CUBE for this * situation, but

Re: [Mesa-dev] [PATCH] glsl: fix opt_minmax redundancy checks against baserange

Hi Tim, it's been a while, so off the top of my head I don't have any particular suggestions or the capacity to tell whether your fix is correct or not :-/. I'll try to spend some time re-acquainting myself with that code on Monday and see if I can see what is going on here. Iago On Fri,

Re: [Mesa-dev] [PATCH] anv: don't skip the VUE header if we are reading gl_Layer in a fragment shader

On Thu, 2017-01-05 at 14:08 +0100, Iago Toral Quiroga wrote: > This is the same we do in the GL driver: the hardware provides > gl_Layer > in the VUE header, so when the fragment shader reads it we can't skip > it. Forgot to add that this fixes the following Vulkan CTS

[Mesa-dev] [PATCH] anv: don't skip the VUE header if we are reading gl_Layer in a fragment shader

This is the same we do in the GL driver: the hardware provides gl_Layer in the VUE header, so when the fragment shader reads it we can't skip it. --- With this patch we now successfully read gl_Layer in fragment shaders. Layered rendering still does not work though, probably because we still need

[Mesa-dev] [PATCH] docs: Mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as done for i965/hsw+

--- docs/features.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index 63b45af..f4a67df 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -107,7 +107,7 @@ GL 3.3, GLSL 3.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi,

Re: [Mesa-dev] [PATCH] docs: add GL_ARB_gpu_shader_fp64 and OpenGL 4.0 support for Intel Haswell.

On Thu, 2017-01-05 at 09:59 +0200, Martin Peres wrote: > On 05/01/17 09:56, Iago Toral Quiroga wrote: > > > > --- > >   docs/relnotes/13.1.0.html | 2 ++ > >   1 file changed, 2 insertions(+) > > > > diff --git a/docs/relnotes/13.1.0.html b/docs/relnotes

[Mesa-dev] [PATCH] docs: add GL_ARB_gpu_shader_fp64 and OpenGL 4.0 support for Intel Haswell.

--- docs/relnotes/13.1.0.html | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/relnotes/13.1.0.html b/docs/relnotes/13.1.0.html index 4dce843..124da93 100644 --- a/docs/relnotes/13.1.0.html +++ b/docs/relnotes/13.1.0.html @@ -47,6 +47,8 @@ Note: some of the new features are only

Re: [Mesa-dev] [PATCH v2 4/4] i965: add a kernel_features bitfield to intel screen

On Wed, 2017-01-04 at 15:35 -0800, Kenneth Graunke wrote: > On Wednesday, January 4, 2017 1:26:23 PM PST Iago Toral Quiroga > wrote: > > > > We can use this to track various features that may or may not be > > supported > > by the hw / kernel. Currently,

Re: [Mesa-dev] [PATCH v2 1/4] i965: Move the pipelined test for SO register access to the screen

On Wed, 2017-01-04 at 15:34 -0800, Kenneth Graunke wrote: > On Wednesday, January 4, 2017 1:26:20 PM PST Iago Toral Quiroga > wrote: > > > > From: Chris Wilson <ch...@chris-wilson.co.uk> > [snip] > > > > +   /* And afterwards clear the register */

[Mesa-dev] [PATCH v2 4/4] i965: add a kernel_features bitfield to intel screen

We can use this to track various features that may or may not be supported by the hw / kernel. Currently, we usually do this by checking the generation and supported command parser versions in various places thoughtout the driver code. With this patch, we centralize all these checks in just once

[Mesa-dev] [PATCH v2 3/4] i965/gen7: Enable OpenGL 4.0 in Haswell when supported

--- src/mesa/drivers/dri/i965/intel_extensions.c | 2 ++ src/mesa/drivers/dri/i965/intel_screen.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 8e67b57..aa89380 100644

[Mesa-dev] [PATCH v2 1/4] i965: Move the pipelined test for SO register access to the screen

From: Chris Wilson Moving the test to the screen places it alongside the other global HW feature tests that want to be shared between contexts. Also, we need to know if we support pipelined register writes at screen creation time so that we can tell if we can expose

[Mesa-dev] [PATCH v2 2/4] i965: get rid of brw->can_do_pipelined_register_writes

Instead, check the screen field directly. --- src/mesa/drivers/dri/i965/brw_context.c | 2 -- src/mesa/drivers/dri/i965/brw_context.h | 5 - src/mesa/drivers/dri/i965/gen7_l3_state.c| 5 +++-- src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-

[Mesa-dev] [PATCH v2 0/4] Enable OpenGL 4.0 on Haswell

current were doing this and we save one flag, let me know if you prefer them to be separate flags. Chris Wilson (1): i965: Move the pipelined test for SO register access to the screen Iago Toral Quiroga (3): i965: get rid of brw->can_do_pipelined_register_writes i965/gen7: Enable OpenGL

Re: [Mesa-dev] [PATCH 0/6] Enable OpenGL 4.0 on Haswell

On Tue, 2017-01-03 at 07:48 -0800, Kenneth Graunke wrote: > On Tuesday, January 3, 2017 2:02:19 PM PST Iago Toral wrote: > > > > On Tue, 2017-01-03 at 11:14 +, Chris Wilson wrote: > > > > > > On Tue, Jan 03, 2017 at 11:42:50AM +010

Re: [Mesa-dev] [PATCH 0/6] Enable OpenGL 4.0 on Haswell

On Tue, 2017-01-03 at 11:14 +, Chris Wilson wrote: > On Tue, Jan 03, 2017 at 11:42:50AM +0100, Iago Toral Quiroga wrote: > > > > Enabling GL 4.0 in gen7 requires a bit of work because some > > hardware and kernel > > combinations may not support all the features

[Mesa-dev] [PATCH 2/6] i965: make intel_batchbuffer_emit_dword() take a batchbuffer as argument

--- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 6 +++--- src/mesa/drivers/dri/i965/intel_batchbuffer.h | 18 +- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c

[Mesa-dev] [PATCH 3/6] i965: make intel_batchbuffer_free() take a batchbuffer as argument

--- src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 8 src/mesa/drivers/dri/i965/intel_batchbuffer.h | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c

[Mesa-dev] [PATCH 5/6] i965: check if we support pipelined register writes at screen creation time

We need this feature to enable OpenGL 4.0 on gen7 hardware. Some hardware and kernel combinations support this while other don't, so we check for it by writing to a register and verifying the result. Unfortunately, we need to know this at screen creation time when we don't have a brw_context

[Mesa-dev] [PATCH 0/6] Enable OpenGL 4.0 on Haswell

-October/133502.html Iago Toral Quiroga (6): i965: Make intel_bachbuffer_reloc() take a batchbuffer argument i965: make intel_batchbuffer_emit_dword() take a batchbuffer as argument i965: make intel_batchbuffer_free() take a batchbuffer as argument i965: remove brw_context dependency from

[Mesa-dev] [PATCH 4/6] i965: remove brw_context dependency from intel_batchbuffer_init()

--- src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 59 +++ src/mesa/drivers/dri/i965/intel_batchbuffer.h | 3 +- 3 files changed, 36 insertions(+), 28 deletions(-) diff --git

[Mesa-dev] [PATCH 6/6] i965/gen7: Enable OpenGL 4.0 in Haswell when supported

--- src/mesa/drivers/dri/i965/intel_extensions.c | 2 ++ src/mesa/drivers/dri/i965/intel_screen.c | 11 --- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index

[Mesa-dev] [PATCH 1/6] i965: Make intel_bachbuffer_reloc() take a batchbuffer argument

--- src/mesa/drivers/dri/i965/genX_blorp_exec.c | 4 ++-- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 8 src/mesa/drivers/dri/i965/intel_batchbuffer.h | 18 +- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git

Re: [Mesa-dev] [PATCH] glsl: Update ES 3.2 shader output restrictions.

ructure[i].type- > >is_array() || > - var->type->fields.structure[i].type- > >is_record()) > +   if (type->is_record()) { > +  for (unsigned i = 0; i < type->length; i++) { > + if (type->fields.structure[i].type->is_array()

Re: [Mesa-dev] [PATCH] glsl: Use ir_var_temporary when generating inline functions.

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Mon, 2016-12-19 at 15:29 -0800, Kenneth Graunke wrote: > We were using ir_var_auto for the inlined function parameter > variables, > which is wrong, as it suggests that those are real variables declared > by the prog

[Mesa-dev] [PATCH] nir/lower_tex: fix number of components in replace_gradient_with_lod()

We should make the dest in the textureLod() operation have the same number of components as the destination in the original textureGrad() Fixes regression in ES3-CTS.gtf.GL3Tests.shadow Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99072 --- src/compiler/nir/nir_lower_tex.c | 3 ++- 1

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

On Tue, 2016-12-13 at 13:22 +0100, Samuel Iglesias Gonsálvez wrote: > On Sun, 2016-12-11 at 15:00 -0800, Matt Turner wrote: > > > > i965/vec4: handle 32 and 64 bit channels in liveness analysis > > > > Please indent the returned multiline expressions in > > var_from_reg() like we do

Re: [Mesa-dev] [PATCH v2 2/7] nir/lower_tex: add lowering for texture gradient on cube maps

On Mon, 2016-12-12 at 23:14 -0800, Kenneth Graunke wrote: > On Monday, December 12, 2016 2:11:43 PM PST Iago Toral Quiroga wrote: > > > > This is ported from the Intel lowering pass that we use with GLSL > > IR. > > The NIR pass only handles cube maps, not shadow s

Re: [Mesa-dev] [PATCH v2 2/7] nir/lower_tex: add lowering for texture gradient on cube maps

On Mon, 2016-12-12 at 23:14 -0800, Kenneth Graunke wrote: > On Monday, December 12, 2016 2:11:43 PM PST Iago Toral Quiroga wrote: > > > > This is ported from the Intel lowering pass that we use with GLSL > > IR. > > The NIR pass only handles cube maps, not shadow s

[Mesa-dev] [PATCH v2 5/7] i965/nir: enable lowering of texture gradient for shadow samplers

This gets the lowering on the Vulkan driver too, which is required for hardware that does not have the sample_l_d message (up to IvyBridge). --- src/mesa/drivers/dri/i965/brw_nir.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_nir.c

[Mesa-dev] [PATCH v2 6/7] i965: remove brw_lower_texture_gradients

This has been ported to NIR now so we don'tneed to keep the GLSL IR lowering any more. --- src/mesa/drivers/dri/i965/Makefile.sources | 1 - src/mesa/drivers/dri/i965/brw_context.h| 2 - src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-

[Mesa-dev] [PATCH v2 1/7] nir/lower_tex: generalize get_texture_size()

This was written specifically for RECT samplers. Make it more generic so we can call this from the gradient lowerings too. --- src/compiler/nir/nir_lower_tex.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/compiler/nir/nir_lower_tex.c

[Mesa-dev] [PATCH v2 7/7] nir/lower_tex: lower gradients on shadow cube maps if lower_txd_shadow is set

Even if lower_txd_cube_map isn't. Suggested by Ken to make the flag more consistent with its name. --- src/compiler/nir/nir_lower_tex.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c index

[Mesa-dev] [PATCH v2 4/7] nir/lower_tex: add lowering for texture gradient on shadow samplers

This is ported from the Intel lowering pass that we use with GLSL IR. This takes care of lowering texture gradients on shadow samplers other than cube maps. Intel hardware requires this for gen < 8. v2 (Ken): - Use the helper function to retrieve ddx/ddy - Swizzle away size components we are

[Mesa-dev] [PATCH v2 3/7] i965/nir: enable lowering of texture gradient for cube maps

This gets the lowering on the Vulkan driver too. Fixes Vulkan CTS cube map texture gradient tests in: dEQP-VK.glsl.texture_functions.texturegrad.* --- src/mesa/drivers/dri/i965/brw_nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_nir.c

[Mesa-dev] [PATCH v2 2/7] nir/lower_tex: add lowering for texture gradient on cube maps

This is ported from the Intel lowering pass that we use with GLSL IR. The NIR pass only handles cube maps, not shadow samplers, which are also lowered for gen < 8 on Intel hardware. We will add support for that in a later patch, at which point we should be able to remove the GLSL IR lowering pass.

[Mesa-dev] [PATCH v2 0/7] i965: port texture gradient lowering to NIR

to pass 2 components instead of one for example. Since we are swizzling away undesired components in the current GLSL IR lowering and you gave your Rb without asking for that change I did not look too much into it, but I can spend some more time into it if you think it is worth it. Iago Toral

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

On Mon, 2016-12-05 at 15:21 -0800, Matt Turner wrote: > On 10/11, Iago Toral Quiroga wrote: > > > > It's been some time since > ... anyone has reviewed your patches. Sorry. :( > > I'm going to review from your rebased i965-fp64-gen7-scalar-vec4-rc2 > branch. Th

Re: [Mesa-dev] [PATCH 4/6] nir/lower_tex: add lowering for texture gradient on shadow samplers

On Mon, 2016-12-05 at 20:39 -0800, Kenneth Graunke wrote: > On Thursday, December 1, 2016 8:53:19 AM PST Iago Toral Quiroga > wrote: > > > > This is ported from the Intel lowering pass that we use with GLSL > > IR. > > This takes care of lowering texture gradient

Re: [Mesa-dev] [PATCH 1/6] nir/lower_tex: generalize get_texture_size()

On Mon, 2016-12-05 at 20:38 -0800, Kenneth Graunke wrote: > On Thursday, December 1, 2016 8:53:16 AM PST Iago Toral Quiroga > wrote: > > > > This was written specifically for RECT samplers. Make it more > > generic so > > we can call this from the gradient lowerings

[Mesa-dev] [PATCH] spirv: Builtin Layer is an input for fragment shaders

This change makes it so we emit a load_input intrinsic when Layer is read in a fragment shader. --- Even with this, layered rendering does not seem to work in the Vulkan driver, so there is something else that is broken. We are probably not mapping the Layer input correctly somewhere.

Re: [Mesa-dev] [PATCH v2] nir: Get rid of nir_constant_data

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Thu, 2016-12-01 at 16:07 -0800, Jason Ekstrand wrote: > This has bothered me for about as long as NIR has been around.  Why > do we > have two different unions for constants?  No good reason other than > one of > them

Re: [Mesa-dev] [PATCH] nir: Get rid of nir_constant_data

On Tue, 2016-11-29 at 22:51 -0800, Jason Ekstrand wrote: > This has bothered me for about as long as NIR has been around.  Why > do we > have two different unions for constants?  No good reason other than > one of > them is a direct port from GLSL IR. > --- >  src/compiler/glsl/glsl_to_nir.cpp  |

[Mesa-dev] [PATCH 6/6] i965: remove brw_lower_texture_gradients

This has been ported to NIR now so we don'tneed to keep the GLSL IR lowering any more. --- src/mesa/drivers/dri/i965/Makefile.sources | 1 - src/mesa/drivers/dri/i965/brw_context.h| 2 - src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-

[Mesa-dev] [PATCH 5/6] i965/nir: enable lowering of texture gradient for shadow samplers

This gets the lowering on the Vulkan driver too, which is required for hardware that does not have the sample_l_d message (up to IvyBridge). --- src/mesa/drivers/dri/i965/brw_nir.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_nir.c

[Mesa-dev] [PATCH 4/6] nir/lower_tex: add lowering for texture gradient on shadow samplers

This is ported from the Intel lowering pass that we use with GLSL IR. This takes care of lowering texture gradients on shadow samplers other than cube maps. Intel hardware requires this for gen < 8. --- src/compiler/nir/nir.h | 7 +++ src/compiler/nir/nir_lower_tex.c | 40

[Mesa-dev] [PATCH 0/6] i965: port texture gradient lowering to NIR

of the GLSL IR lowering pass. Iago Toral Quiroga (6): nir/lower_tex: generalize get_texture_size() nir/lower_tex: add lowering for texture gradient on cube maps i965/nir: enable lowering of texture gradient for cube maps nir/lower_tex: add lowering for texture gradient on shadow samplers i965/nir

[Mesa-dev] [PATCH 3/6] i965/nir: enable lowering of texture gradient for cube maps

This gets the lowering on the Vulkan driver too. Fixes Vulkan CTS cube map texture gradient tests in: dEQP-VK.glsl.texture_functions.texturegrad.* --- src/mesa/drivers/dri/i965/brw_nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_nir.c

[Mesa-dev] [PATCH 1/6] nir/lower_tex: generalize get_texture_size()

This was written specifically for RECT samplers. Make it more generic so we can call this from the gradient lowerings too. --- src/compiler/nir/nir_lower_tex.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/compiler/nir/nir_lower_tex.c

Re: [Mesa-dev] [PATCH] anv/state: if enabled, use anisotropic filtering also with VK_FILTER_NEAREST

On Thu, 2016-11-24 at 16:28 -0800, Jason Ekstrand wrote: > > On Nov 24, 2016 7:12 AM, "Iago Toral" <ito...@igalia.com> wrote: > > > > On Thu, 2016-11-24 at 14:33 +0100, Iago Toral wrote: > > > Hi Lionel, > > > > > > On Thu, 2016-11-2

Re: [Mesa-dev] [PATCH] anv/state: if enabled, use anisotropic filtering also with VK_FILTER_NEAREST

On Thu, 2016-11-24 at 14:33 +0100, Iago Toral wrote: > Hi Lionel, > > On Thu, 2016-11-24 at 13:08 +, Lionel Landwerlin wrote: > > > > Hi Iago, > > > > Looking at the history, before > > ed4fe3e9ba9018e68afe6fdd4f267218a537fdaa  > > we seem t

Re: [Mesa-dev] [PATCH] anv/state: if enabled, use anisotropic filtering also with VK_FILTER_NEAREST

at check. Iago > On 24/11/16 11:30, Iago Toral Quiroga wrote: > > > > Fixes multiple Vulkan CTS tests that combine anisotropy and > > VK_FILTER_NEAREST > > in dEQP-VK.texture.filtering_anisotropy.* > > --- > >   src/intel/vulkan/genX_state.c | 2 +- > >

[Mesa-dev] [PATCH] anv/state: if enabled, use anisotropic filtering also with VK_FILTER_NEAREST

Fixes multiple Vulkan CTS tests that combine anisotropy and VK_FILTER_NEAREST in dEQP-VK.texture.filtering_anisotropy.* --- src/intel/vulkan/genX_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index

Re: [Mesa-dev] [PATCH] anv: fix enumeration of properties

Hey Emil, On Thu, 2016-10-06 at 14:12 +0100, Emil Velikov wrote: > From: Emil Velikov > > Driver should enumerate only up-to min2(num_available, num_requested) > properties and return VK_INCOMPLETE if the # of requested props is > smaller than the ones available. >

Re: [Mesa-dev] [PATCH] i965/gen7: Only advertise 4 samples for RGBA32F on GLES

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2016-11-22 at 00:17 -0800, Jordan Justen wrote: > We can't render to 8x MSAA if the width is greater than 64 bits. (see > brw_render_target_supported) > > Fixes ES31-CTS.sample_variables.mask.rgba32f.samples_8.mask

Re: [Mesa-dev] [PATCH v2] nir/spirv: implement ordered / unordered floating point comparisons properly

On Tue, 2016-11-22 at 12:15 +, Lionel Landwerlin wrote: > > > Sounds good to me, thanks! > > Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> >  On 17/11/16 08:36, Iago Toral Quiroga wrote: > > > > Besides the logical operation involved,

Re: [Mesa-dev] [PATCH] util/disk_cache: close a previously opened handle in disk_cache_put

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Sun, 2016-11-20 at 22:59 +0900, Mun Gwan-gyeong wrote: > We're missing the close() to the matching open(). > > CID 1373407 > > Signed-off-by: Mun Gwan-gyeong <elong...@gmail.com> > --- >  src/util/disk_c

Re: [Mesa-dev] [PATCH 06/13] anv/pipeline: Move gather_info further down the compilation process

On Thu, 2016-11-17 at 08:56 -0800, Jason Ekstrand wrote: > On Thu, Nov 17, 2016 at 4:43 AM, Iago Toral <ito...@igalia.com> > wrote: > > Ah, I had missed this, ignore my comment then  :) > > > I just sent out a v2 of patch 7 and force-pushed my review branch if > you

[Mesa-dev] [PATCH] anv/state: enable coordinate address rounding for Min/Mag filters

This patch improves pass rate of dEQP-VK.texture.explicit_lod.2d.sizes.* from 68.0% (98/144) to 83.3% (120/144) by enabling sampler address rounding mode when the selected filter is not nearest, which is the same thing we do for OpenGL. These tests check texture filtering for various texture

Re: [Mesa-dev] [PATCH 06/13] anv/pipeline: Move gather_info further down the compilation process

Ah, I had missed this, ignore my comment then  :) On Wed, 2016-11-16 at 21:18 -0800, Jason Ekstrand wrote: > Forget this patch.  It's bogus.  The computation of prog_data- > >nr_params requires gathered info so the earliest we could put it is > at the top of this function.  Instead, we'll just

Re: [Mesa-dev] [PATCH 06/13] anv/pipeline: Move gather_info further down the compilation process

aces. The attached patch (which applies on top of the series) fixes the regressions. You probably want to merge it in this patch and the next. Iago >     return nir; >  } >  From ec586f02b408da68a26798e66c285cf6370a60e0 Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga <ito...

[Mesa-dev] [PATCH v2] nir/spirv: implement ordered / unordered floating point comparisons properly

Besides the logical operation involved, these also require that we test if the operands are ordered / unordered. For ordered operations, both operands must be ordered (and they must pass the conditional test) while for unordered operations it is sufficient if only one of the operands is unordered

Re: [Mesa-dev] [PATCH] anv: don't try to free VK_NULL_HANDLE objects

Never mind this, I just noticed that Jason has the same patch in his vulkan-cts fixes branch, I am not sure how I missed that. Iago On Wed, 2016-11-16 at 13:34 +0100, Iago Toral Quiroga wrote: > Initial Vulkan documentation stated that it was invalid to free > VK_NULL_HANDLE > objects

[Mesa-dev] [PATCH] anv: don't try to free VK_NULL_HANDLE objects

Initial Vulkan documentation stated that it was invalid to free VK_NULL_HANDLE objects, however this has been changed. From the Vulkan 1.0.33 specification. 2.6.2. Implicit Valid Usage. Valid Usage for Object Handles: "It is valid to pass VK_NULL_HANDLE to any vkDestroy* or vkFree* command,

[Mesa-dev] [PATCH] nir/spirv: implement ordered / unordered floating point comparisons properly

Besides the logical operation involved, these also require that we test if the operands are ordered / unordered. For ordered operations, both operands must be ordered (and they must pass the conditional test) while for unordered operations it is sufficient if only one of the operands is unordered

Re: [Mesa-dev] [PATCH 1/2] anv/format: handle unsupported formats properly

On Mon, 2016-11-14 at 09:29 -0800, Jason Ekstrand wrote: > On Mon, Nov 14, 2016 at 5:23 AM, Iago Toral Quiroga <ito...@igalia.co > m> wrote: > > According to the spec for vkGetPhysicalDeviceImageFormatProperties: > > > > "If format is not a supported

Re: [Mesa-dev] [PATCH 1/2] anv/descriptor_set: Write the state offset in the surface state free list.

>   set->buffer_views[b].surface_state.map; >    entry->next = pool->surface_state_free_list; > +  entry->offset = set->buffer_views[b].surface_state; This will fail to compile, I think you meant: entry->offset = set->buffer_views[b].surface_state.offset;

[Mesa-dev] [PATCH 1/2] anv/format: handle unsupported formats properly

According to the spec for vkGetPhysicalDeviceImageFormatProperties: "If format is not a supported image format, or if the combination of format, type, tiling, usage, and flags is not supported for images, then vkGetPhysicalDeviceImageFormatProperties returns VK_ERROR_FORMAT_NOT_SUPPORTED."

[Mesa-dev] [PATCH 2/2] anv/format: support VK_FORMAT_R8G8B8_SRGB

Fixes dEQP-VK.api.image_clearing.clear_color_image.1d_r8g8b8_srgb --- src/intel/vulkan/anv_formats.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c index bca9aeb..2adde8b 100644 ---

[Mesa-dev] [PATCH] glsl: validate output blocks against input blocks

Until now were validating in/out blocks by listing the inputs in the consumer stage and then, for each output of the producer, we checked that it was a match if it was consumed. This method does not catch the case where the consumer has an input that is not present as an output in the producer

Re: [Mesa-dev] [PATCH] i965/compute: Allow ARB_compute_shader in compat profile

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Thu, 2016-11-03 at 15:31 -0700, Jordan Justen wrote: > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97447 > Cc: Evan Odabashian <eodab...@gmail.com> > Signed-off-by: Jordan Justen <jordan.l.jus...@inte

[Mesa-dev] [PATCH 3/2] i965/vec4: initialize the pull param count 0 every time we run the visitor

This was being initialized just once to 0, but we want to reset it every time we call run() on the visitor, which can happen more than once in scenarios where we failed the compilation using a method and we are falling back to a different configuration. This is possible, for example, with geometry

Re: [Mesa-dev] [PATCH] glsl/cache: correct asprintf error handling

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Thu, 2016-11-03 at 11:03 +0100, Nicolai Hähnle wrote: > From: Nicolai Hähnle <nicolai.haeh...@amd.com> > > From the manpage of asprintf: > >    "If memory allocation wasn't possible, or some other err

Re: [Mesa-dev] [PATCH] i965: use rzalloc instead of calloc in brwNewProgram

Program( struct > > gl_context *ctx, > >  rzalloc(NULL, struct gen4_fragment_program); > >   prog = _prog->base; > >    } else { > > - prog = CALLOC_STRUCT(brw_program); > > + prog = rzalloc(NULL, struct brw_program); > &g

[Mesa-dev] [PATCH 2/2] i965/vec4: fix indentation in lower_attributes_to_hw_regs()

--- src/mesa/drivers/dri/i965/brw_vec4.cpp | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 1fb65f3..03c83af 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++

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