Fixes:
dEQP-GLES31.functional.debug.negative_coverage.log.shader.compile_compute_shader
dEQP-GLES31.functional.debug.negative_coverage.callbacks.shader.compile_compute_shader
dEQP-GLES31.functional.debug.negative_coverage.get_error.shader.compile_compute_shader
Cc: "17.0"
Signed-off-
5b2675093e863a52b610f112884ae12d42513770
The original patch was correct for GLES that should produce
a compile-time error but the linker error is still necessary in
desktop GL.
Signed-off-by: Jose Maria Casanova Crespo
---
src/compiler/glsl/link_uniform_blocks.cpp | 8 +++-
1 file changed, 7
diate
with the rounding mode (Curro)
v3: Reset optimization for every block. (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro
---
src/intel/compiler/brw_eu_defines.h | 3 ++-
src/intel/compiler/brw_fs.cpp
Jose Maria Casanova Crespo (24):
nir: Add rounding modes enum
nir: Handle fp16 rounding modes at nir_type_conversion_op
spirv: Enable FPRoundingMode decorator to nir operations
i965: Support for 16-bit base types in helper functions
i965: Add support for control register
i965/fs: Add
From: Eduardo Lima Mitev
v2: Renamed glsl_half_float_type() to glsl_float16_t_type().
(Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
Reviewed-by: Jason Ekstrand
---
src/compiler/nir/nir.c | 6 ++
src/compiler/nir/nir.h
From: Eduardo Lima Mitev
This will include the following NIR ALU opcodes:
* nir_op_i2i16
* nir_op_i2f16
* nir_op_u2u16
* nir_op_u2f16
* nir_op_f2i16
* nir_op_f2u16
* nir_op_f2f16
v2: Remove "from" 16-bit in commit subject (Topi Pohjolainen)
Reviewed-by: Jason Ekstrand
---
src/compiler/
nir_type_conversion enables new operations to handle rounding modes to
convert to fp16 values. Two new opcodes are enabled nir_op_f2f16_rtne
and nir_op_f2f16_rtz.
The undefined behaviour doesn't has any effect and uses the original
nir_op_f2f16 operation.
v2: Indentation fixed (Jason Ekstrand)
v
From: Eduardo Lima Mitev
This is basically to avoid "not handle in switch" warnings.
v2: Let the new types hit the assertion instead. (Marek Olšák
and Jason Ekstrand)
Reviewed-by: Marek Olšák
Reviewed-by: Nicolai Hähnle
Reviewed-by: Jason Ekstrand
---
src/mesa/state_tracker/st_glsl_type
v2: Added comments describing each of the rounding modes. (Jason
Ekstrand)
Reviewed-by: Jason Ekstrand
---
src/compiler/nir/nir.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index d50e81b46d..883f371d1f 100644
--- a/src/comp
ement.
(Jason Ekstrand)
v3: Use GL_FLOAT16_NV instead of GL_HALF_FLOAT for consistency
(Ilia Mirkin)
v4: Add missing 16-bit base types support in glsl_to_nir (Eduardo Lima).
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
Signed-off-by: Alejandro Piñeiro
Review
From: Alejandro Piñeiro
These types have similar vec4 sizes as their 32-bit counterparts.
The vec4 backend doesn't support 16-bit types and probably never will,
but this method is called by the scalar backend at
fs_visitor::nir_setup_outputs(), so we still need to provide valid vec4
sizes for 16
Control register cr0 in i965 can be used to change the rounding modes
in 32-bit to 16-bit floating-point conversions.
From intel Skylake PRM, vol 07, section "Register and Tegister Regions",
subsection "Control Register" (page 754):
"Subregister cr0.0:ud contains normal operation control fields
.
- Assert align1 for scattered messages and assume Gen8+.
- Inline brw_set_dp_byte_scattered_write.
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro
---
src/intel/compiler/brw_eu.h| 7 +
src/intel/compiler/brw_eu_defines.h| 17
From: Alejandro Piñeiro
Note that we don't remove the assert at i965/vec4. At this point half
float support is only for the scalar backend.
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_ir_fs.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/intel/compiler/brw_ir_fs.h b/src/
code style.
Signed-off-by: Alejandro Piñeiro
Signed-off-by: Jose Maria Casanova Crespo
Reviewed-by: Francisco Jerez
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_eu.h | 4
src/intel/compiler/brw_eu_defines.h | 16
src/intel/compiler/brw_e
ir_op (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs_nir.cpp | 18 ++
1 file changed, 18 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/com
v2: Fixed calculation of scalar size for 16-bit types. (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_fs.cpp | 4
src/intel/compiler/brw_nir.c | 16
src/intel
From: Eduardo Lima Mitev
v2: Minor changes after rebase against recent master (Alejandro
Pinheiro)
Reviewed-by: Jason Ekstrand
---
src/compiler/spirv/nir_spirv.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/src/compiler/spirv/nir_s
From: Eduardo Lima Mitev
v2: Added more missing implementations of 16-bit types. (Jason Ekstrand)
v3: Store values in values[0].u16[i] (Jason Ekstrand)
Include switches based on bitsize for 16-bit types
(Chema Casanova)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo
types.
v3 (Topi Pohjolainen)
- Code style fix
(Jason Ekstrand)
- Now nir_op_f2f16 was renamed to nir_op_f2f16_undef
because conversion to f16 with undefined rounding is explicit
Signed-off-by: Eduardo Lima
Signed-off-by: Alejandro Piñeiro
Signed-off-by: Jose Maria Casanova Crespo
SpvOpFConvert now manages the FPRoundingMode decorator for the
returning values enabling the nir_rounding_mode in the conversion
operation to fp16 values.
v2: Fixed breaking of specialization constants. (Jason Ekstrand)
v3: Avoid nir_rounding_mode * casting. (Jason Ekstrand)
Reviewed-by: Jason E
diate
with the rounding mode (Curro)
v3: Reset optimization for every block. (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_eu_defines.h | 1 +
src/intel/compiler/brw_fs.cpp
/type_slots on store_ssbo.
(Jose Maria Casanova)
- Take into account that get_nir_src returns now WORD types for
16-bit sources instead of DWORD.
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro
---
src/intel/compiler/brw_fs_nir.cpp | 51
v2: Fix alignment style (Topi Pohjolainen)
(Jason Ekstrand)
- Enable bit_size parameter to scattered messages to enable different
bitsizes byte/word/dword.
- Remove use of brw_send_indirect_scattered_message in favor of
brw_send_indirect_surface_message.
- Move scattered
Used to enable 16-bit reads at do_untyped_vector_read, that is used on
the following intrinsics:
* nir_intrinsic_load_shared
* nir_intrinsic_load_ssbo
v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand)
v3: - Add bitsize to scattered read operation (Jason Ekstrand)
- Remov
From: Eduardo Lima Mitev
v2: minor changes after rebase against recent master (Alejandro)
---
src/intel/vulkan/anv_pipeline.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 907b24a758..c58bd2f9a1 100644
--- a/src/intel/
load_ubo is using 32-bit loads as uniforms surfaces have a 32-bit
surface format defined. So when reading 16-bit components with the
sampler we need to unshuffle two 16-bit components from each 32-bit
component.
Using the sampler avoids the use of the byte_scattered_read message
that needs one mes
This helpers are used to load/store 16-bit types from/to 32-bit
components.
The functions shuffle_32bit_load_result_to_16bit_data and
shuffle_16bit_data_for_32bit_write are implemented in a similar
way than the analogous functions for handling 64-bit types.
---
src/intel/compiler/brw_fs.h |
storageBuffer16BitAccess and uniformAndStorageBuffer16BitAccess.
- Only expose VK_KHR_16bit_storage on Gen8+
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro
---
src/intel/vulkan/anv_device.c | 13 +
src/intel/vulkan/anv_extensions.py | 1 +
2 files changed, 14
issues with writemask yz with 16-bit writes. (Jason Ektrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
---
src/intel/compiler/brw_fs_nir.cpp | 61 +--
1 file changed, 46 insertions(+), 15 deletions(-)
diff --git a/src/intel/compiler
New shader attribute to mark when a location has 16-bit
value. This patch includes support on mesa glsl and nir.
v2: Remove use of is_half_slot as is a duplicate of is_16bit
(Topi Pohjolainen)
Renamed half_inputs_read to inputs_read_16bit (Jason Ekstrand)
---
src/compiler/glsl_types.h
Enables the support of 16-bit types on load_input and
store_outputs intrinsics intra-stages.
The approach was based on re-using the 32-bit URB read
and writes between stages, shuffling pairs of 16-bit values into
32-bit values at load_store intrinsic and un-shuffling the values
at load_inputs.
v2
(example: use *R32* for *R16G16*).
v2: Always use UINT surface format variants. (Topi Pohjolainen)
Renamed half_inputs_read to inputs_read_16bit (Jason Ekstrand)
Reword commit log (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro
---
src/intel
From: Alejandro Piñeiro
While on Untyped Surface messages the bits of the execution mask are
ANDed with the corresponding bits of the Pixel/Sample Mask, that is
not the case for byte scattered writes. That is needed to avoid ssbo
stores writing on helper invocations. So when that can affect, we l
ld be packed (Jason Ekstrand)
Remove not necessary alignment operation for 16-bit to
32-bit conversion (Chema Casanova)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
---
src/intel/compiler/brw_fs_nir.cpp | 48 +++
1 file cha
half_inputs_read to inputs_read_16bit.
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro
---
src/intel/vulkan/anv_device.c | 10 ++
src/intel/vulkan/genX_cmd_buffer.c | 20 ++--
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a
SSBO loads were using byte_scattered read messages as they allow
reading 16-bit size components. byte_scattered messages can only
operate one component at a time so we needed to emit as many messages
as components.
But for vec2 and vec4 of 16-bit, being multiple of 32-bit we can use the
untyped_su
example: on
brw_inst.h).
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
Signed-off-by: Alejandro Piñeiro
---
src/intel/compiler/brw_eu.h | 6 --
src/intel/compiler/brw_eu_emit.c | 25 -
src/intel/compiler/brw_fs.c
Enables storageInputOutput16 feature of VK_KHR_16bit_storage
for Gen8+.
---
src/intel/vulkan/anv_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 2e5b914480..26c0ace1ca 100644
--- a/src/intel/vulkan/anv
The VS load input for 16-bit values receives pairs of 16-bit values
packed in 32-bit values. Because of the adjusted format used at:
anv/pipeline: Use 32-bit surface formats for 16-bit formats
v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand)
v3: Fix coding style and typo (Topi Po
Includes the info about 16-bit vertex inputs coming from nir on brw VS
prog data, as we already do with 64-bit vertex input.
v2: Renamed half_inputs_read to inputs_read_16bit (Jason Ekstrand)
---
src/intel/compiler/brw_compiler.h | 1 +
src/intel/compiler/brw_vec4.cpp | 1 +
2 files changed, 2
Render Target Message's payloads for 16bit values fit in only one
register.
From Intel PRM vol07, page 249 "Render Target Messages" / "Message
Data Payloads"
"The half precision Render Target Write messages have data payloads
that can pack a full SIMD16 payload into 1 register instead of
---
src/intel/compiler/brw_disasm.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 1a94ed3954..c752e15331 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1676,6 +1676,10 @@ brw_d
We enable the use of 16-bit values in push constants
modifying the assign_constant_locations function to work
with 16-bit types.
The API to access buffers in Vulkan use multiples of 4-byte for
offsets and sizes. Current accountability of uniforms based on 4-byte
slots will work for 16-bit values i
Maria Casanova Crespo
Signed-off-by: Eduardo Lima
---
src/intel/compiler/brw_fs_nir.cpp | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index fb138de76a..04d1e3bbf7 100644
--- a/src
Enables storagePushConstant16 feature of VK_KHR_16bit_storage
for Gen8+.
---
src/intel/vulkan/anv_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 26c0ace1ca..5b6032d794 100644
--- a/src/intel/vulkan/an
messages do not support UNIT
formats." where UNIT is a typo for UINT.
v2: Removed use of stride = 2 on sources (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
---
src/intel/compiler/brw_fs_nir.cpp | 46 +++
1 file ch
From: Alejandro Piñeiro
---
src/intel/compiler/brw_fs_visitor.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/intel/compiler/brw_fs_visitor.cpp
b/src/intel/compiler/brw_fs_visitor.cpp
index 481d9c51e7..01e75ff7fc 100644
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/int
SSBO loads were using byte_scattered read messages as they allow
reading 16-bit size components. byte_scattered messages can only
operate one component at a time so we needed to emit as many messages
as components.
But for vec2 and vec4 of 16-bit, being multiple of 32-bit we can use the
untyped_su
message
that needs one message for each component and is supposed to be
slower.
v2: (Jason Ekstrand)
- Simplify component selection and unshuffling for different bitsizes
- Remove SKL optimization of reading only two 32-bit components when
reading 16-bits types.
Reviewed-by: Jose Maria
it_storage
i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit reg
anv: Enable SPV_KHR_16bit_storage on gen 8+
Jose Maria Casanova Crespo (21):
nir: Add rounding modes enum
nir: Handle fp16 rounding modes at nir_type_conversion_op
spirv: Enable FPRoundingMode decorator to nir
ement.
(Jason Ekstrand)
v3: Use GL_FLOAT16_NV instead of GL_HALF_FLOAT for consistency
(Ilia Mirkin)
v4: Add missing 16-bit base types support in glsl_to_nir (Eduardo Lima).
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
Signed-off-by: Alejandro Piñeiro
Review
From: Eduardo Lima Mitev
v2: Renamed glsl_half_float_type() to glsl_float16_t_type().
(Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
---
src/compiler/nir/nir.c | 6 ++
src/compiler/nir/nir.h | 9
nir_type_conversion enables new operations to handle rounding modes to
convert to fp16 values. Two new opcodes are enabled nir_op_f2f16_rtne
and nir_op_f2f16_rtz.
The undefined behaviour doesn't has any effect and uses the original
nir_op_f2f16 operation.
v2: Indentation fixed (Jason Ekstrand)
--
From: Eduardo Lima Mitev
v2: Minor changes after rebase against recent master (Alejandro
Pinheiro)
---
src/compiler/spirv/nir_spirv.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/ni
From: Eduardo Lima Mitev
This is basically to avoid "not handle in switch" warnings.
v2: Let the new types hit the assertion instead. (Marek Olšák
and Jason Ekstrand)
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_glsl_types.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Alejandro Piñeiro
These types have similar vec4 sizes as their 32-bit counterparts.
The vec4 backend doesn't support 16-bit types and probably never will,
but this method is called by the scalar backend at
fs_visitor::nir_setup_outputs(), so we still need to provide valid vec4
sizes for 16
v2: Added comments describing each of the rounding modes. (Jason
Ekstrand)
---
src/compiler/nir/nir.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 3ab2f7dff1..fb269fcb28 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compi
SpvOpFConvert now manages the FPRoundingMode decorator for the
returning values enabling the nir_rounding_mode in the conversion
operation to fp16 values.
v2: Fixed breaking of specialization constants. (Jason Ekstrand)
---
src/compiler/spirv/vtn_alu.c | 32
1 fil
From: Eduardo Lima Mitev
This will include the following NIR ALU opcodes:
* nir_op_i2i16
* nir_op_i2f16
* nir_op_u2u16
* nir_op_u2f16
* nir_op_f2i16
* nir_op_f2u16
* nir_op_f2f16
Reviewed-by: Jason Ekstrand
---
src/compiler/nir/nir_opcodes_c.py | 2 +-
1 file changed, 1 insertion(+), 1
From: Eduardo Lima Mitev
v2: Added more missing implementations of 16-bit types. (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
---
src/compiler/spirv/spirv_to_nir.c | 46 --
src/compiler/spirv/vtn_variables.c | 21
BRW_REGISTER_TYPE_F
v2 (Jason Ekstrand):
- Use better unreachable() messages
- Add Q types
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro
---
src/intel/compiler/brw_fs_nir.cpp | 69 ---
1 file changed, 64 insertions(+), 5 deletions(-)
diff
From: Alejandro Piñeiro
Note that we don't remove the assert at i965/vec4. At this point half
float support is only for the scalar backend.
---
src/intel/compiler/brw_ir_fs.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
ind
From: Alejandro Piñeiro
By default we don't set the rounding mode. We only set
round-to-near-even or round-to-zero mode if explicitly set from nir.
v2: Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
with the rounding mode (Curro)
Signed-off-by: Jose Maria Casanova C
Control register cr0 in i965 can be used to change the rounding modes
in 32-bit to 16-bit floating-point conversions.
From intel Skylake PRM, vol 07, section "Register and Tegister Regions",
subsection "Control Register" (page 754):
"Subregister cr0.0:ud contains normal operation control fields
types.
Signed-off-by: Eduardo Lima
Signed-off-by: Alejandro Piñeiro
Signed-off-by: Jose Maria Casanova Crespo
---
src/intel/compiler/brw_fs_nir.cpp | 25 +
1 file changed, 25 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler
v2: Fixed calculation of scalar size for 16-bit types. (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
---
src/intel/compiler/brw_fs.cpp | 4
src/intel/compiler/brw_nir.c | 16
src/intel/compiler/brw_shader.cpp | 6
diate
with the rounding mode (Curro)
v3: Reset optimization for every block. (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro
Reviewed-by: Jason Ekstrand
---
src/intel/compiler/brw_eu_defines.h | 1 +
src/intel/compiler/brw_fs.cpp
: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro 4)
+ if (type_size > 4) {
length = MIN2(2, length);
+ } else if (type_size == 2) {
+/* For 16-bit types we are us
From: Alejandro Piñeiro
---
src/intel/compiler/brw_fs_nir.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index b356836e80..e108b5517b 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/int
We enable the use of 16-bit values in push constants
modifying the assign_constant_locations function to work
with 16-bit types.
The API to access buffers in Vulkan use multiples of 4-byte for
offsets and sizes. Current accountability of uniforms based on 4-byte
slots will work for 16-bit values i
ñeiro
Signed-off-by: Jose Maria Casanova Crespo
Reviewed-by: Francisco Jerez
---
src/intel/compiler/brw_eu.h | 4
src/intel/compiler/brw_eu_defines.h | 16
src/intel/compiler/brw_eu_emit.c| 33 +
src/intel/compiler/brw_f
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro
---
src/intel/compiler/brw_eu.h| 6 ++
src/intel/compiler/brw_eu_defines.h| 17 +
src/intel/compiler/brw_eu_emit.c | 89 ++
src/intel/compiler
New shader attribute to mark when a location has 16-bit
value. This patch includes support on mesa glsl and nir.
---
src/compiler/glsl_types.h | 24
src/compiler/nir/nir_gather_info.c | 23 ---
src/compiler/nir_types.cpp | 6 ++
sr
location at the shader, we
use 32-bit formats to avoid the conversion, and will fix getting the
proper content later. Note that as we are using 32-bit formats, we can
use formats with less components (example: use *R32* for *R16G16*).
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by
Includes the info about 16-bit vertex inputs coming from nir on brw VS
prog data, as we already do with 64-bit vertex input.
---
src/intel/compiler/brw_compiler.h | 1 +
src/intel/compiler/brw_vec4.cpp | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/compiler/brw_compiler.h
b/src
Added on do_untyped_vector_read, that is used on the following
intrinsics:
* nir_intrinsic_load_shared
* nir_intrinsic_load_ubo
* nir_intrinsic_load_ssbo
v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand)
---
src/intel/compiler/brw_fs_nir.cpp | 24
---
src/intel/compiler/brw_eu.h| 7 +
src/intel/compiler/brw_eu_defines.h| 2 ++
src/intel/compiler/brw_eu_emit.c | 41 ++
src/intel/compiler/brw_fs.cpp | 10 +++
src/intel/compiler/brw_fs_copy_propaga
The VS load input for 16-bit values receives pairs of 16-bit values
packed in 32-bit values. Because of the adjusted format used at:
anv/pipeline: Use 32-bit surface formats for 16-bit formats
v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand)
---
src/intel/compiler/brw_fs_nir.cpp
From: Alejandro Piñeiro
As we are using 32-bit surface formats with 16-bit elements we can be
on a situation where a vertex element can poke over the buffer by 2
bytes. To avoid that we add a padding when flushing the state.
This is similar to what the i965 drivers prior to Haswell do, as they
u
---
src/intel/compiler/brw_disasm.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 2043d64b27..5708284bb9 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1439,6 +1439,10 @@ brw_d
Maria Casanova Crespo
Signed-off-by: Eduardo Lima
---
src/intel/compiler/brw_fs_nir.cpp | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index a48cf40eae..3dbdcc0955 100644
--- a/src
Render Target Message's payloads for 16bit values fit in only one
register.
From Intel PRM vol07, page 249 "Render Target Messages" / "Message
Data Payloads"
"The half precision Render Target Write messages have data payloads
that can pack a full SIMD16 payload into 1 register instead of
From: Alejandro Piñeiro
---
src/intel/compiler/brw_fs_visitor.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/intel/compiler/brw_fs_visitor.cpp
b/src/intel/compiler/brw_fs_visitor.cpp
index 758c8bf44a..e39bafdb42 100644
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/int
example: on
brw_inst.h).
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
Signed-off-by: Alejandro Piñeiro
---
src/intel/compiler/brw_eu.h | 6 --
src/intel/compiler/brw_eu_emit.c | 25 -
src/intel/compiler/brw_fs.c
ld be packed (Jason Ekstrand)
Remove not necessary alignment operation for 16-bit to
32-bit conversion (Chema Casanova)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
---
src/intel/compiler/brw_fs_nir.cpp | 48 +++
1 file cha
messages do not support UNIT
formats." where UNIT is a typo for UINT.
v2: Removed use of stride = 2 on sources (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
---
src/intel/compiler/brw_fs_nir.cpp | 46 +++
1 file ch
Enables the support of 16-bit types on load_input and
store_outputs intrinsics intra-stages.
The approach was based on re-using the 32-bit URB read
and writes between stages, shuffling pairs of 16-bit values into
32-bit values at load_store intrinsic and un-shuffling the values
at load_inputs.
sh
an expensive
operation.
v2: Removed use of stride = 2 on sources (Jason Ekstrand)
Rework optimization using shuffle 16 write and enable writes
of 16bit vec4 with only one message of 32-bits. (Chema Casanova)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Eduardo Lima
---
src
From: Alejandro Piñeiro
It uses VK_KHR_get_physical_device_properties2 functionality to expose
if the extension is supported or not.
v2: update due rebase against master (Alejandro)
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by: Alejandro Piñeiro storageBuffer16BitAccess = pdevice
load_ubo is using 32-bit loads as uniforms surfaces have a 32-bit
surface format defined. So when reading 16-bit components with the
sampler we need to unshuffle two 16-bit components from each 32-bit
component.
Using the sampler avoids the use of the byte_scattered_read message
that needs one mes
From: Alejandro Piñeiro
While on Untyped Surface messages the bits of the execution mask are
ANDed with the corresponding bits of the Pixel/Sample Mask, that is
not the case for byte scattered writes. That is needed to avoid ssbo
stores writing on helper invocations. So when that can affect, we l
From: Eduardo Lima Mitev
v2: minor changes after rebase against recent master (Alejandro)
---
src/intel/vulkan/anv_pipeline.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index b35bad1050..82ed4ecc1d 100644
--- a/src/intel/
SSBO loads were using byte_scattered read messages as they allow
reading 16-bit size components. byte_scattered messages can only
operate one component at a time so we needed to emit as many messages
as components.
But for vec2 and vec4 of 16-bit, being multiple of 32-bit we can use the
untyped_su
New shader attribute to mark when a location has 16-bit
value. This patch includes support on mesa glsl and nir.
v2: Remove use of is_half_slot as is a duplicate of is_16bit
(Topi Pohjolainen)
---
src/compiler/glsl_types.h | 15 +++
src/compiler/nir/nir_gather_info.c | 21
location at the shader, we
use 32-bit formats to avoid the conversion, and will fix getting the
proper content later. Note that as we are using 32-bit formats, we
can use formats with less components (example: use *R32* for *R16G16*).
Signed-off-by: Jose Maria Casanova Crespo
Signed-off-by
These new methods return for a instruction register source/destination
the read/write byte pattern of the 32-byte GRF as an unsigned int.
The returned pattern takes into account the exec_size of the instruction,
the type bitsize, the register stride and a relative offset inside the
register.
The
We use the information of the registers read/write patterns
to improve variable liveness analysis avoiding extending the
liveness range of a variable to the beginning of the block so
it always reaches the beginning of the shader.
This optimization analyses inside each block if a partial write
defi
These new methods return for a instruction register source/destination
the read/write byte pattern of the 32-byte GRF as an unsigned int.
The returned pattern takes into account the exec_size of the instruction,
the type bitsize, the register stride and a relative offset inside the
register.
The
We used the byte_scattered_read message because it allows to read from
non aligned 32-bit offsets. We were reading one component for each
message.
Using a 32-bit bitsize read at byte_scattered_read we can read up to two
16-bit components or four 8-bit components with only one message per
iteration
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