[Mesa-dev] [PATCH v2 24/29] i965/fs: set rounding mode when emitting affected conversion instructions

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index d9376e92220..be197b5f745 100644 --- a/src/intel

[Mesa-dev] [PATCH v2 29/29] anv: enable VK_KHR_shader_float_controls extension

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_extensions.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py index e481c45d5d5..2e29e941bfa 100644 --- a/src/intel/vulkan/anv_extensions.py +++ b/src

[Mesa-dev] [PATCH v2 25/29] i965/fs: remove brw_rounding_mode() and use brw_float_controls_mode() instead

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_eu.h | 4 --- src/intel/compiler/brw_eu_emit.c| 36 - src/intel/compiler/brw_fs_generator.cpp | 13 +++-- 3 files changed, 11 insertions(+), 42 deletions(-) diff --git a/src

[Mesa-dev] [PATCH v2 23/29] i965/fs: emit shader float controls execution modes as first instruction of shaders

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 12971eeb549..0ccff00dd4c 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel

[Mesa-dev] [PATCH v2 16/29] nir: fix denorm flush-to-zero in sqrt's lowering at nir_lower_double_ops

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_lower_double_ops.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_lower_double_ops.c b/src/compiler/nir/nir_lower_double_ops.c index b3543bc6963..c27e2d384a5 100644 --- a/src

[Mesa-dev] [PATCH v2 15/29] nir: fix denorms in unpack_half_1x16()

serve execution mode." v2: - Add nir_op_unpack_half_2x16_flush_to_zero opcode (Connor) Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_constant_expressions.py | 13 + src/compiler/nir/nir_lower_alu_to_scalar.c | 11 +-- src/compiler/nir/nir_

[Mesa-dev] [PATCH v2 17/29] nir: fix fmin/fmax support for doubles

Until now, it was using the floating point version of fmin, instead of the double version. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_opcodes.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir

[Mesa-dev] [PATCH v2 02/29] spirv: check support for SPV_KHR_shader_float_controls capabilities

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/shader_info.h| 1 + src/compiler/spirv/spirv_to_nir.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index b4bc95912a5..53a89a38244 100644 --- a/src/compiler

[Mesa-dev] [PATCH v2 07/29] spirv/glsl450: fix reflect(denorm, denorm) FTZ = 0.0 case

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 82cc7dc909c..c40594290a3 100644 --- a/src/compiler/spirv

[Mesa-dev] [PATCH v2 14/29] nir: fix constant expressions for rounding mode conversions

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_constant_expressions.py | 46 +--- 1 file changed, 41 insertions(+), 5 deletions(-) diff --git a/src/compiler/nir/nir_constant_expressions.py b/src/compiler/nir/nir_constant_expressions.py index dc2132df0d0

[Mesa-dev] [PATCH v2 12/29] nir: add new rounding mode conversions

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir.h| 2 + src/compiler/nir/nir_opcodes.py | 87 --- src/compiler/nir/nir_opcodes_c.py | 4 +- 3 files changed, 50 insertions(+), 43 deletions(-) diff --git a/src/compiler/nir/nir.h b/src

[Mesa-dev] [PATCH v2 01/29] spirv: Update SPIR-V json and headers to Khronos master

This corresponds to commit 17da9f8231f78cf519b4958c2229463a63ead9e2 on GitHub. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/spirv.core.grammar.json | 316 +++-- src/compiler/spirv/spirv.h | 84 +++--- 2 files changed, 281 insertions(+), 119

[Mesa-dev] [PATCH v2 03/29] spirv/nir: keep track of SPV_KHR_shader_float_controls execution modes

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/shader_enums.h | 14 ++ src/compiler/shader_info.h| 3 +++ src/compiler/spirv/spirv_to_nir.c | 26 ++ 3 files changed, 43 insertions(+) diff --git a/src/compiler/shader_enums.h b/src

[Mesa-dev] [PATCH v2 05/29] spirv/glsl450: fix atan2(0, 0) lowering

We were returning 3*pi/4 when we should return 0.0 according to IEEE 754. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c

[Mesa-dev] [PATCH v2 11/29] util: add fp64 -> fp32 conversion support for RTNE and RTZ rounding modes

Signed-off-by: Samuel Iglesias Gonsálvez --- src/util/Makefile.sources | 2 + src/util/double.c | 197 ++ src/util/double.h | 46 + src/util/meson.build | 2 + 4 files changed, 247 insertions(+) create mode 100644 src/util

[Mesa-dev] [PATCH v2 09/29] nir: create new conversion opcodes with floating point rounding modes

It adds round-towards-zero and round-to-nearest-even opcodes for floating point conversions. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_opcodes.py | 2 +- src/compiler/nir/nir_opcodes_c.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src

[Mesa-dev] [PATCH v2 04/29] nir: add support for flushing to zero denorm constants

xcept when the opcode is OpQuantizeToF16." Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_constant_expressions.h | 3 +- src/compiler/nir/nir_constant_expressions.py | 65 ++-- src/compiler/nir/nir_loop_analyze.c | 7 ++- src/co

[Mesa-dev] [PATCH v2 10/29] util: added float to float16 conversions with RTZ and RTNE

Signed-off-by: Samuel Iglesias Gonsálvez --- src/util/half_float.c | 74 +++ src/util/half_float.h | 7 2 files changed, 81 insertions(+) diff --git a/src/util/half_float.c b/src/util/half_float.c index 63aec5c5c14..5fdcb20045b 100644 --- a/src/util

[Mesa-dev] [PATCH v2 06/29] spirv/glsl450: fix atan2(x, x) case

If x < 0 -> atan2(x, x) = -3*pi/4. If x > 0 -> atan2(x, x) = pi/4. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_gls

[Mesa-dev] [PATCH v2 08/29] nir/algebraic: disable inexact optimizations if SHADER_SIGNED_ZERO_INF_NAN_PRESERVE is enabled

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_algebraic.py | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/compiler/nir/nir_algebraic.py b/src/compiler/nir/nir_algebraic.py index a667c4170f1..9d2b248a1c1 100644 --- a/src/compiler/nir

[Mesa-dev] [PATCH v2 13/29] spirv/nir: take into account the rounding mode in the conversions

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir.h | 15 +++ src/compiler/spirv/vtn_alu.c | 16 +++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 05c87290858..9579b5939fe 100644

Re: [Mesa-dev] [PATCH 1/2] vulkan: Update the XML and headers to 1.1.96

Patch series is, Reviewed-by: Samuel Iglesias Gonsálvez Sam On 17/12/2018 16:39, Jason Ekstrand wrote: > --- > include/vulkan/vulkan_core.h | 16 > src/vulkan/registry/vk.xml | 22 +++--- > 2 files changed, 19 insertions(+), 19 deletions(-) >

Re: [Mesa-dev] [PATCH 14/28] nir: fix denorms in unpack_half_1x16()

On 05/12/2018 19:31, Connor Abbott wrote: > On Wed, Dec 5, 2018 at 4:56 PM Samuel Iglesias Gonsálvez > wrote: >> >> According to VK_KHR_shader_float_controls: >> >> "Denormalized values obtained via unpacking an integer into a vector >> of values with

Re: [Mesa-dev] [PATCH 13/28] nir: take into account rounding modes in conversions

On 05/12/2018 19:21, Connor Abbott wrote: > On Wed, Dec 5, 2018 at 4:56 PM Samuel Iglesias Gonsálvez > wrote: >> >> Signed-off-by: Samuel Iglesias Gonsálvez >> --- >> src/compiler/nir/nir.h | 15 +++ >> src/compiler/

Re: [Mesa-dev] [PATCH 12/28] util: add fp64 -> fp32 conversion support for RTNE and RTZ rounding modes

On 07/12/2018 03:03, Matt Turner wrote: > On Wed, Dec 5, 2018 at 7:56 AM Samuel Iglesias Gonsálvez > wrote: >> >> Signed-off-by: Samuel Iglesias Gonsálvez >> --- >> src/util/Makefile.sources | 2 + >> src/util/double.c | 197

Re: [Mesa-dev] [PATCH 11/28] util: added float to float16 conversions with RTZ and RTNE

Hello Matt, On 07/12/2018 03:20, Matt Turner wrote: > Since this is for an extension that will be BDW+ can we use the > _cvtss_sh() intrinsic instead? It corresponds to an IVB+ instruction > and even takes the rounding mode directly as an immediate argument. > If I understand currently this

Re: [Mesa-dev] [PATCH 17/28] intel/nir: call nir_opt_constant_folding before nir_opt_algebraic is executed

ec1 32 ssa_10 = fmul ssa_5, ssa_19 <<<< denorm * 0 Is it possible to represent fmul (a, 0) = 0 if 'a' is not NaN? Or fmul(a, NaN) = NaN? Do you have any other suggestion? Sam > On Wed, Dec 5, 2018 at 4:56 PM Samuel Iglesias Gonsálvez > wrote: >> >> This w

Re: [Mesa-dev] [PATCH 15/28] nir: support for denorm flush-to-zero in nir_lower_double_ops

nir_feq(b, src, nir_imm_double(b, INFINITY))), src, res); } Notice that we can return 'src', which is not flushed. We fail 3 tests because of this. If you agree, I will fix it here instead for all the double lowerings. Sam > On Wed, Dec 5, 2018 at 4:56 PM Samu

Re: [Mesa-dev] [PATCH 15/28] nir: support for denorm flush-to-zero in nir_lower_double_ops

sary. Right, thanks for reporting it. Sam > On Wed, Dec 5, 2018 at 4:56 PM Samuel Iglesias Gonsálvez > wrote: >> >> Signed-off-by: Samuel Iglesias Gonsálvez >> --- >> src/compiler/nir/nir_lower_double_ops.c | 12 >> 1 file changed, 12 i

Re: [Mesa-dev] [PATCH 25/28] i965/fs: add support for shader float control to remove_extra_rounding_modes()

On 06/12/2018 08:40, apinheiro wrote: > > On 6/12/18 8:37, apinheiro wrote: >> On 5/12/18 16:55, Samuel Iglesias Gonsálvez wrote: >>> The remove_extra_rounding_modes() optimization will remove duplicated >>> rounding mode changes. >>> >&

Re: [Mesa-dev] [PATCH 04/28] nir: add support for flushing to zero denorm constants

fix the rest of things you mentioned here. Sam > On Wed, Dec 5, 2018 at 4:56 PM Samuel Iglesias Gonsálvez > wrote: >> >> Signed-off-by: Samuel Iglesias Gonsálvez >> --- >> src/compiler/nir/nir_opt_constant_folding.c | 74 +++-- >> 1 file chan

[Mesa-dev] [PATCH 13/28] nir: take into account rounding modes in conversions

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir.h | 15 +++ src/compiler/nir/nir_constant_expressions.py | 46 +--- src/compiler/spirv/vtn_alu.c | 16 ++- 3 files changed, 71 insertions(+), 6 deletions(-) diff --git

[Mesa-dev] [PATCH 19/28] i965/fs: add nir_op_f2f*_{rtne,rtz}

This way, we can implement its support later if SPIR-V supports it. Right now, the RTZ, RTNE support in SPIR-V in FPRoundingMode only applies to f2f16 conversions. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 22 +- 1 file changed, 21

[Mesa-dev] [PATCH 23/28] i965/fs: emit shader float controls execution modes as first instruction of shaders

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 32e0817ce02..18dcd92219c 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel

[Mesa-dev] [PATCH 20/28] i965/fs/nir: add nir_op_unpack_half_2x16_split_*_flush_to_zero

The denorm mode is set in the control register, no need to do something else. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index

[Mesa-dev] [PATCH 02/28] spirv: check support for SPV_KHR_shader_float_controls capabilities

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/shader_info.h| 1 + src/compiler/spirv/spirv_to_nir.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index e745cc15fc5..21c3d371a63 100644 --- a/src/compiler

[Mesa-dev] [PATCH 09/28] nir/algebraic: fix (inf - inf) = NaN case

If we have (inf - inf) we should return NaN, not 0.0. Same for (NaN - NaN) case. Fixes tests in Vulkan CTS that produce such kind subtractions. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_opt_algebraic.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/compiler

[Mesa-dev] [PATCH 15/28] nir: support for denorm flush-to-zero in nir_lower_double_ops

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_lower_double_ops.c | 12 1 file changed, 12 insertions(+) diff --git a/src/compiler/nir/nir_lower_double_ops.c b/src/compiler/nir/nir_lower_double_ops.c index b3543bc6963..97b825d2fdb 100644 --- a/src/compiler/nir

[Mesa-dev] [PATCH 04/28] nir: add support for flushing to zero denorm constants

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_opt_constant_folding.c | 74 +++-- 1 file changed, 68 insertions(+), 6 deletions(-) diff --git a/src/compiler/nir/nir_opt_constant_folding.c b/src/compiler/nir/nir_opt_constant_folding.c index 1fca530af24

[Mesa-dev] [PATCH 08/28] spirv/glsl450: fix reflect(denorm, denorm) FTZ = 0.0 case

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 0115648cbb0..69588f56968 100644 --- a/src/compiler/spirv

[Mesa-dev] [PATCH 10/28] nir: create new conversion opcodes with floating point rounding modes

It adds round-towards-zero and round-to-nearest-even opcodes for floating point conversions. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_opcodes.py | 2 +- src/compiler/nir/nir_opcodes_c.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 07/28] spirv/glsl450: fix atan2(x, x) case

If x < 0 -> atan2(x, x) = -3*pi/4. If x > 0 -> atan2(x, x) = pi/4. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_gls

[Mesa-dev] [PATCH 18/28] intel/nir: call nir_opt_constant_folding before brw_nir_apply_trig_workarounds

-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_nir.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 600f7a97df9..41e27054595 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler

[Mesa-dev] [PATCH 16/28] nir: fix fmin/fmax support for doubles

Until now, it was using the floating point version of fmin, instead of the double version. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_opcodes.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir

[Mesa-dev] [PATCH 03/28] spirv/nir: keep track of SPV_KHR_shader_float_controls execution modes

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/shader_enums.h | 14 ++ src/compiler/shader_info.h| 3 +++ src/compiler/spirv/spirv_to_nir.c | 26 ++ 3 files changed, 43 insertions(+) diff --git a/src/compiler/shader_enums.h b/src

[Mesa-dev] [PATCH 06/28] spirv/glsl450: fix atan2(0,0) lowering

We were returning 3*pi/4 when we should return 0.0 according to IEEE 754. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c

[Mesa-dev] [PATCH 27/28] anv: enable support for SPV_KHR_shader_float_controls capabilities

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index d55e51adcbb..cadf9288ad9 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan

[Mesa-dev] [PATCH 28/28] anv: enable VK_KHR_shader_float_controls extension

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_extensions.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py index 9ca42d998ef..d572df3c342 100644 --- a/src/intel/vulkan/anv_extensions.py +++ b/src

[Mesa-dev] [PATCH 24/28] i965/fs: remove brw_rounding_mode() and use brw_float_controls_mode() instead

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_eu.h | 4 --- src/intel/compiler/brw_eu_emit.c| 36 - src/intel/compiler/brw_fs_generator.cpp | 13 +++-- src/intel/compiler/brw_fs_nir.cpp | 18 +++-- 4 files

[Mesa-dev] [PATCH 26/28] anv: add support for VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES_KHR

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_device.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 17b73c115cd..af07c7c831e 100644 --- a/src/intel/vulkan/anv_device.c

[Mesa-dev] [PATCH 25/28] i965/fs: add support for shader float control to remove_extra_rounding_modes()

The remove_extra_rounding_modes() optimization will remove duplicated rounding mode changes. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs.cpp | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler

[Mesa-dev] [PATCH 21/28] i965/fs/generator: add support to set floating points modes in control register

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_eu.h | 4 src/intel/compiler/brw_eu_defines.h | 10 ++ src/intel/compiler/brw_eu_emit.c| 26 + src/intel/compiler/brw_fs_generator.cpp | 8 +++- src/intel

[Mesa-dev] [PATCH 22/28] i965/fs: define emit_shader_float_controls_execution_mode() and aux functions

We need this function to emit code that setups the control register later with the defined execution mode for the shader. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs.h | 1 + src/intel/compiler/brw_fs_visitor.cpp | 52 +++ 2 files

[Mesa-dev] [PATCH 11/28] util: added float to float16 conversions with RTZ and RTNE

Signed-off-by: Samuel Iglesias Gonsálvez --- src/util/half_float.c | 74 +++ src/util/half_float.h | 7 2 files changed, 81 insertions(+) diff --git a/src/util/half_float.c b/src/util/half_float.c index 63aec5c5c14..5fdcb20045b 100644 --- a/src/util

[Mesa-dev] [PATCH 17/28] intel/nir: call nir_opt_constant_folding before nir_opt_algebraic is executed

This would do constant folding and also flush to zero denorms operands before the nir_opt_algebraic is executed. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_nir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel

[Mesa-dev] [PATCH 14/28] nir: fix denorms in unpack_half_1x16()

serve execution mode." Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_constant_expressions.py | 13 + src/compiler/nir/nir_lower_alu_to_scalar.c | 10 -- src/compiler/nir/nir_opcodes.py | 5 + 3 files changed, 26 insertions(+), 2

[Mesa-dev] [PATCH 12/28] util: add fp64 -> fp32 conversion support for RTNE and RTZ rounding modes

Signed-off-by: Samuel Iglesias Gonsálvez --- src/util/Makefile.sources | 2 + src/util/double.c | 197 ++ src/util/double.h | 46 + src/util/meson.build | 2 + 4 files changed, 247 insertions(+) create mode 100644 src/util

[Mesa-dev] [PATCH 05/28] Revert "spirv: Don’t check for NaN for most OpFOrd* comparisons"

This reverts commit c4ab1bdcc9710e3c7cc7115d3be9c69b7e7712ef. We need to check the arguments looking for NaNs, because they can introduce failures in tests for FOrd*, specially when running VK_KHR_shader_float_control tests in CTS. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv

[Mesa-dev] [PATCH 01/28] spirv: Update SPIR-V json and headers to Khronos master

This corresponds to commit 17da9f8231f78cf519b4958c2229463a63ead9e2 on GitHub. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/spirv.core.grammar.json | 316 +++-- src/compiler/spirv/spirv.h | 84 +++--- 2 files changed, 281 insertions(+), 119

[Mesa-dev] [PATCH 00/28] Add VK_KHR_shader_float_controls support to anv

siglesias/VK_KHR_shader_float_controls \ https://github.com/Igalia/mesa.git Thanks! Sam [0] https://lists.freedesktop.org/archives/mesa-dev/2018-December/210896.html Samuel Iglesias Gonsálvez (28): spirv: Update SPIR-V json and headers to Khronos master spirv: check support

Re: [Mesa-dev] [PATCH 1/2] vulkan: Update the XML and headers to 1.1.93

Patch series is, Reviewed-by: Samuel Iglesias Gonsálvez Sam On 19/11/2018 16:39, Jason Ekstrand wrote: > --- > include/vulkan/vulkan_core.h | 35 --- > src/vulkan/registry/vk.xml | 84 +--- > 2 files changed, 98 insertions(+),

Re: [Mesa-dev] [PATCH] anv: allow exporting an imported SYNC_FD semaphore type

Reviewed-by: Samuel Iglesias Gonsálvez On 22/11/2018 08:41, Tapani Pälli wrote: > Fixes issues with following SkQP tests: > >unitTest_VulkanHardwareBuffer_Vulkan_EGL_Syncs >unitTest_VulkanHardwareBuffer_Vulkan_Vulkan_Syncs > > Signed-off-by: Tapani Pälli > --

Re: [Mesa-dev] [PATCH 0/8] intel: Move shared/SSBO access lowering to NIR

ed, Nov 14, 2018 at 5:48 AM Samuel Iglesias Gonsálvez > mailto:sigles...@igalia.com>> wrote: > > Thanks a lot for this work. Patches 1-7 are, > >   Reviewed-by: Samuel Iglesias Gonsálvez <mailto:sigles...@igalia.com>> > > I will review patch

Re: [Mesa-dev] [PATCH] nir/lower_io: Add shared to get_io_offset_src

Reviewed-by: Samuel Iglesias Gonsálvez On 14/11/2018 22:36, Jason Ekstrand wrote: > --- > src/compiler/nir/nir_lower_io.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c > index f3377eaec8f..

Re: [Mesa-dev] [PATCH 8/8] intel/compiler: Lower SSBO and shared loads/stores in NIR

e can easily share the code between the bec4 vec4 Reviewed-by: Samuel Iglesias Gonsálvez > and FS back-ends if we wish. > --- > src/intel/Makefile.sources| 1 + > src/intel/compiler/brw_fs_nir.cpp | 381 -- > s

Re: [Mesa-dev] [PATCH 0/8] intel: Move shared/SSBO access lowering to NIR

Thanks a lot for this work. Patches 1-7 are, Reviewed-by: Samuel Iglesias Gonsálvez I will review patch 8 later, probably tomorrow. Sam On 14/11/2018 00:23, Jason Ekstrand wrote: > In order to properly do all the different kinds of SSBO and SLM writes that > we have in GL and Vulk

Re: [Mesa-dev] [PATCH] nir/constant_folding: fix incorrect bit-size check

Reviewed-by: Samuel Iglesias Gonsálvez Sam On Wednesday, 31 October 2018 12:18:34 (CET) Iago Toral Quiroga wrote: > nir_alu_type_get_type_size takes a type as parameter and we were > passing a bit-size instead, which did what we wanted by accident, > since a bit-size of zer

Re: [Mesa-dev] [PATCH] intel/compiler: fix node interference of simd16 instructions

; - if (inst->dst.file != VGRF) > -continue; > + /* In 16-wide instructions we have an issue where a compressed > + * instruction is actually two instructions executed simultaneiously. simultaneously With these two changes, Reviewed-by: Samuel Iglesias Gonsálvez

Re: [Mesa-dev] [PATCH] intel/compiler: Print hex representation along with floating point value

Pushed both patches! :-) Sam On Thu, 2018-10-25 at 09:45 -0700, Sagar Ghuge wrote: > Thank you for reviewing the patch. > > On 10/25/18 12:40 AM, Samuel Iglesias Gonsálvez wrote: > > Reviewed-by: Samuel Iglesias Gonsálvez > > > > Do you need somebody to pu

Re: [Mesa-dev] [PATCH] intel/compiler: Print message descriptor as immediate source

ot found it written in the coding style guidelines [0], but I have seen it in a lot of places of the code. I can do this change for you before pushing it tomorrow. Sounds good? With that fixed, Reviewed-by: Samuel Iglesias Gonsálvez Sam [0] https://www.mesa3d.org/codingstyle.html > + /*

Re: [Mesa-dev] [PATCH] intel/compiler: Print hex representation along with floating point value

Reviewed-by: Samuel Iglesias Gonsálvez Do you need somebody to push it to the repo? I can do it tomorrow. Sam On Wednesday, 24 October 2018 22:27:27 (CEST) Sagar Ghuge wrote: > While encoding the immediate floating point values in instruction we use > values upto precision 9, but

Re: [Mesa-dev] [PATCH] intel/compiler: Change src1 reg type to unsigned doubleword

hat fixed and assuming no problems appeared on Intel CI, Reviewed-by: Samuel Iglesias Gonsálvez Sam > default type. > > Signed-off-by: Sagar Ghuge > --- > src/intel/compiler/brw_eu_emit.c| 2 +- > src/intel/compiler/brw_fs_generator.cpp | 4 ++-- > 2 files changed

Re: [Mesa-dev] [PATCH 0/9] nir: Add better helpers for handling constant sources

Patch 7/9 has never arrived my inbox and checking the archives [0], looks like the archive is messed up... it has only a few emails. Does somebody know what happened with the ML archive? Sam [0] https://lists.freedesktop.org/archives/mesa-dev/2018-October/date.html On Saturday, 20 October

Re: [Mesa-dev] [PATCH 0/6] nir: Cleanups for opt_algebraic

With the typo fix on patch 5/6 suggested by Matt, this patch series is: Reviewed-by: Samuel Iglesias Gonsálvez Sam On Saturday, 20 October 2018 20:01:28 (CEST) Jason Ekstrand wrote: > This little series provides some cleanups for opt_algebraic. The most > important of which is

Re: [Mesa-dev] [PATCH] nir: add initializer data to fix MSVC compile error

Reviewed-by: Samuel Iglesias Gonsálvez <mailto:sigles...@igalia.com> On 19/09/18 11:40, Juan A. Suarez Romero wrote: > CC: Jason Ekstrand > Fixes: 82799a5d1b8 ("nir: Add a small pass to rematerialize derefs > per-block") > --- > src/compiler/nir/nir_dere

Re: [Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active

On 28/08/18 23:41, Andres Gomez wrote: > Andrii, Samuel, should we also include this in the stable queues ? Yes, please. Add it to stable queue. Sam > > On Wed, 2018-08-15 at 18:20 +0300, asimiklit.w...@gmail.com wrote: >> From: Andrii Simiklit >> >> When the SVBI Payload Enable is false I

Re: [Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active

On Tuesday, August 28, 2018 2:02:07 PM CEST Samuel Iglesias Gonsálvez wrote: > I'll do it later today. Done! Sam > > Thanks for contributing! > > Sam > > On 28/08/18 13:59, andrey simiklit wrote: > > Hi all, > > > > Could somebody push it if

Re: [Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active

I'll do it later today. Thanks for contributing! Sam On 28/08/18 13:59, andrey simiklit wrote: > Hi all, > > Could somebody push it if it seems good for all? > > Regards, > Andrii. > > On Thu, Aug 23, 2018 at 4:53 PM Samuel Iglesias Gonsálvez > mailto:s

[Mesa-dev] [PATCH] anv: Add support for protected memory properties on anv_GetPhysicalDeviceProperties2()

VkPhysicalDeviceProtectedMemoryProperties structure is new on Vulkan 1.1. Fixes Vulkan CTS CL#2849. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_device.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan

Re: [Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active

The patch seems fine to me. I also tested it on Intel CI and there were no regressions. Reviewed-by: Samuel Iglesias Gonsálvez Thanks, Sam On 15/08/18 17:20, asimiklit.w...@gmail.com wrote: > From: Andrii Simiklit > > When the SVBI Payload Enable is false I guess the register R1.

[Mesa-dev] [PATCH] anv: fix assert in anv_CmdBindDescriptorSets()

The assert is checking that we are not binding more descriptor sets than the supported by the driver. When binding the descriptor set number MAX_SETS-1, it was breaking the assert because descriptorSetCount = 1. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_cmd_buffer.c | 2

Re: [Mesa-dev] [PATCH 1/2] intel/blorp: Fix blits to R8G8B8_UNORM_SRGB

Assuming Jenkins is happy with them, this series is Reviewed-by: Samuel Iglesias Gonsálvez Sam On 13/07/18 00:48, Jason Ekstrand wrote: > In this case, the surface faking will give us a R8_UNORM surface and we > need to do an sRGB conversion in the shader. > >

Re: [Mesa-dev] [PATCH] intel/fs: use uint type for per_slot_offset at GS

Reviewed-by: Samuel Iglesias Gonsálvez On 12/06/18 18:51, Jose Maria Casanova Crespo wrote: > This helps us to compact original instruction: > > mul(8) g3<1>D g6<8,8,1>UD 0x0006UD { align1 1Q }; > > So now we emit: > > mul(8) g3<1>UD g6<8,

[Mesa-dev] [PATCH 2/2] spirv: implement support for OpAtomicLoad for image pointers

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/spirv_to_nir.c | 33 +++ 1 file changed, 33 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index e8ab48012f5..dc00d853c39 100644 --- a/src/compiler

[Mesa-dev] [PATCH 1/2] spirv: implement support for OpAtomicStore for image pointers

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/spirv_to_nir.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index fb4211193fb..e8ab48012f5 100644 --- a/src/compiler/spirv

[Mesa-dev] [PATCH] nir/opt_if: Remove unneeded phis if we make progress

Thanks a lot for fixing this, Reviewed-by: Samuel Iglesias Gonsálvez Sam On 26/06/18 01:47, Jason Ekstrand wrote: > Now that SSA values can be derefs and they have special rules, we have > to be a bit more careful about our LCSSA phis. In particular, we need > to clean up in case LC

Re: [Mesa-dev] [PATCH] nir: fixup intrinsic comment

Reviewed-by: Samuel Iglesias Gonsálvez On 25/06/18 14:17, Rob Clark wrote: > Now the deref is the first src. > > Signed-off-by: Rob Clark > --- > src/compiler/nir/nir_intrinsics.py | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/compiler/ni

Re: [Mesa-dev] [PATCH] anv: reduce maxFragmentInputComponents

This patch is still unreviewed. Sam On 29/05/18 09:07, Samuel Iglesias Gonsálvez wrote: > If the application asks for the maximum number of fragment input > components (128), use all of them plus some builtins that are > passed in the VUE, then we exceed the maximum number of used VU

[Mesa-dev] [PATCH v2 02/22] i965/fs: Implement float64/int64 to float16 conversion

It is not supported directly in the HW, we need to convert to a 32-bit type first as intermediate step. v2 (Iago): handle conversions from 64-bit integers as well Signed-off-by: Samuel Iglesias Gonsálvez --- Added missing (u)int64 -> fp16 conversion and fixed issues with the fallthrou

[Mesa-dev] [PATCH] anv: reduce maxFragmentInputComponents

CLIP_DIST0, CLIP_DIST1 builtins in brw_compute_vue_map() because we don't know if gl_ClipDistance is going to be read/write by an adjacent stage. Fixes VK-GL-CTS CL#2569. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

Re: [Mesa-dev] [PATCH 0/2] i965: Add support for fp16 <-> fp64 conversions

ping On 25/04/18 12:35, Samuel Iglesias Gonsálvez wrote: > These two patches are still unreviewed. > > Sam > > > On 13/04/18 07:30, Samuel Iglesias Gonsálvez wrote: >> Hello, >> >> This series implements support for doing fp16 <-> fp64 conversi

Re: [Mesa-dev] [PATCH] anv: ignore pColorBlendState if all color attachments of the subpass are unused

;& blend->pAttachments[binding->index].colorWriteMask != 0)   return true;     }   What do you think? Sam > > On Mon, May 7, 2018 at 1:01 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com <mailto:sigles...@igalia.com>> wrote: > > Accordi

[Mesa-dev] [PATCH] anv: ignore pColorBlendState if all color attachments of the subpass are unused

color attachments." Fixes tests from CL#2505: dEQP-VK.renderpass.*.simple.color_unused_omit_blend_state Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/vulkan/anv_pipeline.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/

Re: [Mesa-dev] [PATCH 2/2] spirv: convert the offset and count operands for bitfield ops to uint32

On 30/04/18 20:51, Jason Ekstrand wrote: > On Mon, Apr 30, 2018 at 1:46 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com <mailto:sigles...@igalia.com>> wrote: > > On 26/04/18 18:14, Jason Ekstrand wrote: >> >> >> On Thu, Apr 26,

[Mesa-dev] [PATCH v2] spirv: convert some operands for bitwise shift and bitwise ops to uint32

://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html v2: - src_bit_size will have zero value for variable bit-size operands (Jason). Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/spirv/vtn_alu.c | 34 ++ 1 file chang

[Mesa-dev] [PATCH] spirv: convert some operands for bitwise shift and bitwise ops to uint32

://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/spirv/vtn_alu.c | 47 1 file changed, 47 insertions(+) diff --git a/src/compiler/spirv/vtn_alu.c b/src/co

Re: [Mesa-dev] [PATCH 2/2] spirv: convert the offset and count operands for bitfield ops to uint32

On 26/04/18 18:14, Jason Ekstrand wrote: > > > On Thu, Apr 26, 2018 at 2:24 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com <mailto:sigles...@igalia.com>> wrote: > > SPIR-V allows to define the shift operand for shift opcodes with > a bit-size d

[Mesa-dev] [PATCH 2/2] spirv: convert the offset and count operands for bitfield ops to uint32

/2018-April/193026.html Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/spirv/vtn_alu.c | 48 1 file changed, 48 insertions(+) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 6f3b8

[Mesa-dev] [PATCH 1/2] spirv: convert the shift operand for bitwise shift ops to uint32

/2018-April/193026.html Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/spirv/vtn_alu.c | 20 1 file changed, 20 insertions(+) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 71e743cdd1e..6f3b82cd5c3

Re: [Mesa-dev] [PATCH] spirv: convert the shift operand for bitwise shift ops to uint32

Please ignore this patch, I'm about to send a patch series that includes this patch and another one for bitfield ops. Sam On 25/04/18 14:07, Samuel Iglesias Gonsálvez wrote: > SPIR-V allows to define the shift operand for shift opcodes with > a bit-size different than 32 bits, but

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