Re: [Mesa-dev] [PATCH 04/27] i965/gen6: Remove check for stencil format

On Mon, 2017-01-16 at 11:13 +0200, Topi Pohjolainen wrote: > There are is no alternative. > There is no alternative. Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> > --- >

Re: [Mesa-dev] [PATCH 17/22] i965/vec4: fix register_coalesce() for partial writes

On Mon, 2017-01-16 at 09:01 +0100, Samuel Iglesias Gonsálvez wrote: > On Fri, 2017-01-13 at 15:46 -0800, Matt Turner wrote: > > On Thu, Jan 5, 2017 at 5:07 AM, Samuel Iglesias Gonsálvez > > <sigles...@igalia.com> wrote: > > > From: "Juan A. Suarez Romero"

[Mesa-dev] [PATCH v2] anv: increase ANV_MAX_STATE_SIZE_LOG2 limit to 1 MB

off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/vulkan/anv_device.c | 2 +- src/intel/vulkan/anv_private.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 6349537d172..f80a36a94

Re: [Mesa-dev] [PATCH 17/22] i965/vec4: fix register_coalesce() for partial writes

On Fri, 2017-01-13 at 15:46 -0800, Matt Turner wrote: > On Thu, Jan 5, 2017 at 5:07 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > When lowering double_to_single() we a

Re: [Mesa-dev] [PATCH 14/22] i965/vec4: fix double_to_single() for IVB/VLV

On Fri, 2017-01-13 at 14:40 -0800, Matt Turner wrote: > On Thu, Jan 5, 2017 at 5:07 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > In the generator we must generate sligh

Re: [Mesa-dev] [PATCH 09/22] i965/fs: add lowering x2d step for IVB/VLV

On Fri, 2017-01-13 at 14:36 -0800, Matt Turner wrote: > On Thu, Jan 5, 2017 at 5:07 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > On Ivybridge/Valleyview, when converti

Re: [Mesa-dev] [PATCH] i965: Enable OpenGL 4.5 on Haswell.

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> :-D On Fri, 2017-01-13 at 22:53 -0800, Kenneth Graunke wrote: > Everything is in place and the test results look solid. > > Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> > --- >  src/mesa/drivers/

Re: [Mesa-dev] [PATCH] anv: increase ANV_MAX_STATE_SIZE_LOG2 limit to 256 kB

On Fri, 2017-01-13 at 08:29 -0800, Jason Ekstrand wrote: On Fri, Jan 13, 2017 at 1:33 AM, Samuel Iglesias Gonsálvez <sigles...@igalia.com> wrote: Fixes crash in dEQP-VK.ubo.random.all_shared_buffer.48 due to a fragment shader code bigger than 128 kB. This patch increases the allocatio

Re: [Mesa-dev] [PATCH] anv: move nir_lower_wpos_center to later

e rest of optimizations will >> take care of removing unused inputs for each stage, so we don't >> lower the wrong fragment shader's built-in position input. >> >> Fixes a crash in: >> >> dEQP-VK.spirv_assembly.instruction.graphics.module.same_mod >> >> Signed-

[Mesa-dev] [PATCH] anv: move nir_lower_wpos_center to later

sition input. Fixes a crash in: dEQP-VK.spirv_assembly.instruction.graphics.module.same_mod Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/vulkan/anv_pipeline.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/

[Mesa-dev] [PATCH] anv: increase ANV_MAX_STATE_SIZE_LOG2 limit to 256 kB

Fixes crash in dEQP-VK.ubo.random.all_shared_buffer.48 due to a fragment shader code bigger than 128 kB. This patch increases the allocation size limit to 256 kB. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- OpenGL driver compares the code size against the allocated

Re: [Mesa-dev] [PATCH 08/22] i965/fs: fix lower SIMD width for IVB/VLV's MOVE_INDIRECT

On Thu, 2017-01-12 at 16:45 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > Previous to Broadwell, we have 8 registers for MOV_INDIRECT. But i

Re: [Mesa-dev] [PATCH 12/22] i965/vec4: split DF instructions and later duplicate its execsize in IVB/VLV

On Thu, 2017-01-12 at 15:39 -0800, Matt Turner wrote: > On Thu, Jan 5, 2017 at 5:07 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: > > We need to split DF instructions in two on IVB/VLV as it needs an > > execsize 8 to process 4 DF values (one GRF in tot

Re: [Mesa-dev] [PATCH 02/22] i965/fs: add helper to retrieve instruction data size

On Thu, 2017-01-12 at 15:14 -0800, Matt Turner wrote: > On Thu, Jan 5, 2017 at 5:07 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > The execution data size is the bi

Re: [Mesa-dev] [PATCH] spirv: fix typo in warning message

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Mon, 2017-01-09 at 16:09 +0100, Iago Toral Quiroga wrote: > --- >  src/compiler/spirv/spirv_to_nir.c | 2 +- >  1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/compiler/spirv/spirv_to_nir.c &

Re: [Mesa-dev] [PATCH 04/22] i965/fs: add lowering step to duplicate sources with stride 0.

On Tue, 2017-01-10 at 22:07 -0800, Francisco Jerez wrote: > Hi Matt, > > Matt Turner <matts...@gmail.com> writes: > > > On Sun, Jan 8, 2017 at 10:53 PM, Matt Turner <matts...@gmail.com> > > wrote: > > > On 01/05, Samuel Iglesias Gonsálvez wrote:

Re: [Mesa-dev] [PATCH 06/22] i965/fs: double-precision execution does not use 2 channels per DF in IVB/VLV

On Tue, 2017-01-10 at 14:01 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > On Mon, 2017-01-09 at 16:18 -0800, Francisco Jerez wrote: > > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > &

Re: [Mesa-dev] [PATCH 01/22] i965/disasm: also print nibctrl in IVB for execsize=8

On Mon, 2017-01-09 at 14:42 -0800, Francisco Jerez wrote: > Matt Turner <matts...@gmail.com> writes: > > > On 01/05, Samuel Iglesias Gonsálvez wrote: > > > From: Iago Toral Quiroga <ito...@igalia.com> > > > > > > 4-wide DF operations wh

Re: [Mesa-dev] [PATCH] nir: change asserts to unreachable in nir_type_conversion_op

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Tue, 2017-01-10 at 10:14 +0200, Tapani Pälli wrote: > this is to avoid following compilation error on Android: > >    error: control may reach end of non-void function [-Werror,- > Wreturn-type] > > Sig

Re: [Mesa-dev] [PATCH 06/22] i965/fs: double-precision execution does not use 2 channels per DF in IVB/VLV

On Mon, 2017-01-09 at 16:18 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > From: Iago Toral Quiroga <ito...@igalia.com> > > > > It seems to use 1 channel por DF, just like later hardware. The > > docs say

Re: [Mesa-dev] [PATCH v3 21/22] anv: enable float64 feature on supported platforms

On Thu, 2017-01-05 at 12:46 -0800, Jason Ekstrand wrote: > With the image_ms_array line removed (I don't believe we support > that), 20-22 are > > Reviewed-by: Jason Ekstrand > I have applied all the suggestions and pushed the patches to master. Thanks a lot for the

[Mesa-dev] [PATCH] docs: add Vulkan Float64 capability support for anv driver

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- docs/relnotes/13.1.0.html | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/relnotes/13.1.0.html b/docs/relnotes/13.1.0.html index be1ab0d76ef..662f0ceb070 100644 --- a/docs/relnotes/13.1.0.html +++ b/docs/relnotes/

Re: [Mesa-dev] [PATCH v3 06/22] spirv: fix SpvOpSpecConstantOp with SpvOpVectorShuffle working with double-based vecs

On Thu, 2017-01-05 at 17:32 +0100, Erik Faye-Lund wrote: > > > On Jan 5, 2017 10:20, "Samuel Iglesias Gonsálvez" <siglesias@igalia.c > om> wrote: > We need to pick two 32-bit values per component to perform the right > shuffle operation. > > v2 (Jaso

Re: [Mesa-dev] [PATCH 00/22] i965 Ivybridge ARB_gpu_shader_fp64 / OpenGL 4.0

On Sun, 2017-01-08 at 22:59 -0800, Matt Turner wrote: > I have just started reviewing the series, and I have two trivial > comments that seem to apply to a number of patches. The first is that > we > prefer to use the name BayTrail (abbreviation BYT) instead of > Valleyview > (and its abbreviation

[Mesa-dev] [PATCH 22/22] docs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by i965/gen7+

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- docs/features.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index f4a67df..18327af 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -107,7 +107,7

[Mesa-dev] [PATCH 21/22] i965: enable OpenGL 4.0 to Ivybridge/Valleyview

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- src/mesa/drivers/dri/i965/intel_screen.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/sr

[Mesa-dev] [PATCH 20/22] i965: enable ARB_gpu_shader_fp64 for Ivybridge/Valleyview

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/intel_extensions.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 2

[Mesa-dev] [PATCH 19/22] i965/vec4: fix SIMD-with lowering for CMP/MOV instructions with conditional modifiers

ring without any problem. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 80 +++--- 1 file changed, 74 insertions(+), 6 deletions(-) diff --g

[Mesa-dev] [PATCH 14/22] i965/vec4: fix double_to_single() for IVB/VLV

From: "Juan A. Suarez Romero" In the generator we must generate slightly different code for Ivybridge/Valleview, because of the way the stride works in this hardware. --- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 26 +--- 1 file changed, 23

[Mesa-dev] [PATCH 18/22] i965/vec4: adapt setup_imm_df() to allow inserting instructions before another one

Add a new setup_imm_df() that alows the insertion of the instructions before another one. This will be used in the lowering passes for DF instructions. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_vec4.h | 2 ++ src/mesa/drive

[Mesa-dev] [PATCH 17/22] i965/vec4: fix register_coalesce() for partial writes

From: "Juan A. Suarez Romero" When lowering double_to_single() we added a final mov() that puts 32-bit values from one register in the second half of destination. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 5 +

[Mesa-dev] [PATCH 15/22] i965/vec4: fix SIMD-width lowering for double_to_single operation in IVB/VLV

From: "Juan A. Suarez Romero" When spliting double_to_single() in Ivybridge/Valleyview, the second part should use a temporal register, and then move the values to the second half of the original destiny, so we get all the results in the same register. ---

[Mesa-dev] [PATCH 16/22] i965/vec4: consider subregister offset in live variables

From: "Juan A. Suarez Romero" Take in account the offset value when getting the var from register. This is required when dealing with an operation that writes half of the register (like one d2x in IVB/VLV, which uses exec_size == 4). Note that for live analysis variables

[Mesa-dev] [PATCH 13/22] i965/vec4: keep original type when dealing with null registers

From: "Juan A. Suarez Romero" Keep the original type when dealing with null registers. Specially because we do no want to introduce an implicit conversion between types that could affect the conditional flags. This affects specially when the original type is DF, and we are

[Mesa-dev] [PATCH 11/22] i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/VLV

The hardware applies the same channel enable signals to both halves of the compressed instruction which will be just wrong under non-uniform control flow. Fix this by splitting those instructions to SIMD4. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drive

[Mesa-dev] [PATCH 07/22] i965/fs: fix dst stride in IVB/VLV type conversions

From: "Juan A. Suarez Romero" When converting a DF to F, we set dst stride to 2, to fulfil alignment restrictions. But in IVB/VLV, this is not necessary, as each DF conversion already writes 2 F, the first one the real value, and the second one a 0. That is, IVB/VLV already

[Mesa-dev] [PATCH 12/22] i965/vec4: split DF instructions and later duplicate its execsize in IVB/VLV

We need to split DF instructions in two on IVB/VLV as it needs an execsize 8 to process 4 DF values (one GRF in total). Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_ir_vec4.h | 1 + src/mesa/drivers/dri/i965/brw_ve

[Mesa-dev] [PATCH 09/22] i965/fs: add lowering x2d step for IVB/VLV

From: "Juan A. Suarez Romero" On Ivybridge/Valleyview, when converting a float (F) to a double precision float (DF), the hardware automatically duplicates the source horizontal stride, hence converting only the values in odd positions. This commit adds a new lowering step,

[Mesa-dev] [PATCH 03/22] i965/fs: duplicate regioning parameters and execsize for DF in IVB/VLV

From: "Juan A. Suarez Romero" In IVB and VLV, both regioning parameters and execution sizes are measured as floats. So when we have something like: mov(8) g2<1>DF g3<4,4,1>DF We are not actually moving 8 doubles (our intention), but 4 doubles. We need to duplicate the

[Mesa-dev] [PATCH 08/22] i965/fs: fix lower SIMD width for IVB/VLV's MOVE_INDIRECT

From: "Juan A. Suarez Romero" Previous to Broadwell, we have 8 registers for MOV_INDIRECT. But if IVB/VLV deal with DFs, we will duplicate the exec_size from 8 to 16. This patch limits the SIMD width to 4 in this case. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 9 +++--

[Mesa-dev] [PATCH 10/22] i965/fs: indirect addressing with doubles is not supported in IVB/VLV

-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 23 --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 11 ++- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/src/mesa/drivers/dr

[Mesa-dev] [PATCH 06/22] i965/fs: double-precision execution does not use 2 channels per DF in IVB/VLV

From: Iago Toral Quiroga It seems to use 1 channel por DF, just like later hardware. The docs say things like: "Each DF operand uses a pair of channels and all masking and swizzling should be adjusted appropriately." "In Align16, all regioning parameters must use the

[Mesa-dev] [PATCH 02/22] i965/fs: add helper to retrieve instruction data size

From: "Juan A. Suarez Romero" The execution data size is the biggest type size of any instruction operand. We will use it to know if the instruction deals with DF, because in Ivy we need to duplicate the execution size and regioning parameters. ---

[Mesa-dev] [PATCH 00/22] i965 Ivybridge ARB_gpu_shader_fp64 / OpenGL 4.0

IVB/VLV i965/vec4: consider subregister offset in live variables i965/vec4: fix register_coalesce() for partial writes i965/vec4: fix SIMD-with lowering for CMP/MOV instructions with conditional modifiers Samuel Iglesias Gonsálvez (7): i965/fs: indirect addressing with doubles is not sup

[Mesa-dev] [PATCH 01/22] i965/disasm: also print nibctrl in IVB for execsize=8

From: Iago Toral Quiroga 4-wide DF operations where NibCtrl applies require and execsize of 8 in IvyBridge/Valleyview. --- src/mesa/drivers/dri/i965/brw_disasm.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c

[Mesa-dev] [PATCH 05/22] i965/fs: consider execsize can be duplicated in lower_simd_with

From: "Juan A. Suarez Romero" In IVB/VLV, for instructions dealing with DF, execsize will be duplicated in the final code. So take this in account when checking if instructions should be split. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 13 - 1 file changed, 12

[Mesa-dev] [PATCH 04/22] i965/fs: add lowering step to duplicate sources with stride 0.

From: "Juan A. Suarez Romero" When dealing with DF uniforms with just 1 component, we set stride 0 to use the value along the operation. However, when duplicating the regioning parameters in IVB/VLV, we are violating the regioning restrictions. So instead of using the value

[Mesa-dev] [PATCH v3 07/22] spirv: add double support to SpvOpCompositeExtract

v2 (Jason): - Add asserts. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/spirv/spirv_to_nir.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/co

[Mesa-dev] [PATCH v3 18/22] isl: fix VA64 support for double and dvecN vertex attributes

a 256-bit vertex element." v2,v3 (Jason): - Don't delete unused formats. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/isl/isl_format.c | 4 ++-- src/intel/vulkan/anv_formats.c | 8 2 files changed, 6 insertions(+), 6 deletions(-) diff -

[Mesa-dev] [PATCH v3 20/22] spirv: enable SpvCapabilityFloat64 only to supported platforms

v2 (Jason): - Use nir_spirv_supported_extensions to check if the feature is enabled. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/spirv/nir_spirv.h| 1 + src/compiler/spirv/spirv_to_nir.c | 5 - 2 files changed, 5 insertions(+), 1 deletion(-)

[Mesa-dev] [PATCH v3 14/22] spirv/nir: implement DF conversions

SPIR-V does not have special opcodes for DF conversions. We need to identify them by checking the bit size of the operand and the result. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/spirv/spirv_t

[Mesa-dev] [PATCH v3 22/22] anv: enable shaderFloat64 feature

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 062fab6fabe..219c6114083 100644 --- a/src/intel/

[Mesa-dev] [PATCH v3 13/22] nir: add nir_type_conversion_op()

) Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/nir/nir.c | 81 ++ src/compiler/nir/nir.h | 2 ++ 2 files changed, 83 insertions(+) diff --git a/src/

[Mesa-dev] [PATCH v3 11/22] spirv: add support for doubles on OpComposite{Insert, Extract}

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/spirv/spirv_to_nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index

[Mesa-dev] [PATCH v3 10/22] spirv: Enable double floating points when copying variables in _vtn_variable_copy()

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index

[Mesa-dev] [PATCH v3 17/22] anv/pipeline: get map for double input attributes

From: "Juan A. Suarez Romero" Reviewed-by: Jason Ekstrand --- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 21a5a446efc..361fd256cf7 100644

[Mesa-dev] [PATCH v3 19/22] nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributes

From: "Juan A. Suarez Romero" So far, input_reads was a bitmap tracking which vertex input locations were being used. In OpenGL, an attribute bigger than a vec4 (like a dvec3 or dvec4) consumes just one location, any other small attribute. So we mark the proper bit in

[Mesa-dev] [PATCH v3 21/22] anv: enable float64 feature on supported platforms

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/intel/vulkan/anv_pipeline.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 361fd256cf7..e25465fc1d9 100644 --- a/src

[Mesa-dev] [PATCH v3 12/22] nir: add nir_get_nir_type_for_glsl_type()

v2 (Jason): - Refactor nir_get_nir_type_for_glsl_type() to avoid using unneeded helpers (Jason) Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/nir/nir.h | 27 +++ 1 file changed, 27 insertions(+) diff --git a/src/compiler/nir/n

[Mesa-dev] [PATCH v3 16/22] spirv: add support for doubles to OpSpecConstant

v2 (Jason): - Fix indent in radv change - Add vtn_u64_literal() helper to take 64 bits (Jason) Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/amd/vulkan/radv_pipeline.c| 5 - src/compiler/spirv/nir_spirv.h| 5 - src/compiler/spirv/spirv_to_nir.

[Mesa-dev] [PATCH v3 06/22] spirv: fix SpvOpSpecConstantOp with SpvOpVectorShuffle working with double-based vecs

We need to pick two 32-bit values per component to perform the right shuffle operation. v2 (Jason): - Add assert to check matching bit sizes (Jason) - Simplify the code to pick components (Jason) Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler

[Mesa-dev] [PATCH v3 04/22] spirv: add DF support to vtn_const_ssa_value()

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/spirv/spirv_to_nir.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/co

[Mesa-dev] [PATCH v3 01/22] spirv: fix typo in spec_constant_decoration_cb()

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/spirv/spirv_to_nir.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/sp

[Mesa-dev] [PATCH v3 15/22] spirv/nir: add (un)packDouble2x32() translation

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/spirv/vtn_glsl450.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index

[Mesa-dev] [PATCH v3 09/22] spirv: add double support to _vtn_block_load_store()

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index

[Mesa-dev] [PATCH v3 02/22] spirv: add definition of double based data types

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/spirv/spirv_to_nir.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/sp

[Mesa-dev] [PATCH v3 00/22] Enable Float64 capability support for Intel's Vulkan driver

A. Suarez Romero (2): anv/pipeline: get map for double input attributes nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributes Samuel Iglesias Gonsálvez (20): spirv: fix typo in spec_constant_decoration_cb() spirv: add definition of double based data types

[Mesa-dev] [PATCH v3 08/22] spirv: add double support to _vtn_variable_load_store

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index

[Mesa-dev] [PATCH v3 05/22] spirv: add DF support to SpvOp*ConstantComposite

v2 (Jason): - Add assert. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/spirv/spirv_to_nir.c | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/compiler/spirv/sp

[Mesa-dev] [PATCH v3 03/22] spirv: add support for loading DF constants

v2 (Jason): - Add assert. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/compiler/spirv/spirv_to_nir.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/sp

Re: [Mesa-dev] [PATCH v2 17/25] spirv: add support for doubles to OpSpecConstant

rand" <ja...@jlekstrand.net> wrote: > On Fri, Dec 16, 2016 at 6:49 AM, Juan A. Suarez Romero <jasuarez@igal > ia.com> wrote: > > From: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > > > Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com

Re: [Mesa-dev] [PATCH v2 23/25] spirv: enable SpvCapabilityFloat64 only to supported platforms

some patches. We will send a v3 of the patch series soon. Thanks, Sam > On Dec 16, 2016 8:56 AM, "Juan A. Suarez Romero" <jasua...@igalia.com > > wrote: > > From: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > > > Signed-off-by: Samuel

Re: [Mesa-dev] [PATCH 1/2] vec4: use DIM instruction when loading DF immediates in HSW

On Wed, 2017-01-04 at 12:36 +0100, Samuel Iglesias Gonsálvez wrote: > On Tue, 2017-01-03 at 12:14 -0500, Matt Turner wrote: > > On Tue, Jan 3, 2017 at 7:27 AM, Samuel Iglesias Gonsálvez > > <sigles...@igalia.com> wrote: > > > Signed-off-by: Samuel Iglesias G

Re: [Mesa-dev] [PATCH v2 19/25] isl: fix VA64 support for double and dvecN vertex attributes

On Tue, 2017-01-03 at 08:57 -0800, Jason Ekstrand wrote: > > > On Dec 16, 2016 8:55 AM, "Juan A. Suarez Romero" <jasua...@igalia.com > > wrote: > From: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > We use *64*_PASSTHRU formats to upload vertex a

Re: [Mesa-dev] [PATCH v2 17/25] spirv: add support for doubles to OpSpecConstant

On Tue, 2017-01-03 at 08:25 -0800, Jason Ekstrand wrote: > On Fri, Dec 16, 2016 at 6:49 AM, Juan A. Suarez Romero <jasuarez@igal > ia.com> wrote: > > From: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > > > Signed-off-by: Samuel Iglesias Gonsálvez <sig

Re: [Mesa-dev] [PATCH 1/2] vec4: use DIM instruction when loading DF immediates in HSW

On Tue, 2017-01-03 at 12:14 -0500, Matt Turner wrote: > On Tue, Jan 3, 2017 at 7:27 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: > > Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > --- > >  src/mesa/drivers/dri/i965/brw_ve

Re: [Mesa-dev] [PATCH v2 06/25] spirv: fix SpvOpSpecConstantOp with SpvOpVectorShuffle working with double-based vecs

On Mon, 2017-01-02 at 10:10 -0800, Jason Ekstrand wrote: > > > On Fri, Dec 16, 2016 at 6:48 AM, Juan A. Suarez Romero <jasuarez@igal > ia.com> wrote: > > From: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > > > We need to pick two 32-bit val

Re: [Mesa-dev] [PATCH v2 00/25] Enable Float64 capability support for Intel's Vulkan driver

://github.com/Igalia/mesa.g > > ithub > > > > Thanks, > > > >         J.A. > > > > > > > > Juan A. Suarez Romero (2): > >   anv/pipeline: get map for double input attributes > >   nir/i965: use two slots from inputs_read for dvec3/

Re: [Mesa-dev] [PATCH v2 13/25] nir: add nir_get_nir_type_for_glsl_type()

On Mon, 2017-01-02 at 10:16 -0800, Jason Ekstrand wrote: > On Fri, Dec 16, 2016 at 6:48 AM, Juan A. Suarez Romero <jasuarez@igal > ia.com> wrote: > > From: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > > > Signed-off-by: Samuel Iglesias Gonsálvez <

Re: [Mesa-dev] [PATCH v2 14/25] nir: add nir_type_conversion_op()

g to send this week for review too, although maybe we are trying to squeeze too many things for the next release :-D) What do you think? Sam [0] https://lists.freedesktop.org/archives/mesa-dev/2016-November/13701 5.html > --Jason Ekstrand > > On Fri, Dec 16, 2016 at 6:49 AM, Juan A. S

[Mesa-dev] [PATCH 1/2] vec4: use DIM instruction when loading DF immediates in HSW

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 065e317..98e023a

[Mesa-dev] [PATCH 2/2] i965/disasm: remove printing hstride and width in align16 DF source regions

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_disasm.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 6de52b3..167067a

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

Hello Matt, We have pushed all the patches except the last one... > * i965/gen7: expose OpenGL 4.0 on Haswell > >   We are currently discussing it with Curro :-) > We plan to send another patch series with the needed changes to enable OpenGL 4.0 on Haswell and all the suggestions we got from

[Mesa-dev] [PATCH] i965/fs: fix exec_size when emitting DIM instruction

Otherwise, DIM instructions will be emitted with the default exec size which could be 16 in some cases, that is not legal. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Suggested-by: Matt Turner <matts...@gmail.com> --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp |

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

On Thu, 2016-12-22 at 12:13 -0600, Matt Turner wrote: > On Tue, Dec 13, 2016 at 2:01 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: > > On Mon, 2016-12-05 at 15:21 -0800, Matt Turner wrote: > > > i965/vec4: add a helper function to create double immedi

Re: [Mesa-dev] [PATCH 4/5] ttn: handle GLSL_SAMPLER_DIM_SUBPASS_MS case

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Thu, 2016-11-24 at 13:36 +0100, Juan A. Suarez Romero wrote: > Fixes a warning. > --- >  src/gallium/auxiliary/nir/tgsi_to_nir.c | 1 + >  1 file changed, 1 insertion(+) > > diff --git a/src/gallium/auxilia

Re: [Mesa-dev] [PATCH] i965: allow unsourced enabled VAO

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Thu, 2016-11-03 at 11:02 +0100, Juan A. Suarez Romero wrote: > The GL 4.5 spec says: > "If any enabled array’s buffer binding is zero when DrawArrays > or one of the other drawing commands def

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

On Mon, 2016-12-19 at 11:31 -0600, Matt Turner wrote: > On Mon, Dec 19, 2016 at 2:00 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: > > Hello Matt, > > > > We have done most of the suggestions you made to our patches. > > However, > >

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

Hello Matt, We have done most of the suggestions you made to our patches. However, we have replied to some of your questions/suggestions and we are waiting for a reply before marking them as R-b or not. You can clone the new version of the patch series by running this command: $ git clone -b

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

On Sun, 2016-12-11 at 15:00 -0800, Matt Turner wrote: > i965/vec4: handle 32 and 64 bit channels in liveness analysis > > Please indent the returned multiline expressions in > var_from_reg() like we do elsewhere, so that the second line > begins on the same column as the first

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

On Tue, 2016-12-13 at 09:01 +0100, Samuel Iglesias Gonsálvez wrote: > [...] > > i965/vec4/nir: implement double comparisons > > > > Trivial: A newline before the if() would be nice. > > > > I have a memory of Curro telling me that the hardware maps eac

Re: [Mesa-dev] [PATCH v2 000/103] i965 Haswell ARB_gpu_shader_fp64 / OpenGL 4.0

Hello Matt! On Mon, 2016-12-05 at 15:21 -0800, Matt Turner wrote: > On 10/11, Iago Toral Quiroga wrote: > > It's been some time since > > ... anyone has reviewed your patches. Sorry. :( > > I'm going to review from your rebased i965-fp64-gen7-scalar-vec4-rc2 > branch. There have probably been

Re: [Mesa-dev] [PATCH 16/22] isl: fix VA64 support for double and dvecN vertex attributes

On Thu, 2016-12-01 at 18:58 -0800, Jason Ekstrand wrote: > On Fri, Nov 25, 2016 at 12:52 AM, Juan A. Suarez Romero <jasuarez@iga > lia.com> wrote: > > From: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > > > > > > > We use *64*_PASSTHR

Re: [Mesa-dev] [PATCH 04/22] spirv: add DF support to vtn_const_ssa_value()

@igalia.com> wrote: From: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> ---  src/compiler/spirv/spirv_to_nir.c | 24 +---  1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/

Re: [Mesa-dev] [PATCH 12/22] spirv/nir: implement DF conversions

On Thu, 2016-12-01 at 18:50 -0800, Jason Ekstrand wrote: > On Fri, Nov 25, 2016 at 12:52 AM, Juan A. Suarez Romero <jasuarez@iga > lia.com> wrote: > > From: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > > > > SPIR-V does not have special opcodes for DF

Re: [Mesa-dev] [PATCH] i965/gen7: Only advertise 4 samples for RGBA32F on GLES

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Tue, 2016-11-22 at 00:17 -0800, Jordan Justen wrote: > We can't render to 8x MSAA if the width is greater than 64 bits. (see > brw_render_target_supported) > > Fixes ES31-CTS.sample_variables.mask.rgba3

Re: [Mesa-dev] [PATCH] mesa/glsl: remove unused uses_builtin_functions field

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Tue, 2016-11-22 at 18:01 +1100, Timothy Arceri wrote: > This has been unused since 943b69cddd > --- >  src/compiler/glsl/glsl_parser_extras.cpp | 1 - >  src/mesa/main/ff_fragment_shader.cpp | 1 - >  s

Re: [Mesa-dev] [PATCH] main: return error if asking for GL_TEXTURE_BORDER_COLOR in TEXTURE_2D_MULTISAMPLE{_ARRAY} through TexParameterI{i, ui}v()

On Mon, 2016-11-14 at 20:05 -0800, Kenneth Graunke wrote: > On Monday, November 7, 2016 11:49:13 AM PST Samuel Iglesias Gonsálvez > wrote: > > OpenGL ES 3.2 says in section 8.10. "TEXTURE PARAMETERS", at the > > end of > > the section: > > > >

[Mesa-dev] [PATCH] main: return error if asking for GL_TEXTURE_BORDER_COLOR in TEXTURE_2D_MULTISAMPLE{_ARRAY} through TexParameterI{i, ui}v()

resent in that table. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98250 --- src/mesa/main/texparam.c | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c ind

Re: [Mesa-dev] [PATCH] anv: use limits.h instead of deprecated/obsolete values.h

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 03/11/16 12:49, Tapani Pälli wrote: > Mesa uses limits.h elsewhere, and this makes is possible to > compile anv_allocator.c on Android. > > Signed-off-by: Tapani Pälli <tapani.pa...@intel.com> &

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