[Mesa-dev] [PATCH] i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS

2018-06-01 Thread Anuj Phogat
CACHE_MODE_SS is not listed in gfxspecs table for user mode non-privileged registers. So, making any changes from Mesa will do nothing. Kernel is already setting this bit in CACHE_MODE_SS register which is saved/restored to/from the HW context image. Signed-off-by: Anuj Phogat Cc: Lionel Landwerl

Re: [Mesa-dev] [PATCH] i965/icl: Don't set float blend optimization bit in CACHE_MODE_SS

2018-07-03 Thread Anuj Phogat
Bump. On Fri, Jun 1, 2018 at 2:40 PM Anuj Phogat wrote: > > CACHE_MODE_SS is not listed in gfxspecs table for user mode > non-privileged registers. So, making any changes from Mesa > will do nothing. Kernel is already setting this bit in > CACHE_MODE_SS register which is saved/restored to/from > t