From: Nicolai Hähnle
When the HS wave is empty, the hardware writes the LS VGPRs starting at
v0 instead of v2. Workaround by shifting them back into place when
necessary. For simplicity, this is always done in the LS prolog.
According to the hardware team, this will be fixed in future chips,
so
Would it be possible to use this workaround only when LS vertices > HS
vertices? (which should be rare)
Marek
On Mon, Sep 4, 2017 at 8:11 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> When the HS wave is empty, the hardware writes the LS VGPRs starting at
> v0 instead of v2. Workaround b
