Re: [Mesa-dev] [PATCH 0/5] nvc0: better instruction pipelining for Maxwell GPUs

2017-01-12 Thread Samuel Pitoiset
Just pushed the series before the branchpoint. :-) If someone want to do benchmarks, make sure to use Linux 4.10 with pstate 0f. The sched control codes are enabled by default but they can be disabled by setting NV50_PROG_SCHED=0 (for comparison purposes and debugging eventually). Thanks!

Re: [Mesa-dev] [PATCH 0/5] nvc0: better instruction pipelining for Maxwell GPUs

2017-01-12 Thread Samuel Pitoiset
On 01/06/2017 03:34 AM, Alexandre Courbot wrote: On 12/23/2016 08:15 AM, Samuel Pitoiset wrote: This series makes use of the scheduling control code in order to improve the instruction pipelining on Maxwell GPUs. Tested this on Jetson TX1. The performance improvement on glmark2 was only

Re: [Mesa-dev] [PATCH 0/5] nvc0: better instruction pipelining for Maxwell GPUs

2017-01-06 Thread Samuel Pitoiset
On 01/06/2017 11:53 AM, Jan Vesely wrote: On Fri, 2016-12-23 at 00:15 +0100, Samuel Pitoiset wrote: Hello, This series makes use of the scheduling control code in order to improve the instruction pipelining on Maxwell GPUs. Starting with the Kepler architecture, where a control instruction

Re: [Mesa-dev] [PATCH 0/5] nvc0: better instruction pipelining for Maxwell GPUs

2017-01-06 Thread Jan Vesely
On Fri, 2016-12-23 at 00:15 +0100, Samuel Pitoiset wrote: > Hello, > > This series makes use of the scheduling control code in order to improve the > instruction pipelining on Maxwell GPUs. > > Starting with the Kepler architecture, where a control instruction has to be > inserted every 7

Re: [Mesa-dev] [PATCH 0/5] nvc0: better instruction pipelining for Maxwell GPUs

2017-01-06 Thread Samuel Pitoiset
On 01/06/2017 03:34 AM, Alexandre Courbot wrote: On 12/23/2016 08:15 AM, Samuel Pitoiset wrote: This series makes use of the scheduling control code in order to improve the instruction pipelining on Maxwell GPUs. Tested this on Jetson TX1. The performance improvement on glmark2 was only

Re: [Mesa-dev] [PATCH 0/5] nvc0: better instruction pipelining for Maxwell GPUs

2017-01-05 Thread Alexandre Courbot
On 12/23/2016 08:15 AM, Samuel Pitoiset wrote: > This series makes use of the scheduling control code in order to improve the > instruction pipelining on Maxwell GPUs. Tested this on Jetson TX1. The performance improvement on glmark2 was only marginal, with terrain going from 7 to 10 fps at

Re: [Mesa-dev] [PATCH 0/5] nvc0: better instruction pipelining for Maxwell GPUs

2016-12-23 Thread Mike Lothian
Thanks for all your work on Nouveau and I look forward to your contributions to radeonsi On Thu, 22 Dec 2016 at 23:16 Samuel Pitoiset wrote: > Hello, > > This series makes use of the scheduling control code in order to improve > the > instruction pipelining on Maxwell

[Mesa-dev] [PATCH 0/5] nvc0: better instruction pipelining for Maxwell GPUs

2016-12-22 Thread Samuel Pitoiset
Hello, This series makes use of the scheduling control code in order to improve the instruction pipelining on Maxwell GPUs. Starting with the Kepler architecture, where a control instruction has to be inserted every 7 instructions, Maxwell added additional control codes and the control