[Mesa-dev] [PATCH 2/3] radv: Add create image flag to not use DCC/CMASK.

If we import an image, we might not have space in the buffer for CMASK, even though it is compatible. --- src/amd/vulkan/radv_image.c | 43 --- src/amd/vulkan/radv_private.h | 1 + 2 files changed, 25 insertions(+), 19 deletions(-) diff --git a/src/amd/v

[Mesa-dev] [PATCH 3/3] radv: Implement VK_ANDROID_native_buffer.

Passes dEQP-VK.api.smoke.* dEQP-VK.wsi.android.* with android-cts-7.1_r12 . Unlike the initial anv implementation this does use syncobjs instead of waiting on the CPU. This is missing meson build coverage for now. One possible todo is that linux 4.15 now has a sycall that allows us to expor

Re: [Mesa-dev] [PATCH] radv: enable denorms for 64-bit and 16-bit floats

Reviewed-by: Bas Nieuwenhuizen On Thu, Dec 28, 2017 at 10:55 PM, Samuel Pitoiset wrote: > Similar to RadeonSI. > > This fixes: > dEQP-VK.image.texel_view_compatible.graphic.basic.attachment_read.bc*r16g16b16a16_sfloat > dEQP-VK.image.extended_usage_bit.attachment_write.r16_sfloat

Re: [Mesa-dev] [PATCH] radv: remove unused radv_color_buffer_info::cb_clear_valueX

Reviewed-by: Bas nieuwenhuizen On Fri, Jan 5, 2018 at 10:03 AM, Samuel Pitoiset wrote: > Found by inspection. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_private.h | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/src/amd/vulkan/radv_pr

Re: [Mesa-dev] [PATCH 2/2] radv: avoid PS partial flushes when viewports/scissors don't change

Reviewed-by: Bas Nieuwenhuizen for the series. On Fri, Jan 5, 2018 at 6:26 PM, Samuel Pitoiset wrote: > For Vega10 and Raven that need a special workaround for the > scissor bug. > > This seems to give a minor boost for Talos and Dota 2, at least. > > To reduce the cost of

Re: [Mesa-dev] [PATCH 6/6] radv: make shader BOs read-only for the GPU

Reviewed-by: Bas Nieuwenhuizen for the series. On Thu, Jan 4, 2018 at 6:39 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_device.c | 2 ++ > src/amd/vulkan/radv_private.h | 1 + > src/amd/vulkan/radv_shader.c | 5 - >

Re: [Mesa-dev] [PATCH] radv/gfx9: do not load VGPR1 when GS uses points or lines

Reviewed-by: Bas Nieuwenhuizen On Fri, Jan 5, 2018 at 5:26 PM, Samuel Pitoiset wrote: > VGPR1 is only needed for topology that needs 3 offsets like > triangles or quads. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_shader.c | 4 +++- > 1 file change

[Mesa-dev] [PATCH 1/2] vulkan: move anv VK_EXT_debug_report implementation to common code.

For also using it in radv. I moved the remaining stubs back to anv_device.c as they were just trivial. This does not move the vk_errorf/anv_perf_warn or the object type macros, as those depend on anv types and logging. --- src/intel/Makefile.sources | 1 - src/intel/vulka

[Mesa-dev] [PATCH 2/2] radv: Implement VK_EXT_debug_report.

This is not hooked up to any messages yet, but useful for e.g. renderdoc if you add some messages during development. --- src/amd/vulkan/radv_device.c | 46 +++ src/amd/vulkan/radv_extensions.py | 1 + src/amd/vulkan/radv_private.h | 3 +++ 3 files ch

Re: [Mesa-dev] [PATCH 3/3] radv/gfx9: calculate the number of ES VGPRs for merged shaders

Reviewed-by: Bas Nieuwenhuizen for the series. On Tue, Jan 9, 2018 at 4:01 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_shader.c | 13 ++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/src/amd/vulk

Re: [Mesa-dev] [PATCH 1/2] amd/common: do not rely on the pipeline for the push constants logic

Reviewed-by: Bas Nieuwenhuizen for the series. On Tue, Jan 9, 2018 at 6:09 PM, Samuel Pitoiset wrote: > It makes more sense to rely on nir_intrinsic_load_push_constant > instead of the pipeline layout. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/common/ac_

[Mesa-dev] [PATCH 1/2] radv: Add mapping between dynamic state mask and external enum.

The EXT values are really large, e.g. VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT = 199000, so 1 << value is not going to fit into a 32-bit mask. --- src/amd/vulkan/radv_cmd_buffer.c | 36 ++--- src/amd/vulkan/radv_pipeline.c | 49 +++-

[Mesa-dev] [PATCH 2/2] radv: Implement VK_EXT_discard_rectangles.

Tested with a modified deferred demo and no regressions in a 1.0.2 mustpass run. --- src/amd/vulkan/radv_cmd_buffer.c | 51 +++ src/amd/vulkan/radv_device.c | 6 + src/amd/vulkan/radv_extensions.py | 1 + src/amd/vulkan/radv_pipeline.c| 35 ++

Re: [Mesa-dev] [PATCH] amd/common: bump the number of available user SGPRS to 32 on GFX9

Reviewed-by: Bas Nieuwenhuizen On Mon, Jan 8, 2018 at 3:21 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/common/ac_nir_to_llvm.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/src/amd/common/ac_nir_to_llvm.

Re: [Mesa-dev] [PATCH 2/2] radv: Implement VK_EXT_discard_rectangles.

On Wed, Jan 10, 2018 at 11:16 AM, Samuel Pitoiset wrote: > > > On 01/10/2018 03:34 AM, Bas Nieuwenhuizen wrote: >> >> Tested with a modified deferred demo and no regressions in a 1.0.2 >> mustpass run. >> --- >>

[Mesa-dev] [PATCH] ac/nir: Sanitize location_frac for local variables.

If they were promoted from inputs/outputs, they could have a non-zero value left over, which messed with our store handling. Fixes: 06f05040eb "radv: Link shaders." --- src/amd/common/ac_nir_to_llvm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/co

Re: [Mesa-dev] [PATCH] radv: don't emit unneeded vertex state.

Reviewed-by: Bas Nieuwenhuizen On Wed, Jan 10, 2018 at 11:14 PM, Dave Airlie wrote: > From: Dave Airlie > > If the number of instances hasn't changed and we've already > emitted it, don't emit it again. > > If the vertex shader is the same and the first_

Re: [Mesa-dev] [PATCH 2/2] radv: Implement VK_EXT_discard_rectangles.

Am I right? > IIRC, It is not a right interpretation. > Where did you read the register spec? I would like to take a look. > Thanks. > > Best Regards, > David > > > -Original Message- > From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On Behalf O

Re: [Mesa-dev] [PATCH 2/2] radv: Implement VK_EXT_discard_rectangles.

; Am I right? > IIRC, It is not a right interpretation. > Where did you read the register spec? I would like to take a look. > Thanks. > > Best Regards, > David > > > -Original Message- > From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On Behalf

[Mesa-dev] [PATCH] radv: Initialize DCC on transition from preinitialized.

Looks like the decompress does not handle invalid encodings well, which happens with random memory. Of course apps should not use it with random memory, but they are allowed to Fixes: 44fcf58744 "radv: Disable DCC for GENERAL layout and compute transfer dest." --- src/amd/vulkan/radv_cmd_bu

Re: [Mesa-dev] [PATCH 2/2] radv: Implement VK_EXT_discard_rectangles.

er defines the flag for all combinations of four rectangles > that pixel could be finally determined as inside. > > Thanks. > Best Regards, > David > > -Original Message- > From: Bas Nieuwenhuizen [mailto:b...@basnieuwenhuizen.nl] > Sent: Thursday, January 11, 2018 5

Re: [Mesa-dev] [PATCH 2/2] radv/winsys: skip padded empty buffers in chain.

On Thu, Jan 11, 2018 at 5:56 AM, Dave Airlie wrote: > From: Dave Airlie > > When chaining buffers if we see an empty one (just padded) > skip over it. > --- > src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 19 +++ > 1 file changed, 15 insertions(+), 4 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH 3/3] ac: add 'const' qualifiers to the shader info pass

Reviewed-by: Bas Nieuwenhuizen for the series On Thu, Jan 11, 2018 at 10:07 PM, Samuel Pitoiset wrote: > For clarification purposes. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/common/ac_shader_info.c | 17 ++--- > src/amd/common/ac_shader_info.h | 2 +-

Re: [Mesa-dev] [PATCH] amd/common: fix loading InstanceID for tess on < GFX9

t; - shaders[shader_count - 1]->info.stage >> == MESA_SHADER_TESS_CTRL) { >> + if (ctx.options->key.vs.as_ls || >> + (ctx.ac.chip_class == GFX9 && >> +

Re: [Mesa-dev] [PATCH] radv/radeonsi/nir: lower 64bit flrp

Reviewed-by: Bas Nieuwenhuizen On Fri, Jan 12, 2018 at 1:13 AM, Timothy Arceri wrote: > Fixes a bunch of arb_gpu_shader_fp64 piglit tests for example: > > generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-mix-double-double-double.shader_test > --- >

Re: [Mesa-dev] [PATCH 2/2] ac/nir: fix translation of nir_op_b2i for doubles

Maybe just zero-extend the 32-bit value? (or truncate for 16-bit?) I don't know what generates better machinecode. On Fri, Jan 12, 2018 at 2:34 AM, Timothy Arceri wrote: > --- > > Open to suggestions for better ways to do this. > > src/amd/common/ac_nir_to_llvm.c | 13 ++--- > 1 file ch

Re: [Mesa-dev] [PATCH] ac: fix build error in si_shader

else if (ctx->type == PIPE_SHADER_TESS_EVAL) > return get_num_tcs_out_vertices(ctx); > else > - assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN"); > + unreachable(!"invalid shader stage for > TGSI_SEMANT

Re: [Mesa-dev] [PATCH v2] ac/nir: fix translation of nir_op_b2i for doubles

Reviewed-by: Bas Nieuwenhuizen On Sat, Jan 13, 2018 at 11:52 PM, Timothy Arceri wrote: > V2: just zero-extend the 32-bit value. > > Fixes a number of int64 piglet tests, for example: > > generated_tests/spec/arb_gpu_shader_int64/execution/conversion/frag-conversio

Re: [Mesa-dev] [PATCH 2/2] ac: add doubles support to isign

Reviewed-by: Bas Nieuwenhuizen for the series. On Sun, Jan 14, 2018 at 12:09 AM, Timothy Arceri wrote: > Fixes a number of int64 piglit tests, for example: > > generated_tests/spec/arb_gpu_shader_int64/execution/built-in-functions/fs-sign-i64vec2.shader_test > --- >

[Mesa-dev] [PATCH 2/2] radv: Use the CS bo for other uploads too.

If an app keeps building and resetting the command buffers, most command buffers will have 1 CS bo and 1 upload bo. This merges them by allocating uploads from the end of the CS bo. On dota2, this goes from ~700 to ~400 BOs after the merging in the create_bo_list. Sadly no discernible performance

[Mesa-dev] [PATCH 1/2] radv: Add bo argument to upload functions.

--- src/amd/vulkan/radv_cmd_buffer.c | 37 +++-- src/amd/vulkan/radv_meta_buffer.c | 5 +++-- src/amd/vulkan/radv_private.h | 6 -- src/amd/vulkan/si_cmd_buffer.c| 5 +++-- 4 files changed, 33 insertions(+), 20 deletions(-) diff --git a/src/amd/vulk

[Mesa-dev] [PATCH 07/23] radv: Constify some pipeline helpers.

--- src/amd/vulkan/radv_pipeline.c | 8 src/amd/vulkan/radv_private.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 22dd6566a1..1eddacfe51 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/sr

[Mesa-dev] [PATCH 08/23] radv: Merge binning state generation with pm4 emission.

We don't need the pipeline state struct anymore. --- src/amd/vulkan/radv_pipeline.c | 48 +- src/amd/vulkan/radv_private.h | 6 -- 2 files changed, 19 insertions(+), 35 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pip

[Mesa-dev] [PATCH 12/23] radv: Merge depth stencil state with PM4 generation.

--- src/amd/vulkan/radv_pipeline.c | 117 +++-- src/amd/vulkan/radv_private.h | 8 --- 2 files changed, 55 insertions(+), 70 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 8c5706f4b4..dbe33d3cc5 100644 --- a/s

[Mesa-dev] [PATCH 05/23] radv: Record a PM4 sequence for graphics pipeline switches.

This gives about 2% performance improvement on dota2 for me. This is mostly a mechanical copy and replacement, but at bind time we still do: 1) Some stuff that is only based on num_samples changes. 2) Some command buffer state setting. --- src/amd/vulkan/radv_cmd_buffer.c | 458 +

[Mesa-dev] [PATCH 02/23] radv: Always re-emit the sample position offset user SGPR.

The user SGPR location can change between pipelines, so we need to emit it again to the pottentially changed SGPR index. --- src/amd/vulkan/radv_cmd_buffer.c | 34 +- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/

[Mesa-dev] [PATCH 15/23] radv: Split out the ia_multi_vgt_param precomputation.

Also moved everything in a struct and then return the struct from the helper function, so it is clear in the caller what part of the pipeline gets modified. --- src/amd/vulkan/radv_pipeline.c | 169 ++--- src/amd/vulkan/radv_private.h | 16 ++-- src/amd/vulkan

[Mesa-dev] [PATCH 00/23] Rework pipeline emitting.

hould not be functional changes. I found no regressions on a CTS run on GFX9, and you can find a branch at https://github.com/BNieuwenhuizen/mesa/tree/pipeline-optimize Bas Nieuwenhuizen (23): radv: emit pa_sc_mode_cntl_0 with multisample state. radv: Always re-emit the sample position offset

[Mesa-dev] [PATCH 03/23] radv: Determine unneeded dynamic states.

Which avoids setting or emitting them. --- src/amd/vulkan/radv_cmd_buffer.c | 40 +++-- src/amd/vulkan/radv_pipeline.c | 64 +--- src/amd/vulkan/radv_private.h| 1 + 3 files changed, 65 insertions(+), 40 deletions(-) diff --git a/src/

[Mesa-dev] [PATCH 04/23] radv: Add a PM4 sequence data structure + utils.

--- src/amd/vulkan/radv_pipeline.c | 66 ++ src/amd/vulkan/radv_private.h | 19 2 files changed, 85 insertions(+) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 82d9546cc3..ffd5aab7f9 100644 --- a/src/amd/vu

[Mesa-dev] [PATCH 14/23] radv: Split out db_shader_control computation.

--- src/amd/vulkan/radv_pipeline.c | 43 +- src/amd/vulkan/radv_private.h | 1 - 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index b39ee4308b..be71abd858 100644 --- a/src/

[Mesa-dev] [PATCH 06/23] radv: Add PM4 pregeneration for compute pipelines.

--- src/amd/vulkan/radv_cmd_buffer.c | 60 ++-- src/amd/vulkan/radv_pipeline.c | 66 2 files changed, 68 insertions(+), 58 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index

[Mesa-dev] [PATCH 16/23] radv: Split out generating VGT_SHADER_STAGES_EN.

--- src/amd/vulkan/radv_pipeline.c | 50 +++--- src/amd/vulkan/radv_private.h | 1 - 2 files changed, 27 insertions(+), 24 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 9d6663e977..16dad89f4c 100644 --- a/src/

[Mesa-dev] [PATCH 13/23] radv: Compute shader_z_format when emitting it.

--- src/amd/vulkan/radv_pipeline.c | 10 +++--- src/amd/vulkan/radv_private.h | 1 - 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index dbe33d3cc5..b39ee4308b 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/s

[Mesa-dev] [PATCH 18/23] radv: Move tessellation state out of pipeline.

--- src/amd/vulkan/radv_pipeline.c | 95 ++ src/amd/vulkan/radv_private.h | 13 -- 2 files changed, 58 insertions(+), 50 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 9d95073260..cc88a7b10e 100644 --- a

[Mesa-dev] [PATCH 19/23] radv: Split out processing the vertex input state.

--- src/amd/vulkan/radv_pipeline.c | 78 +++--- 1 file changed, 43 insertions(+), 35 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index cc88a7b10e..4357669baa 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd

[Mesa-dev] [PATCH 10/23] radv: Merge vtx_reuse_depth computation with PM4 generation.

--- src/amd/vulkan/radv_pipeline.c | 13 ++--- src/amd/vulkan/radv_private.h | 1 - 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 2f4561d1c2..bd8a2feb8c 100644 --- a/src/amd/vulkan/radv_pipeline.c +++

[Mesa-dev] [PATCH 21/23] radv: Split out cliprect rule generation.

--- src/amd/vulkan/radv_pipeline.c | 57 -- src/amd/vulkan/radv_private.h | 1 - 2 files changed, 33 insertions(+), 25 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index a5239e7a6d..639eb032bb 100644 --- a/src/

[Mesa-dev] [PATCH 22/23] radv: Move gs state out of pipeline.

--- src/amd/vulkan/radv_pipeline.c | 78 +++--- src/amd/vulkan/radv_private.h | 8 - 2 files changed, 43 insertions(+), 43 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 639eb032bb..e1d6fe159d 100644 --- a/

[Mesa-dev] [PATCH 11/23] radv: Merge ps_input_cntl computation with PM4 generation.

--- src/amd/vulkan/radv_pipeline.c | 160 - src/amd/vulkan/radv_private.h | 2 - 2 files changed, 79 insertions(+), 83 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index bd8a2feb8c..8c5706f4b4 100644 --- a/src

[Mesa-dev] [PATCH 20/23] radv: Merge VGT_GS_MODE computation with PM4 generation.

--- src/amd/vulkan/radv_pipeline.c | 51 +- src/amd/vulkan/radv_private.h | 2 -- 2 files changed, 25 insertions(+), 28 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 4357669baa..a5239e7a6d 100644 --- a/src

[Mesa-dev] [PATCH 01/23] radv: emit pa_sc_mode_cntl_0 with multisample state.

We don't have the meta kludge with 0 viewports anymore, so we can always enable them. --- src/amd/vulkan/radv_cmd_buffer.c | 4 ++-- src/amd/vulkan/radv_pipeline.c | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_b

[Mesa-dev] [PATCH 09/23] radv: Merge vs state computation with PM4 generation.

--- src/amd/vulkan/radv_pipeline.c | 83 +- src/amd/vulkan/radv_private.h | 8 2 files changed, 34 insertions(+), 57 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 9b557f9c23..2f4561d1c2 100644 --- a/s

[Mesa-dev] [PATCH 17/23] radv: Move blend state out of pipeline.

--- src/amd/vulkan/radv_pipeline.c | 130 +++-- src/amd/vulkan/radv_private.h | 12 2 files changed, 73 insertions(+), 69 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 16dad89f4c..9d95073260 100644 --- a/

[Mesa-dev] [PATCH 23/23] radv: Merge raster state with PM4 generation.

--- src/amd/vulkan/radv_pipeline.c | 115 ++--- src/amd/vulkan/radv_private.h | 10 2 files changed, 50 insertions(+), 75 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index e1d6fe159d..232c06c9a8 100644 --- a/

Re: [Mesa-dev] [PATCH 04/23] radv: Add a PM4 sequence data structure + utils.

onsi and radv). > > > On 01/17/2018 02:34 AM, Bas Nieuwenhuizen wrote: >> >> --- >> src/amd/vulkan/radv_pipeline.c | 66 >> ++ >> src/amd/vulkan/radv_private.h | 19 >> 2 files changed, 85 insertions

Re: [Mesa-dev] [PATCH 1/2] ac: avoid infinite loop storing doubles to ssbo

On Wed, Jan 17, 2018 at 10:47 AM, Timothy Arceri wrote: > Without this count will always be greater than 4 and we will always > set the writemask so the loop can never exit. > > Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores." > --- > src/amd/common/ac_nir_to_llvm.c | 1 + > 1 file c

Re: [Mesa-dev] [PATCH 2/2] ac: set count correctly when storing doubles to ssbo

Why would this not work for dvec3? That is 6 elements, the intention when writing this code was to do a 4 32-bit component store (hence count=4), and then a 2 32-bit component store afterwards. The only reason this apparently fails now is because we update the writemask wrong here (intepret it as 6

[Mesa-dev] [PATCH 2/2] ac/nir: Fix vector extraction if source vector has >4 elements.

Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores." --- src/amd/common/ac_nir_to_llvm.c | 46 +++-- 1 file changed, 31 insertions(+), 15 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 12f7772a5c..5132

[Mesa-dev] [PATCH 1/2] ac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.

Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores." --- src/amd/common/ac_nir_to_llvm.c | 22 +- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 337dfdb5ec..12f7772a5c 100644 --- a/

Re: [Mesa-dev] [PATCH 1/2] ac: avoid infinite loop storing doubles to ssbo

I put some alternative fixes together that make the test pass: https://patchwork.freedesktop.org/series/36612/ On Wed, Jan 17, 2018 at 1:32 PM, Timothy Arceri wrote: > > > On 17/01/18 22:36, Bas Nieuwenhuizen wrote: >> >> On Wed, Jan 17, 2018 at 10:47 AM, Tim

[Mesa-dev] [PATCH 1/2] radv: Remove DCC check on CS resolve dst image.

Gives a warning when the assert is disabled, and not even necessarily true. --- src/amd/vulkan/radv_meta_resolve_cs.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c index 7c569aa920..5b3bc89832 100644 --- a/src/a

[Mesa-dev] [PATCH 2/2] radv: Replace an assert with unreachable.

Otherwise we get uninitialized variable warnings for es_vgpr_comp_cnt. --- src/amd/vulkan/radv_shader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 9819a522d7..3bcaac168a 100644 --- a/src/amd/vulkan/radv_shad

Re: [Mesa-dev] [PATCH] ac: fix buffer overflow bug in 64bit SSBO loads

On Tue, Jan 16, 2018 at 7:45 AM, Timothy Arceri wrote: > Fixes: 441ee1e65b04 "radv/ac: Implement Float64 SSBO loads" > --- > src/amd/common/ac_nir_to_llvm.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm

Re: [Mesa-dev] [PATCH] ac: fix buffer overflow bug in 64bit SSBO loads

On Thu, Jan 18, 2018 at 1:46 AM, Timothy Arceri wrote: > > > On 18/01/18 11:35, Bas Nieuwenhuizen wrote: >> >> On Tue, Jan 16, 2018 at 7:45 AM, Timothy Arceri >> wrote: >>> >>> Fixes: 441ee1e65b04 "radv/ac: Implement Float64 SSBO loads&

[Mesa-dev] [PATCH v2 2/2] ac/nir: Fix vector extraction if source vector has >4 elements.

v2: Add forgotten argument and start offset. Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores." --- src/amd/common/ac_nir_to_llvm.c | 48 +++-- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/

[Mesa-dev] [PATCH v2 1/2] ac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.

Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores." --- src/amd/common/ac_nir_to_llvm.c | 22 +- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 337dfdb5ec..12f7772a5c 100644 --- a/

Re: [Mesa-dev] [PATCH 1/2] radv: precalculate some vertex info in the binding. (v2)

On Thu, Jan 18, 2018 at 3:04 AM, Dave Airlie wrote: > From: Dave Airlie > > This just moves some calcs from the emission to the binding. > > Probably won't affect much, just reduced some time spent in binding > > v2: Precalculate size as well, to avoid accessing ->buffer > at all in the hw writes

Re: [Mesa-dev] [PATCH 2/2] radv/winsys: skip padded empty buffers in chain. (v2)

ol radv_amdgpu_cs_finalize(struct > radeon_winsys_cs *_cs) > struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs); > > if (cs->ws->use_ib_bos) { > + > + if (cs->empty_padded && cs->base.cdw == 0) > + cs->empty_padded = true; Thi

Re: [Mesa-dev] [PATCH] ac/nir: account for view index in the user sgpr allocation.

Reviewed-by: Bas Nieuwenhuizen On Thu, Jan 18, 2018 at 3:37 AM, Dave Airlie wrote: > From: Dave Airlie > > The view index user sgpr wasn't being accounted for properly, > this refactors out the code to decide if it's required and then > uses that info to account for

Re: [Mesa-dev] [PATCH v2] ac: fix visit_ssa_undef() for doubles

Reviewed-by: Bas Nieuwenhuizen On Thu, Jan 18, 2018 at 2:15 AM, Timothy Arceri wrote: > V2: use LLVMIntTypeInContext() > > Fixes: f4e499ec7914 "radv: add initial non-conformant radv vulkan driver" > --- > src/amd/common/ac_nir_to_llvm.c | 5 +++-- > 1 file changed,

[Mesa-dev] [PATCH] radv: Use correct bindings for inputRate in key generation.

The bindings also have an index field. Fixes: 49d035122e "radv: Add single pipeline cache key." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104677 --- src/amd/vulkan/radv_pipeline.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline.

[Mesa-dev] [PATCH] ac/nir: Fix TCS output LDS offsets.

When a channel was not set we also did not increase the LDS address, while that obviously should happen. The output loading code was inadvertently fixed which resulted in a mismatch causing the SaschaWillems tessellation demo to result in corrupt rendering. Fixes: 7898eb9a60 "ac: rework load_tcs_

Re: [Mesa-dev] [AppVeyor] mesa master #6655 failed

t; > Commit 61a790409e by Bas Nieuwenhuizen on 1/16/2018 1:08 AM: > radv: Always re-emit the sample position offset user SGPR.\n\nThe user SGPR > location can change between pipelines, so we need to\nemit it again to the > pottentially changed SGPR index.\n\nReviewed-by: Samuel Pitoise

[Mesa-dev] [PATCH] radv: Don't redundantly emit pipelines after secondary cmd buffer.

--- src/amd/vulkan/radv_cmd_buffer.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 068247d04d4..5da866ca64e 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer

[Mesa-dev] [PATCH] radv: Also fix up 1D images in the image_size intrinsic.

Forgotten when implementing them using 2D textures. This fixes: dEQP-VK.image.image_size.1d_array.readonly_12x34 dEQP-VK.image.image_size.1d_array.readonly_1x1 dEQP-VK.image.image_size.1d_array.readonly_32x32 dEQP-VK.image.image_size.1d_array.readonly_7x1 dEQP-VK.image.image_size.1d_array.readonly

[Mesa-dev] [PATCH] radv: Check for GFX9 for 1D arrays in image_size intrinsic.

Only on GFX9 we implement them as 2D images. This fixes: dEQP-VK.image.image_size.1d_array.readonly_12x34 dEQP-VK.image.image_size.1d_array.readonly_1x1 dEQP-VK.image.image_size.1d_array.readonly_32x32 dEQP-VK.image.image_size.1d_array.readonly_7x1 dEQP-VK.image.image_size.1d_array.readonly_writeo

Re: [Mesa-dev] [PATCH] radv: Also fix up 1D images in the image_size intrinsic.

Okay, this patch was just nonsense. Superseded by https://patchwork.freedesktop.org/patch/177162/ On Fri, Sep 15, 2017 at 9:24 PM, Bas Nieuwenhuizen wrote: > Forgotten when implementing them using 2D textures. > > This fixes: > dEQP-VK.image.image_size.1d_array.readonly_

Re: [Mesa-dev] Vulkan extensions

On Fri, Sep 15, 2017 at 1:31 AM, Romain Failliot wrote: > 2017-09-14 19:19 GMT-04:00 Bas Nieuwenhuizen : >> >> Also you can implement 0% of the feature list and still be vulkan 1.0 >> compliant ;) > > > Oh... is that so? > Thanks for all your answers, I apparen

[Mesa-dev] [PATCH 1/2] radv: Add code to check if two formats can share DCC metadata.

Ported from radeonsi. --- src/amd/vulkan/radv_formats.c | 85 +++ src/amd/vulkan/radv_private.h | 2 + 2 files changed, 87 insertions(+) diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c index c19a9a37a49..24445412813 100644 --- a/

[Mesa-dev] [PATCH 2/2] radv: Add support for more DCC compression with VK_KHR_image_format_list.

--- src/amd/vulkan/radv_device.c | 4 src/amd/vulkan/radv_image.c | 24 +--- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index c112453e395..e6d595dfbe5 100644 --- a/src/amd/vulkan/radv_device

[Mesa-dev] [PATCH 3/3] radv: Don't use a virtual function for getting the buffer virtual address.

We are really not going to use a winsys which does not need to store the va, so might as well store it in a standard field. Not sure this helps perf much though, as most of the cost is in the cache miss accessing the bo anyway, which we stil need to do. --- src/amd/vulkan/radv_cmd_buffer.c

[Mesa-dev] [PATCH 1/3] radv: Use for_each_bit in the descriptor set flush.

Since most games use only a few, iterating through all of them is a waste. Simplifies the code too. --- src/amd/vulkan/radv_cmd_buffer.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 4ba552ebcbc..e0a

[Mesa-dev] [PATCH 2/3] radv: Only enter the immutable samplers init loop when we have some.

--- src/amd/vulkan/radv_descriptor_set.c | 28 src/amd/vulkan/radv_descriptor_set.h | 2 ++ 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index 314ab5a96d0..5b9cfe66331 100

[Mesa-dev] [PATCH] radv: Add VK_KHR_bind_memory2 support.

Nothing too exciting, just adding the possibility for a pNext pointer, and batch binding. Our binding is pretty much trivial. It also adds VK_IMAGE_CREATE_ALIAS_BIT_KHR, but since we store no state in radv_image, I don't think we have to do anything there. --- src/amd/vulkan/radv_device.c

Re: [Mesa-dev] [PATCH] radv: Implement VK_AMD_rasterization_order

Pushed, thanks. On Mon, Sep 18, 2017 at 6:26 PM, Nicholas Miell wrote: > Tested with AMD's Anvil OutOfOrderRasterization demo on a RX 560. > > Signed-off-by: Nicholas Miell > --- > src/amd/vulkan/radv_device.c | 17 + > src/amd/vulkan/radv_pipeline.c | 10 +- > 2 files

Re: [Mesa-dev] [PATCH] radv: init the trace BO before compiling meta shaders

r-b On Fri, Sep 22, 2017 at 6:16 AM, Samuel Pitoiset wrote: > Otherwise, the disasm string is NULL for meta shaders. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_device.c | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/src/amd/vulkan/radv_de

Re: [Mesa-dev] [PATCH 1/3] radv: make use of ATI_VENDOR_ID everywhere

Reviewed-by: Bas Nieuwenhuizen for the series. On Fri, Sep 22, 2017 at 9:21 AM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_device.c | 4 ++-- > src/amd/vulkan/radv_image.c | 2 +- > src/amd/vulkan/radv_pipeline_cache.c

Re: [Mesa-dev] [PATCH v2 4/4] meson: build "radv" vulkan driver for radeon hardware

Hi Dylan, Awesome work. I noticed though that when llvm-config gives 6.0.0svn we don't strip the svn away when passing to HAVE_LLVM and MESA_LLVM_VERSION_PATCH, which results in compile errors. - Bas On Sun, Sep 24, 2017 at 12:08 AM, Dylan Baker wrote: > I have tested this, and as of v2 it actu

[Mesa-dev] [PATCH] Revert "Revert "radv: fallback to an in-memory cache when no pipline cache is provided""

I tested this 10 times with ./deqp-vk --deqp-case=dEQP-VK.texture.filtering.3d.formats.r4g4b4a4* and one full run of CTS, seems the issue is gone. Also reduces CTS runtime by 30% or so. --- src/amd/vulkan/radv_pipeline.c | 13 - src/amd/vulkan/radv_pipeline_cache.c | 7 +--

[Mesa-dev] [PATCH] radv: Fix VK_KHR_image_format_list.

Spec adding corner cases ... Fixes: 969537d9358 "radv: Add support for more DCC compression with VK_KHR_image_format_list." --- src/amd/vulkan/radv_image.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index cff1b

Re: [Mesa-dev] [PATCH v2 4/4] meson: build "radv" vulkan driver for radeon hardware

0svn-r313497.so llvm-libs-svn /usr/lib/libLLVM-6.0svn.so llvm-libs-svn /usr/lib/libLLVM.so.6.0.0svn-r313497 - Bas > > Dylan > > Quoting Bas Nieuwenhuizen (2017-09-23 21:16:36) >> Hi Dylan, >> >> Awesome work. I noticed though that when llvm-config gives 6.0.0svn w

Re: [Mesa-dev] [PATCH 1/2] radv: remove useless radv_meta_{begin, end}_XXX() helpers

For the series: Reviewed-by: Bas Nieuwenhuizen On Tue, Sep 26, 2017 at 2:26 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_meta.h | 12 --- > src/amd/vulkan/radv_meta_bufimage.c | 42 > -

Re: [Mesa-dev] [PATCH] radv: fix saved compute state when doing statistics/occlusion queries

Reviewed-by: Bas Nieuwenhuizen On Tue, Sep 26, 2017 at 7:52 AM, Samuel Pitoiset wrote: > We are pushing 16-bytes of constants, so we have to save/restore > the same amount of data to avoid data corruption. > > Signed-off-by: Samuel Pitoiset > Cc: 17.2 > --- > src/amd/vu

Re: [Mesa-dev] [PATCH v4 4/4] meson: build "radv" vulkan driver for radeon hardware

It works now, thanks! Also Reviewed-by: Bas Nieuwenhuizen for this patch. On Tue, Sep 26, 2017 at 4:38 PM, Dylan Baker wrote: > This builds, installs, and has been tested on a r290x (Hawaii) with the Vulkan > CTS. It dies horribly in a fire at the same point for the meson build

Re: [Mesa-dev] [PATCH] radv: set image view type when decompressing depth surfaces

Reviewed-by: Bas Nieuwenhuizen On Wed, Sep 27, 2017 at 2:09 PM, Samuel Pitoiset wrote: > This was missing. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_meta_decompress.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/amd/vulkan/radv_me

Re: [Mesa-dev] [PATCH 02/19] radv: do not allocate CMASK for unsupported 128 bit formats

Do we know if this does not have any improvement for 128 bit MSAA, even without fast clear? On Fri, Sep 29, 2017 at 5:48 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_image.c | 3 ++- > src/amd/vulkan/radv_meta_clear.c | 5 - > 2 files changed,

[Mesa-dev] [PATCH] radv: Check for GFX9 for 1D arrays in image_size intrinsic.

Only on GFX9 we implement them as 2D images. This fixes: dEQP-VK.image.image_size.1d_array.readonly_12x34 dEQP-VK.image.image_size.1d_array.readonly_1x1 dEQP-VK.image.image_size.1d_array.readonly_32x32 dEQP-VK.image.image_size.1d_array.readonly_7x1 dEQP-VK.image.image_size.1d_array.readonly_writeo

Re: [Mesa-dev] Mesa 17.2.2 release candidate

> > Rejected (3) > ==== > > Bas Nieuwenhuizen (1): > radv: Check for GFX9 for 1D arrays in image_size intrinsic. > Addresses earlier commits 61ad2f13 and 6dcc54b4 which did not > land in branch Hi, can we still get this in? This addresses a regre

Re: [Mesa-dev] [PATCH 01/19] radv: skip the decompression color pass when CMASK/FMASK/DCC are disabled

Why add this? It sounds like extra code for no reason? On Fri, Sep 29, 2017 at 5:48 PM, Samuel Pitoiset wrote: > This should be a no-op. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_meta_fast_clear.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/src/amd/vulkan/ra

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