When fetching texels from a multisample surface, the sample index is
provided as an extra argument after the lod, and the actual lod needs
to be hardwired to 0.
The frontend gives us the sample index in the lod parameter, so fix this
up.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa
When fetching texels from a multisample surface, the sample index is
provided as an extra argument after the lod, and the actual lod needs
to be hardwired to 0.
The frontend gives us the sample index in the lod parameter, so fix this
up.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa
There are a few things that need to be done to support Gen7+ as well,
but I don't have a machine available to test them.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/intel/intel_extensions.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri
Forbes chr...@ijw.co.nz wrote:
Moves the definition of the sample locations out of
gen6_emit_3dstate_multisample, and unpacks them in
gen6_get_sample_postiion.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_context.c| 3 +
src/mesa/drivers/dri
For the series:
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Wed, Jan 9, 2013 at 11:26 AM, Paul Berry stereotype...@gmail.com wrote:
In the process of reviewing Chris Forbes' patches to implement
ARB_texture_multisample, we discovered considerable confusion in the
code that refers to surface
Hi Paul,
They do work -- they just take the same path as TEXTURE_2D_ARRAY by
this point. It's possible that we're missing some assert(depth0 % 6 ==
0) for sanity there.
Have a look at this piglit:
tests/spec/arb_texture_cube_map_array/cubemap.c; it uses a 2-layer
cubemap array, and depth0 is 12
Here is a simple patch which adds support for the
GL_AMD_seamless_cubemap_per_texture extension to the i965 driver. This may
actually work on pre-Gen6 devices as well, but I haven't been able to test on
one.
Passes the piglit test for this extension.
Originally sent to dri-patches@, but
---
src/mesa/drivers/dri/i965/brw_wm_sampler_state.c |2 +-
src/mesa/drivers/dri/i965/gen7_sampler_state.c |2 +-
src/mesa/drivers/dri/intel/intel_extensions.c|3 +++
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
Does anyone know of any actual use for
GL_AMD_seamless_cubemap_per_texture? I can't think of any -- it reads
I've had a couple of cases where I was using cubes for
non-environment-map things, and the lack of filtering across faces was
useful.
I agree that you pretty much always just want
+void
+brw_blorp_params::exec(struct intel_context *intel) const
+{
+ switch (intel-gen) {
+ case 6:
+ gen6_blorp_exec(intel, this);
+ break;
+ case 7:
+ gen7_blorp_exec(intel, this);
+ break;
+ default:
+ /* BLORP is not supported before Gen7. */
+
This fixes glGetStringi(GL_EXTENSIONS,.. for core contexts. Previously,
all extension names returned would be NULL.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/extensions.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/extensions.c b/src
From the master surface formats list in the Sampler Engine chapter.
The relevant formats for 2_10_10_10 are mentioned in the Sandybridge
PRM as vertex attribute types, but the 0x1b*- encodings are missing from its
list in the Sampler Engine chapter.
---
src/mesa/drivers/dri/i965/brw_defines.h |
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index f5f65ca..0a563ed 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 0a563ed..aba1559 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index aba1559..6b073ad 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 6b073ad..f2d177a 100644
---
TODO: determine exactly which gens can do this. At least 6+;
perhaps as early as 4+?
---
src/mesa/drivers/dri/intel/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c
b/src/mesa/drivers/dri/intel/intel_extensions.c
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index f5f65ca..8ffcc57 100644
--- a/src/mesa/drivers/dri
Always use R10G10B10A2_UINT; Most of the other formats we'd like
don't actually work on the hardware. Will emit w/a for scaling,
sign recovery and BGRA swizzle in the VS.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 18 +-
1 file
Next few patches build on this to add other workarounds
for packed formats.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 14 +++---
src/mesa/drivers/dri/i965/brw_vs.c | 9 +
src/mesa/drivers/dri/i965/brw_vs.h
Flag the need for various workarounds to be applied by
the vertex shader.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vs.c | 30 ++
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b
for final version.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vs_emit.c | 49 +++--
1 file changed, 47 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c
b/src/mesa/drivers/dri/i965/brw_vs_emit.c
Enabled on Gen4+.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
docs/GL3.txt | 2 +-
src/mesa/drivers/dri/intel/intel_extensions.c | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index 876165f..6e66e55 100644
.
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Tue, Sep 10, 2013 at 6:38 AM, Kenneth Graunke kenn...@whitecape.org wrote:
Otherwise, coordinates with four components would result in a MOV
with a destination writemask that has no channels enabled:
mov(8) g1151.F 0D { align16 WE_normal NoDDChk 1Q
In the commit message:
Fortunately, OpenGL only requires separate streams to be supported
when the output type is points, and EndPrimitive() only has an effect
when the input type is line_strip or triangle_strip, so it's not a...
Shouldn't this say 'output type' ?
-- Chris
On Tue, Sep 10,
This is a fair bit saner :)
For the series:
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Tue, Sep 10, 2013 at 11:00 AM, Kenneth Graunke kenn...@whitecape.org wrote:
We can easily compute these without loops, resulting in simpler and
shorter code.
Signed-off-by: Kenneth Graunke kenn
Can we make this approximation conditional on an image-quality control
in driconf [or somewhere else]?
On Thu, Sep 12, 2013 at 5:00 PM, Chia-I Wu olva...@gmail.com wrote:
From: Chia-I Wu o...@lunarg.com
Replicate the gradient of the top-left pixel to the other three pixels in the
subspan, as
. In a *very* quick look I haven't found
anything equivalent -- but I might just be being blind.
CC'ing Ian -- any opinion? Is there any conformance issue here?
-- Chris
On Thu, Sep 12, 2013 at 8:41 PM, Chia-I Wu olva...@gmail.com wrote:
On Thu, Sep 12, 2013 at 2:06 PM, Chris Forbes chr...@ijw.co.nz
Sounds good to me.
On Fri, Sep 13, 2013 at 3:11 PM, Chia-I Wu olva...@gmail.com wrote:
On Thu, Sep 12, 2013 at 10:48 PM, Ian Romanick i...@freedesktop.org wrote:
On 09/12/2013 01:06 AM, Chris Forbes wrote:
Can we make this approximation conditional on an image-quality control
in driconf
This series adds support for ARB_texture_gather.
Patches 1-2 add the core mesa and GLSL compiler scaffolding for the extension;
Patches 3-5 add basic support to the i965 driver;
Patches 6-10 work around a hardware bug which causes incorrect sampling of
R32G32_FLOAT surfaces;
Patch 11 turns
From: Maxence Le Dore maxence.led...@gmail.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mapi/glapi/gen/ARB_texture_gather.xml | 14 ++
src/mapi/glapi/gen/gl_API.xml | 2 +-
src/mesa/main/context.c | 4
src/mesa/main/extensions.c
From: Maxence Le Dore maxence.led...@gmail.com
V2 [Chris Forbes]:
- Add new pattern, fixup parameter reading.
V3: Rebase onto new builtins machinery
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/builtin_functions.cpp | 35 +++
src/glsl
Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and
low-level support for emitting it via generate_tex().
V3: Updated for changes in master.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_defines.h
), and then don't do
anything afterward in the shader.
* For 0/1 swizzles blast the appropriate constant over all the output
channels instead of sampling.
V2: Avoid duplicating header enabling block
V3: Avoid sampling at all, for degenerate swizzles.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Pretty much the same as the FS case. Channel select goes in the header,
V2: Less mangling.
V3: Avoid sampling at all, for degenerate swizzles.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4
src/mesa/drivers/dri/i965/brw_program.h| 5 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4
src/mesa/drivers/dri/i965/brw_wm.c | 9 +
4 files
gather4 GREEN channel against a surface with format R32G32_FLOAT doesn't work
correctly on IVB. w/a from bspec:
- use R32G32_FLOAT_LD = 0x97 instead, for gather4 only.
- select BLUE channel to read GREEN
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 8 ++--
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
b/src/mesa/drivers/dri
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
src/mesa/drivers/dri/i965/intel_extensions.c | 4
2 files changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index
adjusted to provoke this behavior.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Cc: 9.2 mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
This is useful when working on the drivers, since falling back to
indirect rendering means we broke our driver's ability to load somehow.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
docs/envvars.html | 1 +
src/glx/glxext.c | 10 --
2 files changed, 9 insertions(+), 2 deletions
Fixed and landed on master now.
On Mon, Sep 23, 2013 at 8:05 AM, Eric Anholt e...@anholt.net wrote:
Chris Forbes chr...@ijw.co.nz writes:
Hardware requires the magnitude of the largest component to not exceed
1; brw_cubemap_normalize ensures that this is the case.
Unfortunately, we would
We have the destination framebuffer object passed in; there's no need to
go digging around in the context.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers
cube
arrays in the VS.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Cc: 9.2 mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp
b
This series adds support for ARB_texture_gather in core mesa and in i965 for
Gen7+.
Notable changes from V3:
- Only emit extra surface state, recompiles, etc if the shader actually uses
gather4.
- Use SCS to accomplish the workaround on Haswell [will need testing]
Cc: Kenneth Graunke
From: Maxence Le Dore maxence.led...@gmail.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mapi/glapi/gen/ARB_texture_gather.xml | 14 ++
src/mapi/glapi/gen/gl_API.xml | 2 +-
src/mesa/main/context.c | 4
src/mesa/main/extensions.c
From: Maxence Le Dore maxence.led...@gmail.com
V2 [Chris Forbes]:
- Add new pattern, fixup parameter reading.
V3: Rebase onto new builtins machinery
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/builtin_functions.cpp | 35 +++
src/glsl
Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and
low-level support for emitting it via generate_tex().
V3: Updated for changes in master.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_defines.h
), and then don't do
anything afterward in the shader.
* For 0/1 swizzles blast the appropriate constant over all the output
channels instead of sampling.
V2: Avoid duplicating header enabling block
V3: Avoid sampling at all, for degenerate swizzles.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Pretty much the same as the FS case. Channel select goes in the header,
V2: Less mangling.
V3: Avoid sampling at all, for degenerate swizzles.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
---
src/glsl/ir_set_program_inouts.cpp | 9 +
src/mesa/main/mtypes.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/src/glsl/ir_set_program_inouts.cpp
b/src/glsl/ir_set_program_inouts.cpp
index 1267d6d..ab23538 100644
--- a/src/glsl/ir_set_program_inouts.cpp
+++
V4: Only flag quirks if there are any uses of gather in the shader,
to avoid spurious recompiles just because someone happened to use
RG32F.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4
src/mesa/drivers/dri/i965/brw_program.h
gather4 GREEN channel against a surface with format R32G32_FLOAT doesn't work
correctly on IVB. w/a from bspec:
- use R32G32_FLOAT_LD = 0x97 instead, for gather4 only.
- select BLUE channel to read GREEN
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965
Worst-case is that *every* texunit uses a format that needs overriding.
V4: Place the gather slots last, so shaders which don't use gather don't
get penalized by having a huge binding table.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_context.h | 20
what w/a to apply.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 38 +++
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 6 +++-
3 files changed, 39
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
src/mesa/drivers/dri/i965/intel_extensions.c | 4
2 files changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 8 ++--
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa
The new surface channel select bits allow us to avoid having to
recompile the shader for this workaround.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_wm.c| 5 +++--
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14 --
2 files
With those fixes:
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Wed, Oct 2, 2013 at 6:38 AM, Ian Romanick i...@freedesktop.org wrote:
On 09/30/2013 10:54 PM, Chia-I Wu wrote:
From: Chia-I Wu o...@lunarg.com
I agree with both of Ken's comments. With those fixed, this patch is
Reviewed
Acked-by: Chris Forbes chr...@ijw.co.nz
On Wed, Oct 2, 2013 at 8:38 AM, Paul Berry stereotype...@gmail.com wrote:
Previously, we computed dFdy() using the following instruction:
add(8) dst1F src4,4,0)F -src.24,4,0F { align1 1Q }
That had the disadvantage that it computed the same value
Hi Paul,
Sorry, I should have run make check first.
I'll fix this when I get home.
-- Chris
On Thu, Oct 3, 2013 at 1:06 PM, Paul Berry stereotype...@gmail.com wrote:
On 30 September 2013 03:08, Chris Forbes chr...@ijw.co.nz wrote:
From: Maxence Le Dore maxence.led...@gmail.com
Reviewed
Clean up inconsistency in enum decoration:
- Use the undecorated enums where possible.
- MAX_PROGRAM_TEXTURE_GATHER_COMPONENTS_ARB remains decorated, since it
has no undecorated equivalent in GL4.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mapi/glapi/gen/ARB_texture_gather.xml | 6
This series adds support for ARB_texture_query_levels on i965 Gen6+. The fourth
channel of the resinfo message (used for textureSize()) includes the correct
value for textureQueryLevels().
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/extensions.c | 1 +
src/mesa/main/mtypes.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index c0f17c5..2507fdf 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/builtin_functions.cpp | 56 +
src/glsl/glcpp/glcpp-parse.y| 3 ++
src/glsl/glsl_parser_extras.cpp | 1 +
src/glsl/glsl_parser_extras.h | 2 ++
src/glsl/ir.cpp
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index a8ad659
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 9e6cc78
Theoretically would work on Gen5 as well but requires GLSL 1.30, which
is not (yet) enabled by default there.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965
I haven't tested this thoroughly, but this is how it looks like
it ought to work from the PRM.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 80073cd..7ddeb6e 100644
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 52076f7..6f024b4 100644
--- a/src/mesa/drivers/dri
Eek -- so I am. Thanks for spotting this.
On Sat, Oct 5, 2013 at 8:07 PM, Christoph Brill egore...@egore911.de wrote:
2013/10/5 Chris Forbes chr...@ijw.co.nz
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 15 ++-
1 file changed
This series adds some of the new textureGather variants from ARB_gpu_shader5,
and implementation for i965 Gen7+.
- Use with gsampler2DRect
- Component select in the shader
___
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ARB_gpu_shader5 introduces new variants of textureGather* which have an
explicit component selector, rather than relying purely on the sampler's
swizzle state.
This patch adds the GLSL plumbing for the extra parameter.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl
- gsampler2DRect support
- optional `comp` parameter
Future patches will add shadow sampler support and
textureGatherOffsets().
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/builtin_functions.cpp | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff
-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 6141009..5508cdc 100644
--- a/src
-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 224524e..4307125 100644
As of ARB_gpu_shader5, textureGather doesn't always read the
post-swizzle RED channel -- so we can't just look at the red swizzle
state.
Theoretically we could only flag the quirk if *some* green swizzle is in
use, but that's probably more trouble than it's worth.
Signed-off-by: Chris Forbes chr
Yes, that's clearer; what I had was a strange artifact of how it grew :)
-- Chris
On Sun, Oct 6, 2013 at 6:54 AM, Kenneth Graunke kenn...@whitecape.org wrote:
On 10/05/2013 03:38 AM, Chris Forbes wrote:
ARB_gpu_shader5 introduces new variants of textureGather* which have an
explicit component
...@whitecape.org wrote:
On 10/05/2013 03:38 AM, Chris Forbes wrote:
- For HSW: Select the channel based on the component selected (swizzle
is done in HW)
- For IVB: Select the channel based on the swizzle state for the
component selected. Only apply the RG32F w/a if we actually want
green -- we're
- gsampler2DRect
- optional `comp` parameter
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/builtin_functions.cpp | 16
1 file changed, 16 insertions(+)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index d40888d..aa40876 100644
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 45 ++--
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index
This series adds support for the following textureGather* enhancements
that are part of ARB_gpu_shader5:
- new textureGatherOffset variants
- nonconstant offset for all textureGatherOffset variants, when GLSL 4.00 or
ARB_gpu_shader5 is in use. If only ARB_texture_gather is enabled, const
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 0cf8277
Prior to ARB_gpu_shader5 / GLSL 4.0, the offset is required to be
a constant expression.
With that extension, it is relaxed to be any dynamically uniform
expression. If the value is not dynamically uniform, the results
are undefined.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 61c4bf5..19500d1 100644
--- a/src/mesa/drivers/dri/i965
The generator code ends up clearer this way than if we had to sniff
via mlen. Implemented via the gather4_po message in hardware, which is
present in Gen7 and later.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965
Some texturing ops are about to have nonconstant offset support; the
offset in the header in these cases should be zero.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers
The commit message is wrong -- there is no requirement for the offset
to be dynamically uniform, either in the spec or in the i965
implementation in later patches.
On Tue, Oct 8, 2013 at 10:34 PM, Chris Forbes chr...@ijw.co.nz wrote:
Prior to ARB_gpu_shader5 / GLSL 4.0, the offset is required
Sorry, that was a bit sloppy on my part..
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Wed, Oct 9, 2013 at 10:00 AM, Eric Anholt e...@anholt.net wrote:
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965
... in which support for shadow samplers is added.
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ARB_gpu_shader5's textureGather*() functions which take shadow samplers
have a separate `refz` parameter rather than adding it to the
coordinate.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/builtin_functions.cpp | 20 +++-
1 file changed, 15 insertions(+), 5
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/builtin_functions.cpp | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index ef8b7bb..deedddb 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_defines.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index f1ea736..c0caba6 100644
--- a/src/mesa/drivers/dri/i965
gather4_c's argument layout is straightforward -- refz just goes on the
end.
gather4_po_c's layout however -- the array index is replaced with refz.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 12 ++--
src/mesa/drivers/dri/i965
Note that gather4_po_c's parameters are too long for SIMD16. It might be
worth emitting 2xSIMD8 messages in this case at some point.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 15 ---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
The 1D array case doesn't actually exist -- there is no 1D texture
support for gather.
For 2D arrays, the array index lands in the `r` slot of the message.
On Fri, Oct 11, 2013 at 9:25 AM, Eric Anholt e...@anholt.net wrote:
Chris Forbes chr...@ijw.co.nz writes:
Note that gather4_po_c's
You're right, that looks completely bogus.
I only have compiler tests and eyeballs for the shadow variants at
this point -- I'll sort that out :)
-- Chris
On Fri, Oct 11, 2013 at 9:33 AM, Eric Anholt e...@anholt.net wrote:
Chris Forbes chr...@ijw.co.nz writes:
gather4_c's argument layout
Yes; fortunately we don't have to support offset and shadow together on them.
On Fri, Oct 11, 2013 at 10:13 AM, Eric Anholt e...@anholt.net wrote:
Chris Forbes chr...@ijw.co.nz writes:
The 1D array case doesn't actually exist -- there is no 1D texture
support for gather.
For 2D arrays
Great to see this enabled!
For the series:
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Fri, Oct 11, 2013 at 7:12 PM, Kenneth Graunke kenn...@whitecape.org wrote:
On 10/10/2013 09:33 PM, Dave Airlie wrote:
On Fri, Oct 11, 2013 at 2:27 PM, Paul Berry stereotype...@gmail.com wrote:
It's been
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