From: Dave Airlie
This is required as part of ARB_gpu_shader5.
no backend changes are required for this, or if
any are, it's the same ones as for samplers.
Signed-off-by: Dave Airlie
---
docs/GL3.txt | 2 +-
src/gallium/drivers/radeonsi/si_shader.c
From: Dave Airlie
This adds the frontend support, however the llvm
backend produces the wrong pattern, however
we can conditionalise enabling ARB_gpu_shader5
on whatever version of llvm we fix this in.
Signed-off-by: Dave Airlie
---
docs/GL3.txt | 2 +-
src
These two are needs for ARB_gpu_shader5 support,
the only remaining piece is geometry streams, and
I have them implemented, but they are a bit conflicty
with tess.
This also needs an llvm change for sampler indirect
to work, but we should land the frontend pieces.
Dave.
From: Dave Airlie
These entries were put in the GL4.0 section, so removed the commented
out ones.
Signed-off-by: Dave Airlie
---
src/mesa/main/tests/dispatch_sanity.cpp | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/mesa/main/tests/dispatch_sanity.cpp
b/src/mesa/main/tests
From: Dave Airlie
This fixes make check since the tess changes.
Signed-off-by: Dave Airlie
---
src/glsl/tests/varyings_test.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/tests/varyings_test.cpp b/src/glsl/tests/varyings_test.cpp
index 4573529..62f8c6b 100644
From: Dave Airlie
Signed-off-by: Dave Airlie
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 6c97933..33469d4 100644
--- a/src/mesa/drivers/dri/i965
From: Dave Airlie
Signed-off-by: Dave Airlie
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 6c97933..33469d4 100644
--- a/src/mesa/drivers/dri/i965
From: Dave Airlie
This extension is about setting expectation on GL4.1 implementations
rather than actually enforcing things. So once you support GLSL 410
then you support this in theory.
Signed-off-by: Dave Airlie
---
docs/GL3.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On 23 July 2015 at 15:01, Kenneth Graunke wrote:
> On Tuesday, July 21, 2015 03:19:25 PM Dave Airlie wrote:
>> From: Dave Airlie
>>
>> This fleshes out the APIs, using the program resource
>> APIs where they should match.
>>
>> It also sets the default va
From: Dave Airlie
This just adds some missing pieces to nir/i965,
it is lightly tested on my Haswell.
Signed-off-by: Dave Airlie
---
docs/GL3.txt | 2 +-
docs/relnotes/10.7.0.html| 2 +-
src/glsl/glsl_types.cpp
of fp64 support (Ilia)
cc: "11.0"
Signed-off-by: Dave Airlie
---
src/mesa/main/uniform_query.cpp | 53 -
1 file changed, 37 insertions(+), 16 deletions(-)
diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index d487297.
From: Dave Airlie
This fixes the fetching of fp64 inputs to the geometry shader,
this fixes the recently posted piglit's
arb_gpu_shader_fp64/execution/gs-fs-vs-double-array.shader_test
arb_vertex_attrib_64bit/execution/gs-fs-vs-attrib-double-array.shader_test
Signed-off-by: Dave A
Hey all,
Things finally seem to be heading upstream in qemu and kernel
land, so I'm going to post this now.
virgl is a project started by me to create a virtio based
GPU using gallium/tgsi as the basis for 3D acceleration.
The 3D acceleration portion is contained a qemu plugin library
virglrende
This adds support to the parser to accept hex values as floats,
and then adds support to the dumper to allow the user to select
to dump float as 32-bit hex numbers.
This is required to get accurate values for virgl use of TGSI.
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/tgsi
From: Dave Airlie
This is used to detect error in virgl if we overflow the shader
dumping buffers.
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/tgsi/tgsi_dump.c | 10 --
src/gallium/auxiliary/tgsi/tgsi_dump.h | 2 +-
2 files changed, 9 insertions(+), 3 deletions(-)
diff
to the remote renderer, and the
results are readback and copies to the screen
using drisw. This works well enough to develop
new features and to help debug.
Signed-off-by: Dave Airlie
---
configure.ac | 1 +
src/gallium/Makefile.am
you gotta give me something in the commit msg to have any idea what
I'm reading here :-)
why does process_parameters move?
is there a piglit for subroutine/arrays?
Dave.
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ping?
On 9 October 2015 at 10:38, Dave Airlie wrote:
> From: Dave Airlie
>
> So I've known this was broken before, cogl has a workaround
> for it from what I know, but with the gallium based swrast
> drivers BlitFramebuffer from back to front or vice-versa
> was pretty
On 16 October 2015 at 12:51, Timothy Arceri wrote:
> On Fri, 2015-10-16 at 11:44 +1000, Dave Airlie wrote:
>> you gotta give me something in the commit msg to have any idea what
>> I'm reading here :-)
>>
>> why does process_parameters move?
>
> Because we ne
For all 4:
Reviewed-by: Dave Airlie
On 23 October 2015 at 08:42, wrote:
> From: Roland Scheidegger
>
> Just need to use resource target not view target when calculating
> first-layer based mip offsets. (This is a gl specific problem since
> d3d10 does not distinguish betwee
From: Dave Airlie
since 1ad305b612f389fb04c6d51847427d5ec72fae03
Brian Paul
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: plumb offset/size parameters through GetTexSubImage code
I found this testing virgl which exercises a bunch of these
in it's fallbacks.
Signed-off-by: Dave A
wrappers, 'includes what you want' and related fixes.
>>
>> As some of these can be seen as bikeshedding, although rest assured
>> there is a method to the madness, I think.
While I do consider some of it bikesheddy in nature, I can't argue
against any of it,
All
>
> What exactly are the parameters to glGetTextureSubImage() that hits this?
It's actually a call to glGetnTexImage
#4 0x772ce215 in get_tex_depth (ctx=0x9d03d0, dimensions=2,
xoffset=0, yoffset=0, zoffset=0, width=65, height=1, depth=40,
format=6402, type=5125,
pixels=0xe32a10, tex
Coverity reported that ret could only be 0 or 1, since it
was setting ret = fn() > 0, instead of doing (ret = fn()) > 0.
Signed-off-by: Dave Airlie
---
src/gallium/winsys/virgl/drm/virgl_drm_winsys.c | 2 +-
src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c | 2 +-
2 files chan
On 3 November 2015 at 07:31, Roland Scheidegger wrote:
> Am 02.11.2015 um 20:55 schrieb Ilia Mirkin:
>> FTR these are the various operators on nvidia hw:
>>
>> https://urldefense.proofpoint.com/v2/url?u=http-3A__docs.nvidia.com_cuda_parallel-2Dthread-2Dexecution_-23cache-2Doperators&d=BQIFaQ&c=Sqc
On 8 November 2015 at 02:47, Emil Velikov wrote:
> Hi Dave,
>
> On 9 October 2015 at 01:38, Dave Airlie wrote:
>> From: Dave Airlie
>>
>> So I've known this was broken before, cogl has a workaround
>> for it from what I know, but with the gallium based
So it appears my patch to enable front buffer access on soft/llvmpipe
causes some piglit regressions. However these are due to piglit having
undefined behaviour where it doesn't create a window but has tests
requiring a front buffer. The new code does an XGetImage on the front
buffer and when it fa
From: Dave Airlie
There might be a reason we do this inside the thread, but I'm not aware of it
yet, move stuff around and see if this jogs anyone's memory.
Doing this outside the thread at least with front buffer rendering avoids
problems with XGetImage failing in the thread and d
From: Dave Airlie
There might be a reason we do this inside the thread, but I'm not aware of it
yet, move stuff around and see if this jogs anyone's memory.
Doing this outside the thread at least with front buffer rendering avoids
problems with XGetImage failing in the thread and d
On 10 November 2015 at 00:30, Roland Scheidegger wrote:
> Am 09.11.2015 um 04:44 schrieb Dave Airlie:
>> So it appears my patch to enable front buffer access on soft/llvmpipe
>> causes some piglit regressions. However these are due to piglit having
>> undefined behaviour wher
On 10 November 2015 at 06:36, Brian Paul wrote:
> On 11/09/2015 01:15 PM, Dave Airlie wrote:
>>
>> On 10 November 2015 at 00:30, Roland Scheidegger
>> wrote:
>>>
>>> Am 09.11.2015 um 04:44 schrieb Dave Airlie:
>>>>
>>>> So it
From: Dave Airlie
On some chips the GSVS itemsize needs to be aligned to a cacheline size.
This only applies to some of the r600 family chips.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_state.c | 20
1 file changed, 20 insertions(+)
diff --git a/src
I've had these sitting locally and heiko on #dri-devel found
they fixed some issues for him.
Marek provided me with some errata and this is the results of
implementing them.
It is nearly all fixes for r600 era hw.
Dave.
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From: Dave Airlie
streamout, gs rings bug on certain r600s, requires a wait idle
before each surface sync.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_hw_context.c | 4
src/gallium/drivers/r600/r600_pipe.h | 1 +
src/gallium/drivers/r600/r600_state_common.c
From: Dave Airlie
This is specified in the docs for rv670 to work properly.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_state.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600
From: Dave Airlie
SB suggests we do this for r600, so lets do it,
for the copy shader.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600
From: Dave Airlie
Need to insert a SQ_NON_EVENT when ever geometry
shaders are enabled.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_hw_context.c | 5 +
src/gallium/drivers/r600/r600_pipe.h | 1 +
src/gallium/drivers/r600/r600_state_common.c | 7 +++
src
From: Dave Airlie
We need to emit at least one cut/emit in every
geometry shader, the easiest workaround it to
stick a single CUT at the top of each geom shader.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src
From: Dave Airlie
Seems like MFC should be set for this shader.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 80922bf..c8eb03f
From: Dave Airlie
The docs say we should send the emit after the ring writes,
so lets do that and not have an ALU in between.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 42 +++---
1 file changed, 24 insertions(+), 18 deletions(-)
diff
>>
>> Well, it's not just a NIR thing -- GLSL IR also effectively treats
>> subroutines as integers. Actually, I wonder why the
>> glsl_type::is_vector_or_scalar() doesn't return true for subroutine
>> types in the first place.
>
> For that matter, why do we have a special subroutine type at all?
From: Dave Airlie
This should fix the getteximage-depth test that currently asserts.
I was hitting problem with virgl as well in this area.
This moves the 1D array handling code to a single place.
Signed-off-by: Dave Airlie
---
src/mesa/main/texgetimage.c | 24 +---
1
From: Dave Airlie
This fixes the corruption on rendering that we are seeing in
certain geometry shaders.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/evergreen_state.c | 4
src/gallium/drivers/r600/evergreend.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/src
On 22 January 2015 at 11:35, Matt Turner wrote:
> On Wed, Jan 21, 2015 at 5:28 PM, Dave Airlie wrote:
>> From: Dave Airlie
>>
>> anonymous structs/union don't work with c99 but do work with gnu99
>> on gcc 4.4.
>>
>> This on top of Jason's desig
Hey,
This didn't look like it should be too difficult, however I have
two worries about my approach
a) the prereq change to move the pixel shader selector,
I should probably move more code, but it might not matter,
but I worry this could have side effects though the ps key
doesn't depend
From: Dave Airlie
In order to detect that a pixel shader has a prim id
input when we have no geometry shader we need to reorder
the shader selection so the pixel shader is selected
first, then the vertex shader key can take into account
the primitive id input requirement and lack of geom shader
From: Dave Airlie
GLSL 1.50 specifies a fragment shader may have a primitive id
input without a geometry shader present.
On r600 hw there is a special GS scenario for this, you have
to enable GS_SCENARIO_A and pass the primitive id through
the vertex shader which operates in GS_A mode.
This is
From: Dave Airlie
This use the gallium poly stipple helper to modify
the fragment shader and sets up the appropriate state
around it.
This renders the polys test from mesa demos properly.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=25280
TODO:
should this be in radeon common code
On 27 January 2015 at 18:04, Dave Airlie wrote:
> From: Dave Airlie
>
> This use the gallium poly stipple helper to modify
> the fragment shader and sets up the appropriate state
> around it.
>
> This renders the polys test from mesa demos properly.
> Fixes:
> h
(oops pushed send too quick)
> So there is resistance to a query API upstream in the KHR area, at
> least according
> to https://www.khronos.org/registry/egl/extensions/MESA/EGL_MESA_drm_image.txt
> which I based this on.
>
> So I'm wondering how would this API look if we are going to pass back
> m
>>
>> On 29 August 2014 08:46, Gwenole Beauchesne wrote:
>>>
>>> Could you please describe in there the ownership model? I think the
>>> implementation should own the fd, so the clients should dup() it if
>>> ever necessary.
>>
>>
>> So the fd can be destroyed at any time, particularly with thread
From: Dave Airlie
Like the RGTC code sharing this could be done nicer in the util lib.
This slighty increase i965_dri.so size by ~100 bytes,
but it decreases the combined gallium driver by over 1k,
and its just nicer to avoid TAG().
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/util
On 30 December 2014 at 08:14, Roland Scheidegger wrote:
> Just minor nits, looks good to me otherwise.
> I agree with others that probably the round family of functions should
> be added too (but could be done in another patch). Maybe could have one
> cap bit then (so some implementations only doi
These 3 patches are similiar to the last repost, and I'd like
to merge them to get the ball rolling.
The main change is adding DRSQ to this list, Ilia has some other
patches to add the rounding ones, but I'd like to get things started
with this set and work forwards.
Dave.
__
From: Dave Airlie
These act like flt32 except they take up two slots, and you
can only add 2 x flt64 constants in one slot.
The main reason they are different is we don't want to match half a flt64
constants against a flt32 constant in the matching code, we need to make
sure we treat both
(Glenn), fix review comments (Glenn).
v3.1: add DRSQ docs, fix typo (Roland)
This is based on code by Michael Krol
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 753 -
src/gallium/auxiliary/tgsi/tgsi_info.c | 25 +-
src/gallium/docs/
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/tgsi/tgsi_exec.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h
b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index cc5a916..256cf72 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
On 9 February 2015 at 08:44, Aditya Avinash wrote:
> Ya. I just want to know that part "only some r600".
> I believe some of the nv0 cards doesn't support double. You have any ideas
> or suggestions to make it possible?
For AMD
http://en.wikipedia.org/wiki/List_of_AMD_graphics_processing_units
h
On 9 February 2015 at 09:30, Matt Turner wrote:
> On Sun, Feb 8, 2015 at 2:51 PM, Dave Airlie wrote:
>> On 9 February 2015 at 08:44, Aditya Avinash wrote:
>>> Ya. I just want to know that part "only some r600".
>>> I believe some of the nv0 cards doesn
On 12 February 2015 at 23:49, Maarten Lankhorst
wrote:
> Op 12-02-15 om 14:23 schreef Glenn Kennard:
>> Don't try to do float comparisons on signed integer values,
>> some of them look like NaNs.
>>
>> Fixes fs-temp-array-mat3-index-col-row-rd.shader_test regression
>> caused by 0d4272cd8e7c451571
From: Dave Airlie
There was some code here to avoid MULADD on r600/r700, however some
recent changes caused some tests to start failing on evergreen as well.
(cayman has no T slot).
It seems likely there are some issues with writing a register in XYZW slots
and reading the same registers in T
From: Dave Airlie
everytime I open this file in emacs with show trailing whitespace
or git add from it my screen flares with red.
Just do a general cleanup, makes working on fp64 support not as
jarring.
I'm not saying this is perfect, its just better than before.
Signed-off-by: Dave A
On 10 February 2015 at 21:59, Ilia Mirkin wrote:
> Signed-off-by: Ilia Mirkin
This makes sense but the warning is there now, so I tore out the IMAGE
bits and pushed them.
The double bits are,
Reviewed-by: Dave Airlie
Dave.
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On 10 February 2015 at 21:59, Ilia Mirkin wrote:
> Signed-off-by: Ilia Mirkin
Looks good to me,
Reviewed-by: Dave Airlie
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This seems like the correct solution, hopefully Ian can further examine this,
but it seems to fix the problems seen.
Reviewed-by: Dave Airlie
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From: Dave Airlie
When we schedule an instructions with undefined value, we
eventually will use 0, which is a constant, however sb wasn't
taking this into account and creating ops with illegal scalar
swizzles.
this replaces my fix for op3 in t slots.
Signed-off-by: Dave Airlie
---
I've addressed most of these,
>>
>> + /* double modifiers handled by caller */
>> + if (dtype)
>> + return;
>
> Should the below code just get moved to fetch_source? Or does it rely
> on local args which makes that a pain? If it's not too hard, I think
> it'd be a lot cleaner / clearer th
(Glenn), fix review comments (Glenn).
v4: drop DDIV
v4.1: cleanups, fix some docs bugs, (Ilia)
rework store_dest and fetch_source fns. (Ilia)
This is based on code by Michael Krol
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 765
From: Dave Airlie
It looks like no hw does div anyways, so we should just
lower at the GLSL level.
Signed-off-by: Dave Airlie
---
src/glsl/lower_instructions.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl
From: Dave Airlie
v2 : add double to int/unsigned conversion
v3: handle fp64 consts better
v4: use DRSQ
v4.1: add d2b
v4.2: drop DDIV
v5: split out some prep patches.
v5.1: add some comments.
v5.2: more comments
v6: simplify down the double instruction
generation loop.
v7: Merge Ilia&#
This just fills in some blanks to avoid warnings in the i965 driver.
Signed-off-by: Dave Airlie
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp | 13 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
he docs I mentioned on irc
This series is
Reviewed-by: Dave Airlie
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From: Dave Airlie
This allows drivers to work out if a shader contains any
double opcodes easily.
Signed-off-by: Dave Airlie
---
src/gallium/auxiliary/tgsi/tgsi_scan.c | 4
src/gallium/auxiliary/tgsi/tgsi_scan.h | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src
This just implements FP64 on cayman but disables the sb compiler
for now.
Dave.
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From: Dave Airlie
Only a subset of AMD GPUs supported by r600g support doubles,
CAYMAN and CYPRESS are probably all we'll try and support, however
I don't have a CYPRESS so ignore that for now.
This disables SB support for doubles, as we think we need to
make the scheduler smarter to
From: Dave Airlie
I'm not sure we really care about this, but we need to
write better support if we do. For now just disable it.
piglit test:
tests/spec/arb_gpu_shader_fp64/execution/vs-out-fs-in-double-2.shader_test
Signed-off-by: Dave Airlie
---
src/glsl/lower_packed_varyings.cp
From: Dave Airlie
This hack for fixing gl_FragDepth apparantly caused a GLSL shader
outputting a single double to try and output a dvec4, but we hadn't
assigned outputs for the secondary bit.
This avoids going into the hack code for scalar doubles.
Signed-off-by: Dave Airlie
---
src
On 20 February 2015 at 12:49, Ilia Mirkin wrote:
> On Thu, Feb 19, 2015 at 9:43 PM, Dave Airlie wrote:
>> From: Dave Airlie
>>
>> I'm not sure we really care about this, but we need to
>> write better support if we do. For now just disable it.
&
From: Dave Airlie
I'm not sure we really care about this, but we need to
write better support if we do. For now just disable it.
piglit test:
tests/spec/arb_gpu_shader_fp64/execution/vs-out-fs-in-double-2.shader_test
v2: move code down below to avoid getting array type.
Signed-off-by:
SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
> +return 0;
> case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
> case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
> return VC4_MAX_TEXTURE_SAMPLERS;
Why does vc4 no collapse them in
nd it seems like the best way to get double varying packing working.
Reviewed-by: Dave Airlie
>
> Signed-off-by: Ilia Mirkin
> ---
>
> Packing *all* doubles is a bit of a hack... we shouldn't need to do it
> for dvec2/dvec4. And yet, here we are. This means that setting
On 2 March 2015 at 01:23, Marek Olšák wrote:
> From: Marek Olšák
>
Reviewed-by: Dave Airlie
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89372
> ---
> src/gallium/auxiliary/draw/draw_pt_emit.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
&g
On 3 March 2015 at 10:37, Brian Paul wrote:
> On 03/02/2015 04:03 PM, Eric Anholt wrote:
>>
>> Kenneth Graunke writes:
>>
>>> Generated by the following Coccinelle semantic patch:
>>>
>>> @@
>>> expression E;
>>> @@
>>> if (
>>> -E
>>> +unlikely(E)
>>> )
>>> { ... _mesa_error(...) ... }
>>>
>>>
Okay I've revised this to add some more info to the interface,
essentially I need to get the fourcc back so I can later pass
it across the "wire" to the EGL_EXT_image_dma_buf_import, also
the number of planes (though for my usecase I don't care so much).
The problem with EGL_MESA_drm_image is tha
From: Dave Airlie
At the moment to get an EGL image to a dma-buf file descriptor,
you have to use EGL_MESA_drm_image, and then use libdrm to
convert this to a file descriptor.
This extension just provides an API modelled on EGL_MESA_drm_image,
to return a dma-buf file descriptor.
v2: update
On 3 March 2015 at 13:57, Dave Airlie wrote:
>
> Okay I've revised this to add some more info to the interface,
> essentially I need to get the fourcc back so I can later pass
> it across the "wire" to the EGL_EXT_image_dma_buf_import, also
> the number of planes
From: Dave Airlie
(just resending with some cleanups/updates).
At the moment to get an EGL image to a dma-buf file descriptor,
you have to use EGL_MESA_drm_image, and then use libdrm to
convert this to a file descriptor.
This extension just provides an API modelled on EGL_MESA_drm_image,
to
On 4 March 2015 at 05:06, Chad Versace wrote:
> On 03/03/2015 11:01 AM, Daniel Stone wrote:
>> Hi,
>>
>> On 3 March 2015 at 18:40, Chad Versace wrote:
>>> On 03/03/2015 12:13 AM, Daniel Stone wrote:
>>>> On Tuesday, March 3, 2015, Dave Ai
On 4 March 2015 at 05:23, Chad Versace wrote:
> On 03/03/2015 11:13 AM, Dave Airlie wrote:
>> On 4 March 2015 at 05:06, Chad Versace wrote:
>>> On 03/03/2015 11:01 AM, Daniel Stone wrote:
>>>> Hi,
>>>>
>>>> On 3 March 2015 at 18:40, Chad Vers
From: Dave Airlie
At the moment to get an EGL image to a dma-buf file descriptor,
you have to use EGL_MESA_drm_image, and then use libdrm to
convert this to a file descriptor.
This extension just provides an API modelled on EGL_MESA_drm_image,
to return a dma-buf file descriptor.
v2: update
this isn't hooked up to anything at all from what I can see.
Signed-off-by: Dave Airlie
---
src/mesa/state_tracker/st_cb_texture.c | 21 -
src/mesa/state_tracker/st_texture.h| 6 --
2 files changed, 27 deletions(-)
diff --git a/src/mesa/state_tr
This has no users.
Signed-off-by: Dave Airlie
---
src/mesa/state_tracker/st_texture.c | 40 -
src/mesa/state_tracker/st_texture.h | 10 --
2 files changed, 50 deletions(-)
diff --git a/src/mesa/state_tracker/st_texture.c
b/src/mesa/state_tracker
On 28 January 2017 at 10:35, Bas Nieuwenhuizen wrote:
> Apparently the source is not an address but an offset, so we actually
> need to use the base.
Nice find!
Reviewed-by: Dave Airlie
>
> Signed-off-by: Bas Nieuwenhuizen
> ---
> src/amd/common/ac_nir_to_llvm.c | 7 +--
On 30 January 2017 at 03:26, Bas Nieuwenhuizen wrote:
> v2: Create the descriptor BO with CPU access.
> Signed-off-by: Bas Nieuwenhuizen
Tom has pushed the spill to llvm 4.0 as well now, so with the checks
changed to 4.0
for the series:
Reviewed-by: Dave Airlie
> ---
> sr
From: Dave Airlie
It appears we can get image barriers like:
srcStageMask: VkPipelineStageFlags = 4096
(VK_PIPELINE_STAGE_TRANSFER_BIT)
dstStageMask: VkPipelineStageFlags = 4096
(VK_PIPELINE_STAGE_TRANSFER_BIT)
dependencyFlags
This is rebased onto the scratch buffer in CS preamble work
that Bas has done, makes this all a lot cleaner for emitting
the rings.
Otherwise there shouldn't be any changes.
Dave.
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From: Dave Airlie
This is to later allow ES shaders to be emitted.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_cmd_buffer.c | 69 +++-
1 file changed, 40 insertions(+), 29 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan
From: Dave Airlie
This just places the flag into the shader info so we can use it from
the driver after we create the shader.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 3 +++
src/amd/common/ac_nir_to_llvm.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/src/amd
From: Dave Airlie
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 6 ++
src/amd/common/ac_nir_to_llvm.h | 6 ++
2 files changed, 12 insertions(+)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index dedea65..fadbb55 100644
--- a/src/amd
From: Dave Airlie
This enables the paths for setting up user ptrs to vs/es and gs.
Signed-off-by: Dave Airlie
---
src/amd/vulkan/radv_cmd_buffer.c | 30 ++
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd
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