On Tue, 2017-02-14 at 11:32 +0100, Iago Toral Quiroga wrote:
> As soon as we support shaderStorageImageWriteWithoutFormat we can see
> write-only images (sampled == 2) that don't have a format specified.
> ---
I didn't do a thorough testing yet, but I caught this immediately
On Tue, 2017-02-14 at 09:46 +, Alex Smith wrote:
> On 14 February 2017 at 08:45, Iago Toral wrote:
> > On Mon, 2017-02-13 at 16:29 +, Lionel Landwerlin wrote:
> > > Run this by our CI earlier today and got a few failures :
> > >
> > > dEQP-VK.im
On Tue, 2017-02-14 at 11:37 +, Lionel Landwerlin wrote:
> On 14/02/17 11:19, Iago Toral wrote:
> >
> > On Tue, 2017-02-14 at 09:46 +, Alex Smith wrote:
> > >
> > > On 14 February 2017 at 08:45, Iago Toral
> > > wrote:
> > > >
> &
On Tue, 2017-02-14 at 11:42 +, Alex Smith wrote:
> Hi Iago,
>
> On 14 February 2017 at 11:19, Iago Toral wrote:
> > On Tue, 2017-02-14 at 09:46 +, Alex Smith wrote:
> > > On 14 February 2017 at 08:45, Iago Toral
> > wrote:
> > > > On Mon, 20
Both patches are:
Reviewed-by: Iago Toral Quiroga
On Tue, 2017-02-14 at 16:03 -0800, Jason Ekstrand wrote:
> ---
> src/util/Makefile.sources | 3 ++-
> src/util/vk_util.h| 43
> +++
> 2 files changed, 45 insertions(+), 1 deleti
Reviewed-by: Iago Toral Quiroga
You can also add the new piglit tests that this fixes to the commit
log.
Iago
On Wed, 2017-02-15 at 15:12 +0100, Jose Maria Casanova Crespo wrote:
> If an unsized declared array is not the last in an SSBO
> and an implicit size can not be defined on l
Patches 1-5 are:
Reviewed-by: Iago Toral Quiroga
On Fri, 2017-02-17 at 01:56 -0800, Kenneth Graunke wrote:
> These driver hooks are not used when MI_MATH and MI_LOAD_REGISTER_REG
> are supported, which Gen8+ can always do. So this code is dead.
>
> Signed-off-by: Kenneth Graunke
And patches 6-7 are also:
Reviewed-by: Iago Toral Quiroga
On Fri, 2017-02-17 at 13:21 +0100, Iago Toral wrote:
> Patches 1-5 are:
>
> Reviewed-by: Iago Toral Quiroga
>
> On Fri, 2017-02-17 at 01:56 -0800, Kenneth Graunke wrote:
> >
> > These driver hooks ar
; shouldn't miss anything right?).
>
> On 22/02/17 14:45, Iago Toral Quiroga wrote:
> >
> > This fixes a number of new CTS tests that would crash otherwise:
> > dEQP-VK.pipeline.render_to_image.*
> > ---
> > src/intel/vulkan/genX_cmd_buffer.c
On Wed, 2017-02-22 at 21:15 +0100, Marek Olšák wrote:
> On Wed, Feb 22, 2017 at 9:11 PM, Matt Turner
> wrote:
> >
> > On Wed, Feb 22, 2017 at 12:06 AM, Iago Toral Quiroga > .com> wrote:
> > >
> > > From: Iago Toral Quiroga > > ia.com>
>
On Wed, 2017-02-22 at 09:38 -0800, Jason Ekstrand wrote:
> On Wed, Feb 22, 2017 at 6:45 AM, Iago Toral Quiroga m> wrote:
> > This fixes a number of new CTS tests that would crash otherwise:
> > dEQP-VK.pipeline.render_to_image.*
> > ---
> > src/intel/vulkan/genX_cm
On Thu, 2017-02-23 at 12:10 +0100, Iago Toral wrote:
> On Wed, 2017-02-22 at 09:38 -0800, Jason Ekstrand wrote:
> >
> > On Wed, Feb 22, 2017 at 6:45 AM, Iago Toral Quiroga > co
> > m> wrote:
> > >
> > > This fixes a number of new CTS
I think the comment affects the hunk after these checks, so maybe
removing the checks after the comment makes more sense?
Either way:
Reviewed-by: Iago Toral Quiroga
On Fri, 2017-02-24 at 15:10 +0200, Juha-Pekka Heikkila wrote:
> On both sides of the comment on what's being checked are
On Thu, 2015-07-23 at 11:40 -0700, Anuj Phogat wrote:
> On Wed, Jul 22, 2015 at 7:10 AM, Iago Toral wrote:
> > The problem here is that the _mesa_meta_BlitFramebuffer is not setting
> > G/B channels to 0.0 when doing Luminance/Intensity to RGBA conversions,
> > so why not
On Fri, 2015-07-24 at 16:18 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > When we have code such as this:
> >
> > mov vgrf1.0.x:F, vgrf2.:F
> > mov vgrf3.0.x:F, vgrf1.:F
> > ...
> > mov vgrf3.0.x:F, vgrf1.:F
> >
&
On Fri, 2015-07-24 at 16:20 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > Larger registers should have been moved to scratch (like GRF array access)
> > or split to size 1 by the split_virtual_grfs pass.
>
> Not necessarily. split_virtual_grfs() won&
On Tue, 2015-07-28 at 18:17 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > Link to v1:
> > http://lists.freedesktop.org/archives/mesa-dev/2015-July/089766.html
> >
> > Changes after review (Curro)
> > - Drop the patch that asserted
Funny, we had 3 instances of the same function with the same
implementation :), there is still util_is_power_of_two in Gallium btw.
Reviewed-by: Iago Toral Quiroga
On Tue, 2015-07-28 at 16:48 -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/common/me
On Sun, 2015-07-26 at 18:35 +1000, Timothy Arceri wrote:
> Since commit c0cd5b var->data.binding was being used as a replacement
> for atomic buffer index, but they don't have to be the same value they
> just happen to end up the same when binding is 0.
>
> Now we store atomic buffer index in the
r_name' is associated with an input with a non-zero stream,
which is not allowed"
Iago
> Marek
>
> On Wed, Jun 18, 2014 at 11:51 AM, Iago Toral Quiroga
> wrote:
> > Outputs that are linked to inputs in the next stage must be output to
> > stream 0,
&
On Thu, 2015-07-30 at 09:43 +0200, Marek Olšák wrote:
> On Thu, Jul 30, 2015 at 8:49 AM, Iago Toral wrote:
> > On Wed, 2015-07-29 at 21:58 +0200, Marek Olšák wrote:
> >> Hi,
> >>
> >> Where does the spec say we should fail to link? I don't see such a
>
On Wed, 2015-07-29 at 15:16 -0700, Ian Romanick wrote:
> On 07/29/2015 07:01 AM, Samuel Iglesias Gonsalvez wrote:
> > From: Iago Toral Quiroga
> >
> > We will need this later on when we implement proper support for precision
> > qualifiers in the drivers and also
On Wed, 2015-07-29 at 15:21 -0700, Ian Romanick wrote:
> On 07/29/2015 07:01 AM, Samuel Iglesias Gonsalvez wrote:
> > From: Iago Toral Quiroga
> >
> > Currently, we only consider precision qualifiers at compile-time. This patch
> > adds precision information to ir_vari
On Thu, 2015-07-30 at 15:58 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > ---
> > src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 +-
> > src/mesa/drivers/dri/i965/brw_vec4.cpp| 2 +-
> > src/mesa/drivers/dri/i965/intel_debu
On Thu, 2015-07-30 at 16:27 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > In theory, GRF array access should have been moved to scratch by the time
> > we got here, so this should never happen. A full piglit run forcing
> > spilling of all registers se
On Thu, 2015-07-30 at 17:14 +0300, Francisco Jerez wrote:
> Francisco Jerez writes:
>
> > Iago Toral Quiroga writes:
> >
> >> When we have code such as this:
> >>
> >> mov vgrf1.0.x:F, vgrf2.:F
> >> mov vgrf3.0.x:F, vgrf1.:F
>
On Thu, 2015-07-30 at 16:33 +0300, Francisco Jerez wrote:
> Francisco Jerez writes:
>
> > Iago Toral Quiroga writes:
> >
> >> Previous patches made it so that we do not need to unspill the same vgrf
> >> with every instruction as long as these instructions co
On Thu, 2015-07-30 at 17:08 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > When we have code such as this:
> >
> > mov vgrf1.0.x:F, vgrf2.:F
> > mov vgrf3.0.x:F, vgrf1.:F
> > ...
> > mov vgrf3.0.x:F, vgrf1.:F
> >
&
On Fri, 2015-07-31 at 13:12 +0300, Francisco Jerez wrote:
> Iago Toral writes:
>
> > On Thu, 2015-07-30 at 17:08 +0300, Francisco Jerez wrote:
> >> Iago Toral Quiroga writes:
> >>
> >> > When we have code such as this:
> >> >
> >>
On Fri, 2015-07-31 at 13:12 +0300, Francisco Jerez wrote:
> Iago Toral writes:
>
> > On Thu, 2015-07-30 at 17:08 +0300, Francisco Jerez wrote:
> >> Iago Toral Quiroga writes:
> >>
> >> > When we have code such as this:
> >> >
> >>
On Thu, 2015-07-30 at 17:08 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > When we have code such as this:
> >
> > mov vgrf1.0.x:F, vgrf2.:F
> > mov vgrf3.0.x:F, vgrf1.:F
> > ...
> > mov vgrf3.0.x:F, vgrf1.:F
> >
&
Reviewed-by: Iago Toral Quiroga
On Mon, 2015-08-03 at 16:36 -0700, Eric Anholt wrote:
> I lazily generated some of these in VC4 NIR lowering.
> ---
> src/glsl/nir/nir_opt_algebraic.py | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/glsl/nir/nir_opt_algebraic.py
ted programs: 1671486 -> 1653025 (-1.10%)
> helped:5248
> HURT: 12868
> GAINED:0
> LOST: 0
>
> We can probably whittle that down pretty quick.
>
On Tue, 2015-08-04 at 14:08 -0700, Jordan Justen wrote:
> On 2015-07-14 00:46:10, Iago Toral Quiroga wrote:
> > From: Samuel Iglesias Gonsalvez
> >
> > They only can be defined in the last position of the shader
> > storage blocks.
> >
> > When an unsized
On Tue, 2015-08-04 at 16:04 -0700, Jordan Justen wrote:
> On 2015-08-04 15:12:06, Jordan Justen wrote:
> > On 2015-07-14 00:46:11, Iago Toral Quiroga wrote:
> > > From: Samuel Iglesias Gonsalvez
> > >
> > > It also creates unop and triop expressions to te
On Tue, 2015-08-04 at 14:08 -0700, Jordan Justen wrote:
> On 2015-07-14 00:46:10, Iago Toral Quiroga wrote:
> > From: Samuel Iglesias Gonsalvez
> >
> > They only can be defined in the last position of the shader
> > storage blocks.
> >
> > When an unsized
On Thu, 2015-07-30 at 12:33 +0200, Iago Toral wrote:
> On Wed, 2015-07-29 at 15:21 -0700, Ian Romanick wrote:
> > On 07/29/2015 07:01 AM, Samuel Iglesias Gonsalvez wrote:
> > > From: Iago Toral Quiroga
> > >
> > > Currently, we only consider precis
Reviewed-by: Iago Toral Quiroga
On Wed, 2015-08-05 at 20:31 +1000, Timothy Arceri wrote:
> Cc: Iago Toral Quiroga
> Cc: Jason Ekstrand
> ---
> src/glsl/nir/nir_lower_io.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/src/glsl/nir/nir_lower_io.c b/src/gl
On Wed, 2015-08-05 at 20:04 +1000, Timothy Arceri wrote:
> On Wed, 2015-08-05 at 10:30 +0200, Iago Toral Quiroga wrote:
> > ---
> > src/glsl/ast_to_hir.cpp | 9 -
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/src/glsl/ast_to_
On Wed, 2015-08-05 at 13:38 +0300, Francisco Jerez wrote:
> Iago Toral writes:
>
> > On Tue, 2015-08-04 at 16:04 -0700, Jordan Justen wrote:
> >> On 2015-08-04 15:12:06, Jordan Justen wrote:
> >> > On 2015-07-14 00:46:11, Iago Toral Quiroga wrote:
> &g
On Wed, 2015-08-05 at 22:22 +1000, Timothy Arceri wrote:
> On Wed, 2015-08-05 at 13:45 +0200, Iago Toral wrote:
> > On Wed, 2015-08-05 at 20:04 +1000, Timothy Arceri wrote:
> > > On Wed, 2015-08-05 at 10:30 +0200, Iago Toral Quiroga wrote:
> > > > ---
> &
On Thu, 2015-08-06 at 08:53 +0300, Tapani Pälli wrote:
> Reviewed-by: Tapani Pälli
>
> On 08/05/2015 11:30 AM, Iago Toral Quiroga wrote:
> > From: Samuel Iglesias Gonsalvez
> >
> > According to ARB_uniform_buffer_object spec:
> >
> > "If the parameter
On Wed, 2015-08-05 at 12:23 -0400, Ilia Mirkin wrote:
> On Wed, Aug 5, 2015 at 4:30 AM, Iago Toral Quiroga wrote:
> > These handle querying the buffer name attached to a giving binding point
> > as well as the start offset and size of that buffer.
> > ---
> >
On Wed, 2015-08-05 at 11:59 -0700, Connor Abbott wrote:
> On Wed, Aug 5, 2015 at 1:30 AM, Iago Toral Quiroga wrote:
> > From: Samuel Iglesias Gonsalvez
> >
> > Signed-off-by: Samuel Iglesias Gonsalvez
> > ---
> > src/glsl/nir/glsl_to_nir.cpp | 10 ++
&
On Wed, 2015-08-05 at 12:24 -0700, Connor Abbott wrote:
> On Wed, Aug 5, 2015 at 1:30 AM, Iago Toral Quiroga wrote:
> > The original GLSL IR intrinsics have been lowered to an internal
> > version that accepts a block index and an offset instead of a
> > SSBO reference.
>
On Wed, 2015-08-05 at 12:17 -0700, Connor Abbott wrote:
> On Wed, Aug 5, 2015 at 1:30 AM, Iago Toral Quiroga wrote:
> > ---
> > src/glsl/nir/glsl_to_nir.cpp | 36
> > src/glsl/nir/nir_intrinsics.h | 12 ++--
> > 2 files c
On Thu, 2015-08-06 at 11:06 -0700, Connor Abbott wrote:
> On Thu, Aug 6, 2015 at 12:30 AM, Iago Toral wrote:
> > On Wed, 2015-08-05 at 12:17 -0700, Connor Abbott wrote:
> >> On Wed, Aug 5, 2015 at 1:30 AM, Iago Toral Quiroga
> >> wrote:
> >> > ---
>
On Thu, 2015-08-06 at 18:27 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > If we have spilled/unspilled a register in the current instruction, avoid
> > emitting unspills for the same register in the same instruction or
> > consecutive
> > inst
On Fri, 2015-08-07 at 07:43 +0200, Iago Toral wrote:
> On Thu, 2015-08-06 at 11:06 -0700, Connor Abbott wrote:
> > On Thu, Aug 6, 2015 at 12:30 AM, Iago Toral wrote:
> > > On Wed, 2015-08-05 at 12:17 -0700, Connor Abbott wrote:
> > >> On Wed, Aug 5, 2015
On Wed, 2015-08-05 at 10:29 +0200, Iago Toral Quiroga wrote:
> From: Francisco Jerez
>
> These functions handle the conversion of a vec4 into the form expected
> by the dataport unit in message and message return payloads. The
> conversion is not always trivial because some
On Fri, 2015-08-07 at 14:14 +0300, Francisco Jerez wrote:
> Iago Toral writes:
>
> > On Thu, 2015-08-06 at 18:27 +0300, Francisco Jerez wrote:
> >> Iago Toral Quiroga writes:
> >>
> >> > If we have spilled/unspilled a register in the current instructi
Reviewed-by: Iago Toral Quiroga
El 2015-08-11 14:25, Oded Gabbay escribió:
On Mon, Aug 10, 2015 at 9:50 AM, Jason Ekstrand
wrote:
The swizzle defines where in the format you should look for any given
channel. When we flip the format around for BE targets, we need to
change
the destinations
Reviewed-by: Iago Toral Quiroga
El 2015-08-08 18:04, Jason Ekstrand escribió:
Cc: Iago Toral
Cc: Oded Gabbay
---
src/mesa/main/formats.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c
index baeb1bf..d927073 100644
Reviewed-by: Iago Toral Quiroga
El 2015-08-12 10:24, Tapani Pälli escribió:
Extension spec originally required 2^24 but 2^27 is the minimum value
required by OpenGL 4.5 and OpenGL ES 3.1 specifications.
Fixes:
ES31-CTS.shader_storage_buffer_object.basic-max
Signed-off-by: Tapani Pälli
emory qualifier parsing. I wrote a Piglit test that
fails with these changes (I tested against
itoral-ARB_shader_storage_buffer_object-v4.1 branch), here:
http://lists.freedesktop.org/archives/piglit/2015-August/016777.html
On 08/05/2015 11:30 AM, Iago Toral Quiroga wrote:
---
src/glsl/glsl_lex
Hey,
On Tue, 2015-08-18 at 12:52 +1000, Dave Airlie wrote:
> Hey,
>
> while running CTS under valgrind I got to see a lot of
>
> ==32256== Invalid read of size 2
> ==32256==at 0x5B53F07: convert_ushort (format_utils.c:1155)
> ==32256==by 0x5B8523A: _mesa_swizzle_and_convert (format_utils
On Tue, 2015-09-01 at 12:34 +0200, Iago Toral wrote:
> Hey,
>
> On Tue, 2015-08-18 at 12:52 +1000, Dave Airlie wrote:
> > Hey,
> >
> > while running CTS under valgrind I got to see a lot of
> >
> > ==32256== Invalid read of size 2
> > ==32256==
On Tue, 2016-09-13 at 22:12 -0700, Francisco Jerez wrote:
> Iago Toral writes:
>
> >
> > On Mon, 2016-09-12 at 14:05 -0700, Francisco Jerez wrote:
> > >
> > > Iago Toral Quiroga writes:
> > >
> > > >
> > > >
> > &g
On Tue, 2016-09-13 at 22:24 -0700, Francisco Jerez wrote:
> Iago Toral writes:
>
> >
> > On Mon, 2016-09-12 at 14:19 -0700, Francisco Jerez wrote:
> > >
> > > Iago Toral Quiroga writes:
> > >
> > > >
> > > &
On Wed, 2016-08-17 at 14:16 -0700, Francisco Jerez wrote:
> Iago Toral writes:
>
> >
> > On Tue, 2016-08-02 at 18:40 -0700, Francisco Jerez wrote:
> > >
> > > Iago Toral Quiroga writes:
> > >
> > > >
> > > >
Reviewed-by: Iago Toral Quiroga
On Tue, 2016-10-04 at 12:03 +1100, Timothy Arceri wrote:
> Fixes a bunch of warnings in 32-bit builds.
> ---
> src/intel/tools/aubinator.c | 17 +
> src/intel/tools/decoder.c | 7 ---
> 2 files changed, 13 insertions(+
The series is:
Reviewed-by: Iago Toral Quiroga
On Tue, 2016-10-04 at 11:15 +1100, Timothy Arceri wrote:
> This fixes an unused variable warning on release builds.
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/sr
On Tue, 2016-10-04 at 22:38 +1100, Timothy Arceri wrote:
> On Tue, 2016-10-04 at 10:33 +0200, Iago Toral wrote:
> >
> > The series is:
> >
> > Reviewed-by: Iago Toral Quiroga
> Thanks for taking a look. Are you happy with me changing patch 1 and
> 4
>
For the series:
Reviewed-by: Iago Toral Quiroga
On Tue, 2016-10-04 at 15:37 -0700, Chad Versace wrote:
> I'm preparing to implement EGL_ANDROID_native_fence_sync, and I
> wanted
> to land these fixes and cleanups before doing the real work.
>
> Patch 1 is a bugfix. T
Reviewed-by: Iago Toral Quiroga
On Fri, 2016-10-07 at 17:12 -0700, Ian Romanick wrote:
> From: Ian Romanick
>
> This was found partially by inspection and partially by hitting a
> problem while working on nir_op_pack_int64_2x32_split. The code
> previously would 'contin
Reviewed-by: Iago Toral Quiroga
On Mon, 2016-10-10 at 09:49 +0300, Tapani Pälli wrote:
> Patch changes function to use _mesa_lookup_shader_program_err both
> in TransformFeedbackVaryings and GetTransformFeedbackVarying that
> handles errors correctly for invalid values of shade
SSA
> > > value.
> > >
> > > Signed-off-by: Ian Romanick
> > > Cc: mesa-sta...@lists.freedesktop.org
> > > Cc: Iago Toral Quiroga
> > > ---
> > > src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 +-
> > > 1 file changed, 1 inse
On Tue, 2016-08-02 at 18:27 -0700, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> >
> > ---
> > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 18 ++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/src/mesa/driver
On Tue, 2016-08-02 at 18:40 -0700, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> >
> > ---
> > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8 +---
> > 1 file changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/src/mesa/driver
On Wed, 2016-08-03 at 13:28 -0700, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> >
> > Gen7 hardware does not support double immediates so these need
> > to be moved in 32-bit chunks to a regular vgrf instead. Instead
> > of doing this every time we
On Wed, 2016-08-17 at 15:15 -0700, Francisco Jerez wrote:
> Iago Toral writes:
>
> >
> > On Tue, 2016-08-02 at 18:27 -0700, Francisco Jerez wrote:
> > >
> > > Iago Toral Quiroga writes:
> > >
> > > >
> > > >
On Wed, 2016-08-17 at 15:15 -0700, Francisco Jerez wrote:
> Iago Toral writes:
>
> >
> > On Tue, 2016-08-02 at 18:27 -0700, Francisco Jerez wrote:
> > >
> > > Iago Toral Quiroga writes:
> > >
> > > >
> > > >
On Thu, 2016-08-18 at 11:57 +0300, Tapani Pälli wrote:
> Implementation previously used case value itself as the key, however
> afterhash implementation change by ee02a5e we cannot use 0 as key.
> Patch uses _mesa_hash_data to formulate a suitable key for this hash.
>
> Signed-off-by: Tapani Pälli
Reviewed-by: Iago Toral Quiroga
On Wed, 2016-08-17 at 11:54 -0700, Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_cfg.cpp | 10 ++
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp
> b/src/mes
On Wed, 2016-08-17 at 11:54 -0700, Matt Turner wrote:
> The basic block following a control flow structure like an infinite
> loop
> will be unreachable. Ignore any non-control-flow instructions in it
> since they can have no effect on the program.
If the block is unreachable control-flow instruct
On Mon, 2016-08-08 at 15:58 -0700, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> >
> > ---
> > src/mesa/drivers/dri/i965/brw_disasm.c | 8 +++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/src/mesa/drivers/dr
On Mon, 2016-08-08 at 15:30 -0700, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> >
> > ---
> > src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
&g
On Thu, 2016-08-18 at 14:25 +0300, Tapani Pälli wrote:
> On 08/18/2016 01:08 PM, Iago Toral wrote:
> >
> > On Thu, 2016-08-18 at 11:57 +0300, Tapani Pälli wrote:
> > >
> > > Implementation previously used case value itself as the key,
> > > howeve
On Mon, 2016-08-08 at 15:26 -0700, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> >
> > From the HSW PRM, Command Reference, QtrCtrl:
> >
> > "NibCtrl is only allowed for SIMD4 instructions with a DF
> > (Double Float)
> > s
_LOG_LENGTH , the length of the info log,
> including
> a null terminator, is returned. If there is no info log, zero is
> returned."
Reviewed-by: Iago Toral Quiroga
> Signed-off-by: Tapani Pälli
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97321
> ---
> src/m
On Thu, 2016-08-18 at 16:16 -0700, Francisco Jerez wrote:
> Iago Toral writes:
>
> >
> > On Mon, 2016-08-08 at 15:58 -0700, Francisco Jerez wrote:
> > >
> > > Iago Toral Quiroga writes:
> > >
> > > >
> > >
On Fri, 2016-08-19 at 08:50 +0200, Iago Toral wrote:
> On Thu, 2016-08-18 at 12:08 -0700, Francisco Jerez wrote:
> >
> > Iago Toral writes:
> >
> > >
> > >
> > > On Wed, 2016-08-17 at 15:15 -0700, Francisco Jerez wro
On Thu, 2016-08-18 at 12:08 -0700, Francisco Jerez wrote:
> Iago Toral writes:
>
> >
> > On Wed, 2016-08-17 at 15:15 -0700, Francisco Jerez wrote:
> > >
> > > Iago Toral writes:
> > >
> > > >
> > > &
Reviewed-by: Iago Toral Quiroga
On Fri, 2016-08-19 at 10:39 +0300, Tapani Pälli wrote:
> (warning: ‘surftype’ may be used uninitialized ...)
>
> Signed-off-by: Tapani Pälli
> ---
> src/mesa/drivers/dri/i965/gen6_blorp.c | 2 ++
> src/mesa/drivers/dri/i965/gen7_blorp.c
On Wed, 2016-08-03 at 14:32 -0700, Francisco Jerez wrote:
> Iago Toral Quiroga writes:...)writes:...)
(...)
> > + return lo)+}++bool+vec4_visitor::lower_simd_width()
> > +{
> > + bool progress = false;
> > +
> > + foreach_block_and_inst_safe(b
hat I'll move the switch statement to another helper that takes a
backend_reg as input parameter and call that from byte_offset.
Iago
> --Michael
>
> Am 23.08.2016 um 10:24 schrieb Iago Toral Quiroga:
> >
> > This will make it more consistent with the FS implementatio
On Tue, 2016-08-23 at 12:58 -0700, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> >
> > So we can access it in the vec4 backend to handle byte offsets into
> > registers.
> This change has deep implications in the meaning of the vec4 register
> objects
On Wed, 2016-08-24 at 18:51 -0700, Francisco Jerez wrote:
> Iago Toral writes:
>
> >
> > On Tue, 2016-08-23 at 12:58 -0700, Francisco Jerez wrote:
> > >
> > > Iago Toral Quiroga writes:
> > >
> > > >
> > > >
&
Reviewed-by: Iago Toral Quiroga
On Mon, 2016-08-29 at 19:16 -0700, Kenneth Graunke wrote:
> Caught by Coverity. Likely fixes real issues if an output component
> is not present.
>
> CID: 1372278
> Signed-off-by: Kenneth Graunke
> ---
> src/compiler/glsl/lower_blend_equa
I think we might also be missing a few _NEW_POLYGON flags which I note
below, otherwise:
Reviewed-by: Iago Toral Quiroga
On Mon, 2016-08-29 at 15:05 -0700, Kenneth Graunke wrote:
> calculate_attr_overrides() uses is_drawing_points(), which depends
> on tessellation and geometry program
Reviewed-by: Iago Toral Quiroga
On Mon, 2016-08-29 at 15:05 -0700, Kenneth Graunke wrote:
> State upload code should use prog_data rather than poking at core
> Mesa shader data structures wherever possible.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965
On Tue, 2016-08-30 at 21:50 -0700, Kenneth Graunke wrote:
> calculate_attr_overrides() uses is_drawing_points(), which depends
> on tessellation and geometry program state, as well as polygon state.
>
> v2: Add missing _NEW_POLYGON as well. Caught by Iago Toral.
>
> Sign
n6_clip_state
> atom because it doesn't care about early culling, but it also needs
> BRW_NEW_TES_PROG_DATA, which was missing.
Cool! :)
Reviewed-by: Iago Toral Quiroga
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_state.h| 1 -
> sr
ontrol flow was bogus: halt, cont,
> break
> cannot be compacted because they have both JIP and UIP. Instead, we
> should never see a compacted instruction in this code at all.
Compaction is the last thing we do in the generators right after we
call brw_set_uip_jip(), so this should be
On Wed, 2016-09-07 at 18:48 -0700, Francisco Jerez wrote:
(...)
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
> b/src/mesa/drivers/dri/i965/brw_shader.cpp
> index ea39252..29435f6 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
> @@
On Wed, 2016-09-07 at 18:48 -0700, Francisco Jerez wrote:
(...)
> src/mesa/drivers/dri/i965/brw_ir_vec4.h| 4 +-
> src/mesa/drivers/dri/i965/brw_vec4.cpp | 61
> --
> .../drivers/dri/i965/brw_vec4_cmod_propagation.cpp | 2 +-
> .../drivers/dri/i965/brw
On Wed, 2016-09-07 at 18:48 -0700, Francisco Jerez wrote:
> ---
> src/mesa/drivers/dri/i965/brw_shader.cpp | 2 --
> src/mesa/drivers/dri/i965/brw_shader.h | 15 ++-
> 2 files changed, 2 insertions(+), 15 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
> b/sr
On Wed, 2016-09-07 at 18:48 -0700, Francisco Jerez wrote:
> The fs_reg::subreg_offset and ::offset fields are now redundant, the
> sub-GRF offset can just be added to the single ::offset field
> expressed in byte units. The current subreg_offset value can be
> recovered by applying the following r
On Wed, 2016-09-07 at 18:48 -0700, Francisco Jerez wrote:
(...)
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index 12ab7b3..a678351 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/b
On Wed, 2016-09-07 at 18:48 -0700, Francisco Jerez wrote:
> This is in preparation for dropping vec4_instruction::regs_read and
> ::regs_written in favor of more accurate alternatives expressed in
> byte units. The main reason these wrappers are useful is that a
> number of optimization passes imp
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