Re: [Mesa-dev] [PATCH] HUD: Add support for block I/O, network I/O and lmsensor stats

well it won't for your GPU, it is currently Fermi (GF100+) only. I guess I will add support for it later then 2016-09-13 13:14 GMT+02:00 Steven Toth : >>> Ahh, my nouveau card must be too old then. I only get temperature from >>> it. I have a 6yo(?) 8800 GTS. That being said - it services the >>>

Re: [Mesa-dev] Mesa 13.0.0 release plan (Was Re: Mesa 12.1.0 release plan (Was Re: Next Mesa release, anyone?))

2016-09-30 16:57 GMT+02:00 Ian Romanick : > On 09/30/2016 06:23 AM, Brian Paul wrote: >> On 09/30/2016 04:59 AM, Emil Velikov wrote: >>> On 30 September 2016 at 03:31, Timothy Arceri >>> wrote: On Thu, 2016-09-29 at 19:17 -0700, Jason Ekstrand wrote: On Sep 29, 2016 5:14 PM, "Timoth

[Mesa-dev] [PATCH] nv50/ra: let simplify return an error and handle that

fixes a crash in the case simplify reports an error Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers

[Mesa-dev] [PATCH] nv50/ir: optimize sub(a, 0) to a

25837792 -> 25837192 (-0.00%) localgpr inst bytes helped 0 0 33 33 hurt 0 0 0 0 Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 3

[Mesa-dev] [PATCH] nv50/ir: start LocalCSE with getFirst to merge PHI instructions

lgpr inst bytes helped 0 25 100 100 hurt 0 0 0 0 Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Mesa-dev] [PATCH 4/6] nv50/ir: rework postraconstantfolding pass

we might want to add more folding passes here, so make it a bit more generic Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 124 ++--- 1 file changed, 62 insertions(+), 62 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen

[Mesa-dev] [PATCH 5/6] nv50/ra: always prefer def == src2 for mad/sad

just little random noise in shader-db will help in the next patch Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers

[Mesa-dev] [PATCH 6/6] nv50/ir: implement mad post ra folding for nvc0+

0 0 0 Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 65 -- 1 file changed, 60 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/

[Mesa-dev] [PATCH 0/6] nv50/ir: PostRaConstantFolding improvements

This series reworks the structure of the pass to make it easier to add more optimisations to it. Also implements folding for mad on gf100+ ISAs to reduce instruction count by ~0.37% I can only test it on a gk106 for now. Karol Herbst (6): nv50/ir: add LIMM form of mad to gk110 nv50/ir: add

[Mesa-dev] [PATCH 1/6] nv50/ir: add LIMM form of mad to gk110

Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 49 ++ 1 file changed, 32 insertions(+), 17 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp

[Mesa-dev] [PATCH 3/6] nv50/ir: replace post_ra_dead by Instruction::isDead

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir.h| 2 +- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 20 +++- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h b/src

[Mesa-dev] [PATCH 2/6] nv50/ir: add LIMM form of mad to gm107

Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 32 -- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp

Re: [Mesa-dev] [PATCH 1/6] nv50/ir: add LIMM form of mad to gk110

hings and mupuf will appreciate. :) > I think you read the patches in the wrong order. The two first patches are the changes in the emiter. > On 10/08/2016 05:43 PM, Karol Herbst wrote: >> >> Signed-off-by: Karol Herbst >> --- >> .../drivers/nouveau/codegen/nv50_ir_emit_g

[Mesa-dev] [PATCH] gf100/ir: limms on gm107 are 19 bit

the emit code uses 19 everywhere, so we should let CodeEmitterGM107::longIMMD and TargetNVC0::insnCanLoad check against this too Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 6 +++--- src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp

Re: [Mesa-dev] [PATCH] gf100/ir: limms on gm107 are 19 bit

tIMMD and it indeed does some magic there. > > On Sat, Oct 8, 2016 at 3:23 PM, Karol Herbst wrote: >> the emit code uses 19 everywhere, so we should let >> CodeEmitterGM107::longIMMD and TargetNVC0::insnCanLoad check against >> this too >> >> Signed-off-by: Karol

Re: [Mesa-dev] [PATCH] nv50/ir: optimize ADD(SHL(a, b), c) to SHLADD(a, b, c)

looks great, a few comments below 2016-10-08 21:55 GMT+02:00 Samuel Pitoiset : > total instructions in shared programs :2286901 -> 2284473 (-0.11%) > total gprs used in shared programs:335256 -> 335273 (0.01%) > total local used in shared programs :31968 -> 31968 (0.00%) > >

Re: [Mesa-dev] [PATCH 2/6] nv50/ir: add LIMM form of mad to gm107

2016-10-08 18:12 GMT+02:00 Samuel Pitoiset : > Usually we prefix with gm107/ir, gk110/ir, etc... > > More comments below. > > On 10/08/2016 05:43 PM, Karol Herbst wrote: >> >> Signed-off-by: Karol Herbst >> --- >> .../drivers/nouv

Re: [Mesa-dev] [PATCH 3/6] nv50/ir: replace post_ra_dead by Instruction::isDead

2016-10-08 18:39 GMT+02:00 Samuel Pitoiset : > > > On 10/08/2016 05:43 PM, Karol Herbst wrote: >> >> Signed-off-by: Karol Herbst >> --- >> src/gallium/drivers/nouveau/codegen/nv50_ir.h| 2 +- >> .../drivers/nouveau/codegen/nv50_ir_peephole.cpp

[Mesa-dev] [PATCH v2 1/6] gk110/ir: add LIMM form of mad

v2: renamed commit reordered modifiers add assert(dst == src2) Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 50 ++ 1 file changed, 33 insertions(+), 17 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen

[Mesa-dev] [PATCH v2 3/6] nv50/ir: replace post_ra_dead by Instruction::isDead

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir.h| 2 +- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 20 +++- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h b/src

[Mesa-dev] [PATCH v2 0/6] nv50/ir: PostRaConstantFolding improvements

inst bytes helped 0 2640934093 hurt 0 20 61 61 Karol Herbst (6): gk110/ir: add LIMM form of mad gm107/ir: add LIMM form of mad nv50/ir: replace post_ra_dead by Instruction::isDead nv5

[Mesa-dev] [PATCH v2 4/6] nv50/ir: restructure postraconstantfolding pass

we might want to add more folding passes here, so make it a bit more generic v2: leave the comment and reword commit message Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 120 +++-- 1 file changed, 62 insertions(+), 58 deletions(-) diff

[Mesa-dev] [PATCH v2 6/6] nv50/ra: always prefer def == src2 for mad/sad

gt; 25743616 (-0.12%) localgpr inst bytes helped 0 2617361736 hurt 0 20 78 78 v2: reorder to show the benefit of this patch Signed-off-by: Karol Herbst --- src/gallium/drivers/nou

[Mesa-dev] [PATCH v2 5/6] nv50/ir: implement mad post ra folding for nvc0+

0 0 0 v2: removed TODO reorderd to show changes without RA modification removed stale debugging print() call Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 64 +++--- 1 file changed, 57 insertions(+), 7 deletions

[Mesa-dev] [PATCH v2 2/6] gm107/ir: add LIMM form of mad

v2: renamed commit reordered modifiers add assert(dst == src2) Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 35 -- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen

Re: [Mesa-dev] [PATCH] nv50/ir: optimize ADD(SHL(a, b), c) to SHLADD(a, b, c)

2016-10-09 13:58 GMT+02:00 Samuel Pitoiset : > > > On 10/08/2016 10:04 PM, Karol Herbst wrote: >> >> looks great, a few comments below > > > Thanks! > >> >> 2016-10-08 21:55 GMT+02:00 Samuel Pitoiset : >>> >>> total instructions in s

Re: [Mesa-dev] [PATCH] nv50/ir: optimize ADD(SHL(a, b), c) to SHLADD(a, b, c)

2016-10-09 21:34 GMT+02:00 Ilia Mirkin : > On Sun, Oct 9, 2016 at 3:28 PM, Karol Herbst wrote: >> 2016-10-09 13:58 GMT+02:00 Samuel Pitoiset : >>> >>> >>> On 10/08/2016 10:04 PM, Karol Herbst wrote: >>>> >>>> looks great, a few comments

[Mesa-dev] [PATCH 4/4] nv50: add PostRADualIssue Pass

=640: inst_executed: 1.03G inst_issued1: 614M -> 500M inst_issued2: 213M -> 271M score: 1021 -> 1056 Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 59 ++ 1 file changed, 59 insertions(+) diff --git a/src/gallium/drivers/nouvea

[Mesa-dev] [PATCH 0/4] nvc0: improve dual issueing

compiler pass aren't as big as with it. Karol Herbst (4): nv50: add target->hasDualIssueing() nvc0/ir: don't dual issue instructions which depend on each other nvc0/ir: dual issue two min/max instructions nv50: add PostRADualIssue Pass src/gallium/drivers/nouveau/codege

[Mesa-dev] [PATCH 3/4] nvc0/ir: dual issue two min/max instructions

> 1030 with dual_issue pass: inst_executed: 1.03G inst_issued1: 535M -> 500M inst_issued2: 254M -> 271M score: 1052 -> 1056 Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp| 14 -- 1 file changed, 12 insertions(+), 2 deletions(-)

[Mesa-dev] [PATCH 2/4] nvc0/ir: don't dual issue instructions which depend on each other

no changes without a dual_issue pass changes with for ./GpuTest /test=pixmark_piano /benchmark /no_scorebox /msaa=0 /benchmark_duration_ms=6 /width=1024 /height=640: inst_executed: 1.03G inst_issued1: 538M -> 535M inst_issued2: 251M -> 254M score: 1038 -> 1052 Signed-off-by: Kar

[Mesa-dev] [PATCH 1/4] nv50: add target->hasDualIssueing()

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_target.h| 1 + src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 7 ++- src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.h | 1 + 3 files changed, 8 insertions(+), 1 deletion(-) diff

Re: [Mesa-dev] [PATCH 3/4] nvc0/ir: dual issue two min/max instructions

2016-08-13 17:43 GMT+02:00 Tobias Klausmann : > Hi Karol, > > one question inline. > > > On 13.08.2016 12:02, Karol Herbst wrote: >> >> min/max pairs can be dual issued on Kepler1 >> >> changes for ./GpuTest /test=pixmark_piano /benchmark /no_scorebox /msa

Re: [Mesa-dev] [PATCH 2/4] nvc0/ir: don't dual issue instructions which depend on each other

2016-08-13 18:17 GMT+02:00 Ilia Mirkin : > On Sat, Aug 13, 2016 at 6:02 AM, Karol Herbst wrote: >> no changes without a dual_issue pass >> >> changes with for ./GpuTest /test=pixmark_piano /benchmark /no_scorebox >> /msaa=0 >> /benchmark_duration

Re: [Mesa-dev] [PATCH 2/4] nvc0/ir: don't dual issue instructions which depend on each other

2016-08-13 19:27 GMT+02:00 Ilia Mirkin : > On Sat, Aug 13, 2016 at 1:24 PM, karol herbst wrote: >> 2016-08-13 18:17 GMT+02:00 Ilia Mirkin : >>> On Sat, Aug 13, 2016 at 6:02 AM, Karol Herbst wrote: >>>> no changes without a dual_issue pass >>>> >>&

Re: [Mesa-dev] [PATCH 4/4] nv50: add PostRADualIssue Pass

2016-08-13 21:33 GMT+02:00 Ilia Mirkin : > On Sat, Aug 13, 2016 at 3:26 PM, Connor Abbott wrote: >> So, I don't know much about how nv50 ir works, but to me this just >> seems like a pretty slow implementation of a very limited instruction >> scheduler. In addition to the runtime complexity proble

[Mesa-dev] [PATCH] nvc0/ir: joins get a sched of 0x2f

slightly improves performance for GpuTest /test=pixmark_piano /benchmark /no_scorebox /msaa=0 /benchmark_duration_ms=6 /width=1024 /height=640 score: 1031 -> 1033 observed from the binary generated by nvidia Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/code

Re: [Mesa-dev] [PATCH] HUD: Add support for block I/O, network I/O and lmsensor stats

Hey, nice work regarding the lmsensor bits. But I think it makes sense to also wire the power things in, cause we actually expose them within nouveau. Others might want or actually do the same as well. Many thanks 2016-09-12 20:33 GMT+02:00 Steven Toth : > Three new features: > 1. Disk/block I/O

Re: [Mesa-dev] [PATCH] HUD: Add support for block I/O, network I/O and lmsensor stats

2016-09-12 23:20 GMT+02:00 Steven Toth : >> nice work regarding the lmsensor bits. But I think it makes sense to >> also wire the power things in, cause we actually expose them within >> nouveau. Others might want or actually do the same as well. > > Karol, thank you for your feedback. > > I'm happ

Re: [Mesa-dev] [PATCH] HUD: Add support for block I/O, network I/O and lmsensor stats

2016-09-13 0:15 GMT+02:00 Steven Toth : >> I think you expose Temperature, Voltage and Current. But Nouveau exposes >> Temperature, Voltage, Fan and Power through hwmon. >> >> Read the "power" section here for more info: >> https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface > > Ahh, my

Re: [Mesa-dev] [PATCH 5/5] nv50/ir: detect when a SLCT is equivalent to a SET

On 21 October 2016 8:30:33 a.m. GMT+02:00, Ilia Mirkin wrote: >Signed-off-by: Ilia Mirkin >--- >.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 23 >++ > 1 file changed, 19 insertions(+), 4 deletions(-) > >diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephol

Re: [Mesa-dev] [PATCH] nv50/ir: start LocalCSE with getFirst to merge PHI instructions

l-4.30/execution/built-in-functions/cs-any-bvec4-using-if: fail >> >> Piglit spotted those on GK110, please figure out and send a v2. :) > > > Looks fine now. > > Maybe you can reply and update the shader-db results since I added a bunch > of new shaders from F1, Shadow O

Re: [Mesa-dev] [PATCH v2 2/6] gm107/ir: add LIMM form of mad

2016-10-26 19:20 GMT+02:00 Samuel Pitoiset : > > > On 10/09/2016 11:04 AM, Karol Herbst wrote: >> >> v2: renamed commit >> reordered modifiers >> add assert(dst == src2) >> >> Signed-off-by: Karol Herbst >> --- >>

[Mesa-dev] [PATCH v3 0/6] nv50/ir: PostRaConstantFolding improvements

4591 hurt 0 23 64 64 Karol Herbst (6): nv50/ir: restructure postraconstantfolding pass nv50/ir: implement mad post ra folding for nvc0+ nv50/ra: always prefer def == src2 for mad/sad gk110/ir: add LIMM form of mad gm107/ir: add LIMM form of m

[Mesa-dev] [PATCH v3 3/6] nv50/ra: always prefer def == src2 for mad/sad

localgpr inst bytes helped 0 2619371937 hurt 0 23 81 81 v2: reorder to show the benefit of this patch Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 3 +-- 1

[Mesa-dev] [PATCH v3 1/6] nv50/ir: restructure postraconstantfolding pass

we might want to add more folding passes here, so make it a bit more generic v2: leave the comment and reword commit message Signed-off-by: Karol Herbst Reviewed-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 121 +++-- 1 file changed, 63

[Mesa-dev] [PATCH v3 5/6] gm107/ir: add LIMM form of mad

v2: renamed commit reordered modifiers add assert(dst == src2) v3: reordered modifiers again Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 35 -- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 3 +- 2 files changed, 27

[Mesa-dev] [PATCH v3 6/6] nv50/ir: replace post_ra_dead by Instruction::isDead

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir.h | 2 +- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 24 -- 2 files changed, 9 insertions(+), 17 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h b/src/gallium

[Mesa-dev] [PATCH v3 2/6] nv50/ir: implement mad post ra folding for nvc0+

0 0 0 0 v2: removed TODO reorderd to show changes without RA modification removed stale debugging print() call v3: remove predicate checks enable only for gf100 ISA Signed-off-by: Karol Herbst fixup Signed-off-by: Karol Herbst --- .../drivers/

[Mesa-dev] [PATCH v3 4/6] gk110/ir: add LIMM form of mad

v2: renamed commit reordered modifiers add assert(dst == src2) v3: removed wrong neg mod emission Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 50 ++ .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 2 +- 2 files changed

Re: [Mesa-dev] [PATCH v3 2/6] nv50/ir: implement mad post ra folding for nvc0+

2016-10-30 23:45 GMT+01:00 Matt Turner : > On Sun, Oct 30, 2016 at 2:20 PM, Karol Herbst wrote: >> Signed-off-by: Karol Herbst >> >> fixup >> >> Signed-off-by: Karol Herbst > > Oops. uhh totally missed that, thanks ___

Re: [Mesa-dev] [PATCH] glcpp: initializes version to -1

for reference the bug I've created for this: https://bugs.freedesktop.org/show_bug.cgi?id=97420 and thanks for fixing this 2016-11-04 13:22 GMT+01:00 Juan A. Suarez Romero : > Shader can define #version as an integer, including 0. > > Initializes version to -1 to know later if shader has defined

Re: [Mesa-dev] [PATCH] glcpp: initializes version to -1

2016-11-05 2:50 GMT+01:00 Ian Romanick : > (Sorry about the top post. Sent from my phone.) > > That expression will allow versions like 0130 as valid. If you just want to > allow 0, you need a more complex regular expression. I feel like that's > just a bandage... what about other bad values like

[Mesa-dev] [PATCH v4 0/4] nv50/ir: PostRaConstantFolding improvements

This series reworks the structure of the pass to make it easier to add more optimisations to it. I have to rework the RA commit a bit and the post_ra_dead patch should be submitted on its own. v2: swaped the last two commits v3: reworked order v4: droped last two patches Karol Herbst (4

[Mesa-dev] [PATCH v4 4/4] gm107/ir: add LIMM form of mad

v2: renamed commit reordered modifiers add assert(dst == src2) v3: reordered modifiers again Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 35 -- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 3 +- 2 files changed, 27

[Mesa-dev] [PATCH v4 3/4] gk110/ir: add LIMM form of mad

v2: renamed commit reordered modifiers add assert(dst == src2) v3: removed wrong neg mod emission Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 50 ++ .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 2 +- 2 files changed

[Mesa-dev] [PATCH v4 2/4] nv50/ir: implement mad post ra folding for nvc0+

0 0 0 0 v2: removed TODO reorderd to show changes without RA modification removed stale debugging print() call v3: remove predicate checks enable only for gf100 ISA Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 51 ++

[Mesa-dev] [PATCH v4 1/4] nv50/ir: restructure and rename postraconstantfolding pass

we might want to add more folding passes here, so make it a bit more generic v2: leave the comment and reword commit message v4: rename it to PostRaLoadPropagation Signed-off-by: Karol Herbst Reviewed-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 121

Re: [Mesa-dev] [PATCH v4 4/4] gm107/ir: add LIMM form of mad

Subject: [PATCH v5] gm107/ir: add LIMM form of mad v2: renamed commit reordered modifiers add assert(dst == src2) v3: reordered modifiers again v5: no roudning bit for limms Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 34

Re: [Mesa-dev] [PATCH v4 0/4] nv50/ir: PostRaConstantFolding improvements

no regressions in piglit on my nve6 2016-11-06 15:05 GMT+01:00 Karol Herbst : > This series reworks the structure of the pass to make it easier to add > more optimisations to it. > > I have to rework the RA commit a bit and the post_ra_dead patch should be > submitted on its own.

Re: [Mesa-dev] [PATCH] glcpp: initializes version to -1

2016-11-07 10:05 GMT+01:00 Juan A. Suarez Romero : > On Sat, 2016-11-05 at 10:48 +0100, Karol Herbst wrote: >> 2016-11-05 2:50 GMT+01:00 Ian Romanick : >> > (Sorry about the top post. Sent from my phone.) >> > >> > That expression will allow versions like 01

Re: [Mesa-dev] [PATCH] glcpp: initializes version to -1

2016-11-08 13:35 GMT+01:00 Juan A. Suarez Romero : > On Sat, 2016-11-05 at 10:48 +0100, Karol Herbst wrote: >> "#version 0512": 0:1(10): error: GLSL 3.30 is not supported. >> Supported >> versions are: 1.10, 1.20, 1.30, 1.00 ES, and 3.00 ES >> >> so t

Re: [Mesa-dev] [PATCH 05/12] nir: rename global/local to private/function memory

On Fri, Jan 11, 2019 at 8:50 PM Kenneth Graunke wrote: > > On Friday, January 11, 2019 9:32:20 AM PST Eric Anholt wrote: > > Jason Ekstrand writes: > > > > > On Fri, Jan 11, 2019 at 11:11 AM Kenneth Graunke > > > wrote: > > > > > >> On Friday, January 11, 2019 8:33:41 AM PST Jason Ekstrand wrote

[Mesa-dev] [PATCH] glsl/lower_output_reads: set invariant and precise flags on temporaries

.functional.shaders.invariance.lowp.common_subexpression_2 dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_3 Signed-off-by: Karol Herbst --- src/compiler/glsl/lower_output_reads.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/glsl/lower_output_reads.cpp b/src/compiler/glsl

[Mesa-dev] [PATCH] glsl/lower_output_reads: set invariant and precise flags on temporaries

.functional.shaders.invariance.lowp.common_subexpression_2 dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_3 Signed-off-by: Karol Herbst --- src/compiler/glsl/lower_output_reads.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/glsl/lower_output_reads.cpp b/src/compiler/glsl

Re: [Mesa-dev] [PATCH] nv50,nvc0: mark textures dirty on fb update

Reviewed-by: Karol Herbst On Mon, Jan 21, 2019 at 4:27 AM Ilia Mirkin wrote: > > We may have to flush the cache if there are any textures presently bound > that refer to the outgoing framebuffer. This is only checked at > validation time. > > Fixes a nu

[Mesa-dev] [PATCH v3] nvc0/ir: replace cvt instructions with add to improve shader performance

registers and const memory rework if clauses merge isCvt into this patch Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 + .../drivers/nouveau/codegen/nv50_ir_inlines.h | 17 + .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 64

[Mesa-dev] [PATCH v4] nvc0/ir: replace cvt instructions with add to improve shader performance

registers and const memory rework if clauses merge isCvt into this patch v4: merge isCvt into its use Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 64 +++ .../nouveau/codegen/nv50_ir_lowering_nvc0.h | 1 + 2 files changed, 65 insertions

Re: [Mesa-dev] [PATCH] nvc0/ir: always use CG mode for loads from atomic-only buffers

Reviewed-by: Karol Herbst On Sun, Feb 3, 2019 at 4:10 PM Ilia Mirkin wrote: > > Atomic operations don't update the local cache, which means that we > would have to issue CCTL operations in order to get the updated values. > When we know that a buffer is primarily used for

Re: [Mesa-dev] [PATCH] kmsro: Silence warning if missing

Reviewed-by: Karol Herbst On Thu, Feb 7, 2019 at 11:55 PM Eric Anholt wrote: > > Alyssa Rosenzweig writes: > > > Regardless of whether the build uses kmsro, kmsro is the default driver > > descriptor when the static loader is used. Thus, in an edge case where > > th

[Mesa-dev] [PATCH] WIP nv50/ir: optimize immediates mov to const buffer

some instructions can read from a const buffer but not long immediates, some instructions can take an immediate and a const buffer, but not two immediates. Put immediates we can't load propagate into the driver const buffer, so that shaders can read from there instead doing some movs writing the im

[Mesa-dev] [PATCH 03/34] nv50/ir: move common converter code in base class

v2: remove TGSI related bits Signed-off-by: Karol Herbst Reviewed-by: Pierre Moreau --- src/gallium/drivers/nouveau/Makefile.sources | 2 + .../nouveau/codegen/nv50_ir_from_common.cpp | 107 ++ .../nouveau/codegen/nv50_ir_from_common.h | 58 ++ .../nouveau

[Mesa-dev] [PATCH 00/34] Nouveau NIR patches

spoken of patch. Can be enabled by setting NV50_PROG_USE_NIR=1 Chanelogs attached to the patches directly and nothing really new since the last time I posted that series, mostly just fixing compatibility with master. Have fun. Karol Herbst (34): prog_to_nir: fix write from vps to PSIZ nvc0

[Mesa-dev] [PATCH 05/34] nouveau: add support for nir

ake nir default" fix memory leak when creating compute shaders use debug_get_bool_option as it is available in non debug builds return failure if unsupported IR is encountered don't lower fpow in nir Signed-off-by: Karol Herbst Reviewed-by: Pierre Moreau --- src/gallium/dri

[Mesa-dev] [PATCH 04/34] nv50/ir: add lowering helper

NOT v8: don't require C++11 features Signed-off-by: Karol Herbst Reviewed-by: Pierre Moreau --- src/gallium/drivers/nouveau/Makefile.sources | 2 + .../codegen/nv50_ir_lowering_helper.cpp | 275 ++ .../nouveau/codegen/nv50_ir_lowering_helper.h | 53 src/ga

[Mesa-dev] [PATCH 01/34] prog_to_nir: fix write from vps to PSIZ

Point size is a single component value and drivers might write the full vec4 potentially overwriting other values. Signed-off-by: Karol Herbst --- src/mesa/program/prog_to_nir.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa

[Mesa-dev] [PATCH 06/34] nouveau: fix nir and TGSI shader cache collision

v9: rename variable to driver_flags use constants for shader cache flags Signed-off-by: Karol Herbst Reviewed-by: Pierre Moreau --- src/gallium/drivers/nouveau/nouveau_screen.c | 8 +++- src/gallium/drivers/nouveau/nouveau_screen.h | 3 +++ 2 files changed, 10 insertions(+), 1 deletion

[Mesa-dev] [PATCH 07/34] nv50/ir/nir: run some passes to make the conversion easier

v2: add constant_folding v6: print non final NIR only for verbose debugging v8: add passes we will need for OpenCL compute shaders v9: move type_size into anonymous namespace convert to C++ style comments lower bools to int32 Signed-off-by: Karol Herbst Acked-by: Pierre Moreau

[Mesa-dev] [PATCH 02/34] nvc0: print the shader type when dumping headers

this makes debugging the shader header a little easier Acked-by: Pierre Moreau Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0

[Mesa-dev] [PATCH 08/34] nv50/ir/nir: track defs and provide easy access functions

orted stdlibs replace '(*it).' with 'it->' Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 150 ++ 1 file changed, 150 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gal

[Mesa-dev] [PATCH 28/34] nv50/ir/nir: implement ssbo intrinsics

v4: use loadFrom helper v5: support indirect buffer access v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 90 +++ 1 file changed, 90 insertions(+) diff --git a/src/gallium/drivers/nouveau/co

[Mesa-dev] [PATCH 11/34] nv50/ir/nir: add loadFrom and storeTo helpler

v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 72 +++ 1 file changed, 72 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/co

[Mesa-dev] [PATCH 15/34] nv50/ir/nir: implement nir_alu_instr handling

ps to make it easier to grep them add handling for fpow Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 562 +- 1 file changed, 561 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/ga

[Mesa-dev] [PATCH 10/34] nv50/ir/nir: run assignSlots

error checking to slots Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 642 ++ 1 file changed, 642 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH 13/34] nv50/ir/nir: implement nir_load_const_instr

v8: fix loading 8/16 bit constants Signed-off-by: Karol Herbst Reviewed-by: Pierre Moreau --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 28 +++ 1 file changed, 28 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers

[Mesa-dev] [PATCH 22/34] nv50/ir/nir: implement nir_instr_type_tex

ts fix txf with a uniform constant 0 lod Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 234 ++ 1 file changed, 234 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/n

[Mesa-dev] [PATCH 09/34] nv50/ir/nir: add nir type helper functions

v4: treat imul as unsigned v5: remove pointless !! v7: inot is unsigned as well v8: don't require C++11 features v9: convert to C++ style comments improve formatting print error in all cases where codegen doesn't support a given type Signed-off-by: Karol Herbst Acked-by: Pie

[Mesa-dev] [PATCH 19/34] nv50/ir/nir: implement intrinsic_discard(_if)

v9: use getSSA instead of new_LValue Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen

[Mesa-dev] [PATCH 18/34] nv50/ir/nir: implement load_(interpolated_)input/output

info->prop.fp.readsSampleLocations for at_sample interpolation don't require C++11 features v9: convert to C++ style comments Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 135 ++ 1 file changed, 135 insertions(+) diff --git a/src/ga

[Mesa-dev] [PATCH 16/34] nv50/ir/nir: implement nir_intrinsic_load_uniform

v2: use new getIndirect helper fixes symbols for 64 bit types v4: use smarter getIndirect helper simplify address calculation use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH 14/34] nv50/ir/nir: add skeleton for nir_intrinsic_instr

Signed-off-by: Karol Herbst Reviewed-by: Pierre Moreau --- .../nouveau/codegen/nv50_ir_from_nir.cpp| 17 + 1 file changed, 17 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH 27/34] nv50/ir/nir: implement nir_intrinsic_load_ubo

v4: use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/no

[Mesa-dev] [PATCH 31/34] nv50/ir/nir: implement load_per_vertex_output

v4: use smarter getIndirect helper use new getSlotAddress helper v5: use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 23 +++ 1 file changed, 23 insertions(+) diff --git a/src/ga

[Mesa-dev] [PATCH 30/34] nv50/ir/nir: add memory barriers

v5: add more barrier intrinsics Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 21 +++ 1 file changed, 21 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen

[Mesa-dev] [PATCH 33/34] nv50/ir/nir: handle user clip planes for each emitted vertex

v9: convert to C++ style comments Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen

[Mesa-dev] [PATCH 25/34] nv50/ir/nir: implement variable indexing

types v5: use loadFrom helper v8: don't require C++11 features v9: convert to C++ style comments Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 58 +++ 1 file changed, 58 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_fr

[Mesa-dev] [PATCH 24/34] nv50/ir/nir: implement vote and ballot

d-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 48 +++ 1 file changed, 48 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp index ab3bf7f843a..7a10a408b70 1

[Mesa-dev] [PATCH 17/34] nv50/ir/nir: implement nir_intrinsic_store_(per_vertex_)output

correctly Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 57 ++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp index d

[Mesa-dev] [PATCH 23/34] nv50/ir/nir: add skeleton getOperation for intrinsics

v7: don't assert in default case for getSubOp Signed-off-by: Karol Herbst Reviewed-by: Pierre Moreau --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 22 +++ 1 file changed, 22 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH 20/34] nv50/ir/nir: implement loading system values

d-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 122 ++ 1 file changed, 122 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp index 5c372794e02..43c9a468f5a 1

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