Reviewed-by: Matt Turner
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t->src[1]);
> }
> -src0_1_w.subreg_offset += type_sz(BRW_REGISTER_TYPE_UW);
>
> -ibld.MUL(low, src0_0_w, inst->src[1]);
> -ibld.MUL(high, src0_1_w, inst->src[1]);
> - }
> +fs_reg dst = inst->
On Wed, Aug 5, 2015 at 11:36 AM, Jason Ekstrand wrote:
> On Tue, Aug 4, 2015 at 5:54 PM, Jason Ekstrand wrote:
>> On Tue, Aug 4, 2015 at 5:09 PM, Jordan Justen
>> wrote:
>>> I checked the extension spec, and it appears that like image
>>> load/store, ssbo is only required in fragment and comput
On Wed, Aug 5, 2015 at 8:44 AM, Ben Widawsky wrote:
> On Tue, Aug 04, 2015 at 11:16:55PM -0700, Matt Turner wrote:
>> On Tue, Aug 4, 2015 at 11:18 PM, Matt Turner wrote:
>> > Regression since commit 3a31876600, when tiling modes were moved into
>> > layout_flags.
>&
Regression since commit 3a31876600, when tiling modes were moved into
layout_flags.
The relevant enum values are
MIPTREE_LAYOUT_ALLOC_YTILED = 1 << 5
MIPTREE_LAYOUT_ALLOC_XTILED = 1 << 6
MIPTREE_LAYOUT_ALLOC_ANY_TILED = MIPTREE_LAYOUT_ALLOC_YTILED |
MI
On Wed, Aug 5, 2015 at 5:12 PM, Ben Widawsky wrote:
> On Wed, Aug 05, 2015 at 12:08:31PM -0700, Matt Turner wrote:
>> Regression since commit 3a31876600, when tiling modes were moved into
>> layout_flags.
>>
>> The relevant enum values are
>>
>>
Regression since commit 3a31876600, when tiling modes were moved into
layout_flags.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
i
Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it
needed to include no tiling at all, but the name
MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We can avoid
confusion by replacing "ALLOC" with "TILING" in the identifiers.
---
Once reviewed, I plan to land the patches in the
On Thu, Aug 6, 2015 at 11:14 AM, Ben Widawsky wrote:
> On Thu, Aug 06, 2015 at 11:03:55AM -0700, Matt Turner wrote:
>> Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it
>> needed to include no tiling at all, but the name
>> MIPTREE_LAYOUT_ALLOC_ANY is pret
(Don't top quote)
On Thu, Aug 6, 2015 at 7:22 AM, Boyan Ding wrote:
> But, isn't -INT_MIN == INT_MIN?
In C (-INT_MIN) is undefined since it relies on behavior of signed
integer overflow.
In GLSL though, I think you're right. The spec says that addition
subtraction, and shift operations (weird t
> vec1 ssa_26 = fneg ssa_21
> vec1 ssa_27 = fne ssa_21, ssa_26
>
> Make that:
> vec1 ssa_27 = fne ssa_21, 0.0f
>
> This is found in Dota2 and Brutal Legend.
> One shader is cut by 8%, from 323 -> 296 instructons in SIMD8
>
> Signed-off-by: Thomas Helland
> ---
by: Thomas Helland
> ---
I believe this is also safe.
Reviewed-by: Matt Turner
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Passing NULL to C11 threads functions isn't safe, so there's no need for
our implementation to handle it. Cuts about 1k of .text.
text data bss dec hex filename
5009514 19844026328 5234282 4fde6a i965_dri.so before
5008346 19844026328 5233114 4fd9da i965_
---
src/mesa/main/mtypes.h | 1 -
src/mesa/main/samplerobj.c | 16 +++-
2 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 2adfae2..fcc527f 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1153,
We were locking the Shared->Mutex and then using calling functions like
_mesa_HashInsert that do additional per-hash-table locking internally.
Instead just lock each hash-table's mutex and use functions like
_mesa_HashInsertLocked and the new _mesa_HashRemoveLocked.
In order to do this, we need t
---
src/mesa/main/fbobject.c | 1 -
src/mesa/main/mtypes.h | 1 -
src/mesa/main/renderbuffer.c | 15 +++
3 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index cc342c2..918889e 100644
--- a/src/mesa/main/fbo
Patches 1-11 improve performance of SynMark OglBatch7 by 6.29586% +/- 0.277734%
(n=337) and OglMultithread by 1.12564% +/- 0.424038% (n=209). I haven't
benchmarked individual patches because I'd like to not waste all that time if I
get review feedback that requires me to change things. :)
Patches
---
src/mesa/main/hash.c | 19 +++
src/mesa/main/hash.h | 2 ++
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/hash.c b/src/mesa/main/hash.c
index 315b5d6..aa1c6a1 100644
--- a/src/mesa/main/hash.c
+++ b/src/mesa/main/hash.c
@@ -328,8 +328,8 @@ _mesa
---
src/mesa/main/arrayobj.c| 4 +---
src/mesa/main/framebuffer.c | 4 +---
src/mesa/main/pipelineobj.c | 4 +---
src/mesa/main/shaderobj.c | 8 ++--
4 files changed, 5 insertions(+), 15 deletions(-)
diff --git a/src/mesa/main/arrayobj.c b/src/mesa/main/arrayobj.c
index f581e4c..da6757e
---
src/mesa/main/arrayobj.c | 8
src/mesa/main/bufferobj.c| 17 -
src/mesa/main/renderbuffer.c | 2 --
src/mesa/main/samplerobj.c | 8
src/mesa/main/shaderobj.c| 12
src/mesa/program/program.c | 14 --
6 files changed,
---
src/mesa/main/mtypes.h | 1 +
src/mesa/main/samplerobj.c | 10 ++
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 4e00fb6..962dad9 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1153,6 +1153
"Container objects" like vertex array objects, framebuffer objects, and
pipeline objects are not shared between contexts, so they require no
locking.
---
src/mesa/main/arrayobj.c| 6 --
src/mesa/main/fbobject.c| 9 -
src/mesa/main/framebuffer.c | 9 -
src/mesa/main/mtyp
---
src/mesa/main/mtypes.h | 1 -
src/mesa/program/program.c | 15 +++
2 files changed, 3 insertions(+), 13 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index fcc527f..c597ccc 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2095,7
---
src/mesa/main/bufferobj.c | 17 +++--
src/mesa/main/mtypes.h| 1 -
2 files changed, 3 insertions(+), 15 deletions(-)
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index cc035ff..78af229 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.
---
src/mesa/main/mtypes.h | 1 -
src/mesa/main/texobj.c | 17 +++--
2 files changed, 3 insertions(+), 15 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index b8329a0..43d2f67 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1180,7 +1180
---
src/mesa/main/mtypes.h | 1 +
src/mesa/program/program.c | 19 +++
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 962dad9..19f65ee 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -20
On Fri, Aug 7, 2015 at 1:57 AM, Timothy Arceri wrote:
> On Thu, 2015-08-06 at 17:11 -0700, Matt Turner wrote:
>> ---
>> src/mesa/main/hash.c | 19 +++
>> src/mesa/main/hash.h | 2 ++
>> 2 files changed, 17 insertions(+), 4 deletions(-)
>>
>&
On Fri, Aug 7, 2015 at 8:43 AM, Brian Paul wrote:
> On 08/06/2015 06:11 PM, Matt Turner wrote:
>>
>> ---
>> src/mesa/main/hash.c | 19 +++
>> src/mesa/main/hash.h | 2 ++
>> 2 files changed, 17 insertions(+), 4 deletions(-)
>>
>>
On Fri, Aug 7, 2015 at 2:09 AM, Timothy Arceri wrote:
> On Thu, 2015-08-06 at 17:11 -0700, Matt Turner wrote:
>> We were locking the Shared->Mutex and then using calling functions like
>> _mesa_HashInsert that do additional per-hash-table locking internally.
>>
>&g
other than those
> + * described above."
> + */
> + if ((barriers & ~all_allowed_bits) != 0) {
> + _mesa_error(ctx, GL_INVALID_VALUE,
> + "glMemoryBarrierByRegion(unsupported barrier bit");
> + }
> +
> + ctx->Driver.Mem
, Jul 17, 2015 at 2:11 PM, Eric Anholt wrote:
>>>>>> Matt Turner writes:
>>>>>>
>>>>>>> On Fri, Jul 17, 2015 at 10:17 AM, Emil Velikov
>>>>>>> wrote:
>>>>>>>> Cc: Eric Anholt
>>>&
On Fri, Aug 7, 2015 at 11:19 AM, Alexander von Gluck IV
wrote:
> This was causing a failure to build on SCons due to a missing
> -Isrc/egl. Instead of adding in that path, lets just -Isrc/
> and include "utils/u_atomic.h".
> ---
Re
On Fri, Aug 7, 2015 at 2:45 AM, Michel Thierry wrote:
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index 54081a1..ca90784 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchb
On Fri, Aug 7, 2015 at 12:24 PM, Oded Gabbay wrote:
> This patch fixes a bug that is manifested in the read path of mesa when
> running on big-endian machines. The effects can be seen when running
> piglit sanity test and/or taking a screen capture.
>
> The bug is caused when _mesa_format_convert
t; + compiler->glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS
> = false;
>}
> - compiler->glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS =
> false;
Would have been nice to send the patch with enough context to see the
if (compiler->scalar_vs) a few
On Sun, Aug 9, 2015 at 3:57 AM, Jose Fonseca wrote:
> Neither MSVC nor MinGW defines LONG_BIT. For MSVC this was not a problem as
> it doesn't define __x86_64__ macro (it's GCC specific.)
>
> However on Windows long type is guaranteed to be 32bits.
>
> Also add an #error, as GCC will just warn, n
On Sun, Aug 9, 2015 at 3:57 AM, Jose Fonseca wrote:
> As currently only GCC x86_64 builds where using it.
> ---
> src/util/rounding.h | 16 +---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/src/util/rounding.h b/src/util/rounding.h
> index ec31b47..38c1c2f 10064
; +
> +#include "macros.h" // STATIC_ASSERT
I don't think the STATIC_ASSERTs really add any safety, but they do
unfortunately cause us to include macros.h. :(
I'd personally remove them, but whatever you like.
Reviewed-by: Matt Turner
On Fri, Aug 7, 2015 at 10:09 AM, Ian Romanick wrote:
> I know we've talked about this about 100 times, but something in the
> back of my mind tells me that we have a pre-existing race. What happens
> if the p_atomic_dec_zero happens on thread A while thread B is between
> the _mesa_lookup_renderb
On Mon, Aug 3, 2015 at 5:22 PM, Jason Ekstrand wrote:
> The analysis code was already there and running, we just weren't doing
> anything with the result of it yet.
> ---
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/src/mesa/
On Mon, Aug 3, 2015 at 5:22 PM, Jason Ekstrand wrote:
> On BDW+, the negation source modifier on NOT, AND, OR, and XOR, is actually
> a boolean negate and not an integer negate. However, NIR's soruce
> modifiers are the integer version. We have to resolve it with a MOV prior
> to emitting the ac
ted
> NIR with vec4 vertex shaders on BDW, but I think it's probably ok. We
> should definitely verify that at some point.
I gave comments on 2 and 3. With those things fixed, this series is
Reviewed-by: Matt Turner
> I'm not 100% sure what I think about the first two patches.
d of reg_width in alloc_reg_sets
The first four are
Reviewed-by: Matt Turner
> i965/fs: Don't do redundant RA setup on IVB+
I'll take your word that the register sets are identical between
SIMD8/16 on IVB+ and give you an
Acked-by: Matt Turner
_
On Fri, Jul 31, 2015 at 10:05 AM, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
> index 211f
On Mon, Aug 10, 2015 at 11:19 AM, Jason Ekstrand wrote:
> On Mon, Aug 10, 2015 at 11:16 AM, Matt Turner wrote:
>> On Mon, Aug 3, 2015 at 5:22 PM, Jason Ekstrand wrote:
>>> On BDW+, the negation source modifier on NOT, AND, OR, and XOR, is actually
>>> a boolean negat
On Mon, Aug 10, 2015 at 11:37 AM, Jason Ekstrand wrote:
> On Mon, Aug 10, 2015 at 11:30 AM, Matt Turner wrote:
>> On Mon, Aug 10, 2015 at 11:19 AM, Jason Ekstrand
>> wrote:
>>> On Mon, Aug 10, 2015 at 11:16 AM, Matt Turner wrote:
>>>> On Mon, Au
On Mon, Aug 10, 2015 at 10:12 AM, Ian Romanick wrote:
> From: Ian Romanick
>
> On many CPU-limited applications, this is *the* hot path. The idea is
> to generate per-API versions of brw_draw_prims that elide some checks.
> This patch removes render-mode and "is everything in VBOs" checks from
>
dst_reg dst, src_reg src0, src_reg src1);
>
> - src_reg fix_3src_operand(src_reg src);
> + src_reg fix_3src_operand(const src_reg& src);
& goes with the argument name.
> src_reg resolve_source_modifiers(const src_reg& src);
I guess fix the ones in r
On Mon, Aug 10, 2015 at 11:53 AM, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 15 ---
> src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 14 +++---
> 3 files changed, 16 insertions(+), 15 deletions(-)
>
On Mon, Aug 10, 2015 at 12:01 PM, Neil Roberts wrote:
> Are you sure this patch is necessary? The documentation for the multiply
> instruction on BDW+ says:
>
> SourceType :*D
> DestinationType : *D
> Project : EXCLUDE(CHV)
>
> This to me implies that it should work on BXT because
On Mon, Aug 10, 2015 at 2:36 PM, Rob Clark wrote:
> oh, and these two patches are for apitrace.. guess I should have put
> something in the subject line to make that more clear. No idea if
> this is the right place to send apitrace patches..
It's not. There's an apitrace mailing list: apitr...@l
On Tue, Aug 11, 2015 at 9:43 AM, Martin Peres
wrote:
> Signed-off-by: Martin Peres
> ---
> docs/GL3.txt | 4 ++--
> docs/relnotes/11.0.0.html| 1 +
> src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
> 3 files changed, 4 insertions(+), 2 dele
* There is no scalar version of these ops, unless we were to break it
> + * down to bitshifts and math (which is definitely not intended).
> + */
> + return;
> +
> + case nir_op_unpack_half_2x16:
> + /* We could split this into unpack_half_2x16_split_[xy], but should
&
Cuts about 1k of .text.
text data bss dec hex filename
5018165 19716027672 5242997 500075 i965_dri.so before
5017141 19716027672 5241973 4ffc75 i965_dri.so after
---
src/mesa/drivers/dri/i965/brw_inst.h | 8
1 file changed, 4 insertions(+), 4 de
Cuts about 2k of .text.
text data bss dec hex filename
5017141 19716027672 5241973 4ffc75 i965_dri.so before
5014981 19716027672 5239813 4ff405 i965_dri.so after
---
src/mesa/drivers/dri/i965/brw_inst.h | 4 ++--
1 file changed, 2 insertions(+), 2 deleti
On Tue, Aug 11, 2015 at 2:25 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> ---
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74329
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On Tue, Aug 11, 2015 at 1:31 PM, Thomas Helland
wrote:
> 2015-08-11 20:25 GMT+02:00 Eric Anholt :
>> We may find a cause to do more undef optimization in the future, but for
>> now this fixes up things after if flattening. vc4 was handling this
>> internally most of the time, but a GLB2.7 shader
On Tue, Aug 11, 2015 at 4:14 PM, Nanley Chery wrote:
> +static bool
> +_mesa_format_no_online_compression(const struct gl_context *ctx, GLenum
> format)
> +{
> + return _mesa_is_astc_format(format) ||
> + compressedteximage_only_format(ctx, format);
Needs one more space of indentation.
aight into num_configs without being
> clamped to 0.
>
> This was causing the following dEQP EGL test to fail:
> dEQP-EGL.functional.query_config.get_configs.get_configs_bounds
>
> Signed-off-by: Frank Binns
> ---
Reviewed-by: Matt Turner
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Subject: [PATCH] i915: BINDING_TABLE_POINTER_* after CONSTANT_* for SKL & BXT
The driver you're modifying is i965. :)
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quot; on the Steam forums:
>
> https://steamcommunity.com/app/200390/discussions/0/540731690861139279/?insideModal=1#c594820656479479870
>
> Signed-off-by: Richard Yao
> ---
Acked-by: Matt Turner
Thanks. I'll commit this.
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On Tue, Aug 11, 2015 at 6:51 PM, Ilia Mirkin wrote:
> ---
> src/glsl/builtin_functions.cpp | 32
> +-
> src/glsl/glcpp/glcpp-parse.y | 3 +++
> src/glsl/glsl_parser_extras.cpp| 1 +
> src/glsl/glsl_parser_extras.h |
* contexts, and specifying them for other types of contexts
> will
> + * generate an error."
> + */
> + if (!dpy->Extensions.KHR_create_context ||
> + (api != EGL_OPENGL_ES_API && api != EGL_OPENGL_API)) {
> err = EGL_BAD_ATTRIBUTE;
> break;
> }
> --
But I can do that myself before pushing.
Reviewed-by: Matt Turner
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On Wed, Aug 12, 2015 at 11:55 AM, Eric Anholt wrote:
> There are so many flags in textures, that the CSE pass would have a hard
> time referencing the correct set when figuring out if two texture ops are
> the same. By zeroing, we can avoid that fragility.
> ---
Presumably you didn't see that th
If an immediate is written to multiple channels, we can load it in a
single writemasked MOV.
total instructions in shared programs: 6285144 -> 6261991 (-0.37%)
instructions in affected programs: 718991 -> 695838 (-3.22%)
helped:5762
---
The shader-db numbers are
On Thu, Aug 13, 2015 at 4:31 AM, Emil Velikov wrote:
> On 7 August 2015 at 19:22, Matt Turner wrote:
>> On Fri, Aug 7, 2015 at 11:05 AM, Emil Velikov
>> wrote:
>>> On 21 July 2015 at 13:12, Emil Velikov wrote:
>>>> On 20/07/15 21:25, Chad Versace wrote:
&g
Ken added support for 2DArray (commit ec23d5197e) and 1DArray (commit
14ca61125) last year.
---
src/mesa/drivers/common/meta_generate_mipmap.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/drivers/common/meta_generate_mipmap.c
b/src/mesa/drivers/common/meta_genera
On Mon, Aug 17, 2015 at 9:46 AM, Francisco Jerez wrote:
> This is basically just the same atomic functions exposed by
> ARB_shader_image_load_store, with one exception:
>
> "highp float imageAtomicExchange(
> coherent IMAGE_PARAMS,
> float data);"
>
> There's no float atomic
On Mon, Aug 17, 2015 at 9:46 AM, Francisco Jerez wrote:
> ---
> src/mesa/main/extensions.c | 1 +
> src/mesa/main/mtypes.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
> index d934d19..38c7bc8 100644
> --- a/src/mesa/main/e
On Tue, Jul 21, 2015 at 2:08 PM, Vinson Lee wrote:
> Fixes 'make check' on FreeBSD.
>
> Signed-off-by: Vinson Lee
> ---
Seems fine to me.
Reviewed-by: Matt Turner
At the same time, I don't have any idea if the scripts actually rely
on bash itself. I think I've
On Tue, Aug 18, 2015 at 10:53 AM, Francisco Jerez wrote:
> Connor Abbott writes:
>> and so many of them are interconnected and won't even make sense until
>> we have SSA, that it's not always useful to think about the IR we want
>> to have in the distant future in order to decide what to do today
On Mon, Jun 1, 2015 at 3:29 AM, Pohjolainen, Topi
wrote:
> On Fri, May 22, 2015 at 02:24:51PM -0400, Connor Abbott wrote:
>> This can be used for both CSE and value numbering.
>>
>> Signed-off-by: Connor Abbott
>> ---
>> src/glsl/Makefile.sources | 2 +
>> src/glsl/nir/nir_instr_hash.c | 2
On Tue, Aug 18, 2015 at 6:49 PM, Ilia Mirkin wrote:
> Some shaders appear to extract bits using shift/and combos. Detect
> (some) of those and convert to EXTBF instead.
What is EXTBF? Extract byte to float?
I ask because Unigine Heaven has shaders that pack 3x byte-integers
into one component of
On Tue, Aug 18, 2015 at 6:57 PM, Matt Turner wrote:
> On Tue, Aug 18, 2015 at 6:49 PM, Ilia Mirkin wrote:
>> Some shaders appear to extract bits using shift/and combos. Detect
>> (some) of those and convert to EXTBF instead.
>
> What is EXTBF? Extract byte to float?
>
On Wed, Aug 19, 2015 at 7:49 PM, Ian Romanick wrote:
> From: Ian Romanick
>
> grep -lr 'sub license' | while read f; do \
> sed --in-place -e 's/sub license/sublicense/' $f ;\
> done
>
> grep -lr 'NON-INFRINGEMENT' | while read f; do \
> sed --in-place -e 's/NON-INFRINGEMENT/NONINFRIN
Patches 1 and 6 were too large for the mailing list, so I checked them
in your tree. Patch 6 has some diffs that leave lines badly wrapped:
+ * THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWI
On Fri, Aug 21, 2015 at 6:42 AM, Boyan Ding wrote:
> Signed-off-by: Boyan Ding
> ---
> src/glsl/nir/nir_opt_undef.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/glsl/nir/nir_opt_undef.c b/src/glsl/nir/nir_opt_undef.c
> index 4ab27a8..fb9c6bb 100644
> --- a/src/gls
5
> HURT: 0
>
> Signed-off-by: Boyan Ding
> ---
Reviewed-by: Matt Turner
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Reviewed-by: Matt Turner
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On Thu, Aug 20, 2015 at 3:01 PM, Dave Airlie wrote:
>> Shader-db results for vec4 on i965:
>
> reads like a Johnny Cash cover of NIN.
Agreed, so let me explain why we're enabling it now.
The merge window closed yesterday for Mesa 11.0. vec4 NIR isn't quite
where we'd like it to be in terms of co
On Wed, Aug 26, 2015 at 10:50 AM, Jason Ekstrand wrote:
> I like adding constness but I don't really see the need for the
> whitespace changes or adding braces and breaks to the switch.
Please don't top quote.
Looks like he's removing braces and breaks from the switch, not adding them.
_
On Wed, Aug 26, 2015 at 8:40 PM, Tapani Pälli wrote:
> v2: use ARB_texture_multisample enable bit
>
> Patch adds extension enable bit and enables required keywords
> and builtin functions for the extension.
>
> Signed-off-by: Tapani Pälli
> ---
> src/glsl/builtin_functions.cpp | 5 +++--
> src/
On Thu, Aug 27, 2015 at 4:56 PM, Ilia Mirkin wrote:
> The ffsll patch seems dodgy... among other things the same logic is in
> imports.c and thus would probably best refactored to src/util, but
> additionally it's only defined if !_GNU_SOURCE -- is that OK? Would
> e.g. a 32-bit build have ffsll?
I always thought that the is_control_flow() -> return false check was a
bad hack, and some previous attempts to remove it have failed and have
been reverted.
The previous two patches fix some problems that caused register
coalescing to not notice some interference between registers, which the
is_c
equals() returns false for registers with different types, using it
isn't appropriate to determine whether an is overwriting a register.
---
src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_
No shader-db changes on g4x, snb, hsw, or bdw.
---
opt_peephole_sel() still offers some small benefits.
src/mesa/drivers/dri/i965/brw_fs.h | 1 -
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 -
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 89
3 files
Noticed when debugging things that lead to the next patch.
On G45 (and presumably ILK) this helps register coalescing:
total instructions in shared programs: 4077373 -> 4077340 (-0.00%)
instructions in affected programs: 43751 -> 43718 (-0.08%)
helped:52
HURT:
No need to walk through instructions in blocks we know don't contain our
registers' live ranges.
---
View with git diff -w for easier review.
.../drivers/dri/i965/brw_fs_register_coalesce.cpp | 34 +-
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/src/mesa/dr
start_to -> dst_start
end_to-> dst_end
start_from-> src_start
end_from -> src_end
var_to-> dst_var
var_from -> src_var
reg_to-> dst_reg
reg_to_offset -> dst_reg_offset
reg_from -> src_reg
Not sure how these made sense to me
On Thu, Aug 20, 2015 at 6:00 PM, Ilia Mirkin wrote:
> It is fairly tricky to detect the proper conditions for using bitfield
> insert, but easy to just use it up front. This removes a lot of
> instructions on nvc0 when invoking the packing builtins.
>
> Signed-off-by: Ilia Mirkin
> ---
>
> Not su
),
> + constant(16u)),
> + constant(16u));
> + }
> +
> + ir_variable *i = factory.make_temp(glsl_type::int_type,
> + "tmp_unpack_uint_to_ivec2_i");
Every instance
On Thu, Aug 27, 2015 at 8:48 PM, Ilia Mirkin wrote:
> Signed-off-by: Ilia Mirkin
> ---
> src/glsl/builtin_functions.cpp | 48
> +++---
> 1 file changed, 45 insertions(+), 3 deletions(-)
>
> diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functi
On Fri, Aug 28, 2015 at 12:02 AM, Ilia Mirkin wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91785
> Signed-off-by: Ilia Mirkin
> ---
Thanks. Please commit immediately.
Acked-by: Matt Turner
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On Fri, Aug 28, 2015 at 12:10 AM, Ilia Mirkin wrote:
> On Fri, Aug 28, 2015 at 3:02 AM, Matt Turner wrote:
>> On Thu, Aug 27, 2015 at 8:48 PM, Ilia Mirkin wrote:
>>> Signed-off-by: Ilia Mirkin
>>> ---
>>>
---
Here's another glapi patch that I never got upstream.
src/mapi/entry_x86-64_tls.h | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/src/mapi/entry_x86-64_tls.h b/src/mapi/entry_x86-64_tls.h
index 5c03b04..38faccc 100644
--- a/src/mapi/entry_x86-64_tls.h
+++ b/src/
On Mon, Aug 24, 2015 at 2:02 PM, Erik Faye-Lund wrote:
> There's no point in repeatedly looking up the base-format of an
> internalformat. So let's cache it in a variable instead.
>
> Signed-off-by: Erik Faye-Lund
> ---
I actually measure an increase in .text size with this patch, but
marking th
Reviewed-by: Matt Turner
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The remnants of the extension were removed from Mesa in commit 7a58262e.
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=555186
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91020
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91643
---
demo1 and eglscreen didn't look useful, bu
On Wed, Aug 5, 2015 at 1:30 AM, Iago Toral Quiroga wrote:
> From: Samuel Iglesias Gonsalvez
>
> Signed-off-by: Samuel Iglesias Gonsalvez
> ---
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 49
>
> 1 file changed, 49 insertions(+)
>
> diff --git a/src/mesa/driver
See commit 3b7f683f.
---
src/mesa/drivers/dri/i965/brw_fs_builder.h | 2 ++
src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp | 8
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h
b/src/mesa/drivers/dri/i965/brw_fs_bui
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