Use list_move_tail() to move MAC address entry from list of pending
to list of active entries. Simple list_add_tail() leaves the entry
also in the first list, this leads to list corruption.
Cc: Rasesh Mody
Signed-off-by: Ivan Vecera
---
drivers/net/ethernet/brocade/bna/bna_tx_rx.c | 2 +-
1 fil
This issue is caused by runtime power management. When NIC is down (ifconfig
down)
the NIC may be put into runtime suspend state, that cause driver cannot dump
tally counter successfully and incur error message "rtl_counters_cond == 1
(loop: 1000, delay: 10)"
In this patch I add deceting driver r
For RTL8168G/RTL8168H/RTL8411B/RTL8107E, enable this flag to eliminate message
"AMD-Vi: Event logged [IO_PAGE_FAULT device=01:00.0 domain=0x0002
address=0x3000 flags=0x0050] in dmesg.
Signed-off-by: Chunhao Lin
---
drivers/net/ethernet/realtek/r8169.c | 4
1 file changed, 4 dele
When there is no AC power, NIC doesn't work after changing mac address.
Please refer to following link.
http://www.spinics.net/lists/netdev/msg356572.html
This issue is caused by runtime power management. When there is no AC power, if
we
put NIC down (ifconfig down), the driver will be put in run
This series of patches fix 3 issues that are listed below.
Chunhao Lin (3):
r8169:fix nic sometimes doesn't work after changing the mac address.
r8169:eliminate error message in using ethtool -S when nic is down.
r8169: Enable RX_MULTI_EN for RTL_GIGA_MAC_VER_41~48
drivers/net/ethernet/rea
This patch introduces a helper which will return true if we're sure
that the available ring is empty for a specific vq. When we're not
sure, e.g vq access failure, return false instead. This could be used
for busy polling code to exit the busy loop.
Signed-off-by: Jason Wang
---
drivers/vhost/vh
This patch tries to poll for new added tx buffer or socket receive
queue for a while at the end of tx/rx processing. The maximum time
spent on polling were specified through a new kind of vring ioctl.
Signed-off-by: Jason Wang
---
drivers/vhost/net.c| 79 +
This path introduces a helper which can give a hint for whether or not
there's a work queued in the work list. This could be used for busy
polling code to exit the busy loop.
Signed-off-by: Jason Wang
---
drivers/vhost/vhost.c | 7 +++
drivers/vhost/vhost.h | 1 +
2 files changed, 8 insertio
This series tries to add basic busy polling for vhost net. The idea is
simple: at the end of tx/rx processing, busy polling for new tx added
descriptor and rx receive socket for a while. The maximum number of
time (in us) could be spent on busy polling was specified ioctl.
Test A were done through
The FILTMGMT privilege is necessary on BE3 chip to manipulare filters
like MC, UC list management, VLAN filter, promisc mode... This privilege
is dropped for VFs when transparrent tagging is enabled on them. This
prevents to make interface up for such VF because be_enable_if_filters()
called from b
Miscellaneous updates covering SRIOV, IRQ coalescing, firmware logging and
package version for net-next. Thanks.
v2: Updated description and added more comments for patch 1. Fixed
function parameters formatting for patch 4.
Jeffrey Huang (1):
bnxt_en: Send PF driver unload notification to al
From: Jeffrey Huang
During remove_one() when SRIOV is enabled, the PF driver
should broadcast PF driver unload notification to all
VFs that are attached to VMs. Upon receiving the PF
driver unload notification, the VF driver should print
a warning message to message log. Certain operations on th
Use appropriate firmware request header structure to prepare the
firmware messages. This avoids the unnecessary conversion of the
fields to 32-bit fields. Add appropriate endian conversion when
printing out the message fields in dmesg so that they appear correct
in the log.
Reported-by: Rob Swin
From: Rob Swindell
For everything to fit, we remove the PHY microcode version and replace it
with the firmware package version in the fw_version string.
Signed-off-by: Rob Swindell
Signed-off-by: Michael Chan
---
drivers/net/ethernet/broadcom/bnxt/bnxt.c | 8 +-
drivers/net/ethernet
This is used to send NVM_FIND_DIR_ENTRY messages which can return error
if the entry is not found. This is normal and the error message will
cause unnecessary alarm, so silence it.
Signed-off-by: Michael Chan
---
drivers/net/ethernet/broadcom/bnxt/bnxt.c | 11 +++
drivers/net/et
Before this patch, we used a hardcoded value of 500 msec as the default
value for firmware message response timeout. For better portability with
future hardware or debug platforms, use the value provided by firmware in
the first response and store it for all susequent messages. Redefine the
macro
Add a new function bnxt_do_send_msg() to do essentially the same thing
with an additional paramter to silence error response messages. All
current callers will set silent to false.
Signed-off-by: Michael Chan
---
drivers/net/ethernet/broadcom/bnxt/bnxt.c | 14 +-
1 file changed, 9 i
From: Jeffrey Huang
Allow the VF to setup its own MAC address if the PF has not administratively
set it for the VF. To do that, we should always store the MAC address
from the firmware. There are 2 cases:
1. The MAC address is valid. This MAC address is assigned by the PF and
it needs to over
Don't convert these to internal hardware tick values before storing
them. This avoids the confusion of ethtool -c returning slightly
different values than the ones set using ethtool -C when we convert
hardware tick values back to micro seconds. Add better comments for
the hardware settings.
Also
Add a function to set all the coalescing parameters. The function can
be used later to set both rx and tx coalescing parameters.
v2: Fixed function parameters formatting requested by DaveM.
Signed-off-by: Michael Chan
---
drivers/net/ethernet/broadcom/bnxt/bnxt.c | 26 +
When tx and rx rings don't share the same completion ring, tx coalescing
parameters can be set differently from the rx coalescing parameters.
Otherwise, use rx coalescing parameters on shared completion rings.
Adjust rx coalescing default values to lower interrupt rate.
Signed-off-by: Michael Cha
On 02/26/16 at 09:18am, Mikko Rapeli wrote:
> On Thu, Feb 25, 2016 at 10:08:56PM +0100, Thomas Graf wrote:
> > There is another issue with this commit. iptables.h included from m_ipt.c
> > includes xtables.h which includes which is not
> > available on a system without xtables.
> >
> > gcc -Wall
This method allows the controlling device (i.e. the bridge) to specify
additional headroom to be allocated for skb head on frame reception.
Signed-off-by: Paolo Abeni
---
v1 -> v2:
- fixed netdev_get_fwd_headroom()
- added netdev_set_rx_headroom() and netdev_reset_rx_headroom() helpers
v2 -> v
ndo_set_rx_headroom controls the align value used by tun devices to
allocate skbs on frame reception.
When the xmit device adds a large encapsulation, this avoids an skb
head reallocation on forwarding.
The measured improvement when forwarding towards a vxlan dev with
frame size below the egress d
This patch implements bookkeeping support to compute the maximum
headroom for all the devices in each datapath. When said value
changes, the underlying devs are notified via the
ndo_set_rx_headroom method.
This also increases the internal vports xmit performance.
Signed-off-by: Paolo Abeni
---
Currently, while when an OVS or Linux bridge is used to forward frames towards
some tunnel device, a skb_head_copy() may occur if the ingress device do not
provide enough headroom for the tx encapsulation.
This patch series tries to address the issue implementing a new ndo operation to
allow the m
The rx headroom for veth dev is the peer device needed_headroom.
Avoid ping-pong updates setting the private flag IFF_PHONY_HEADROOM.
This avoids skb head reallocation when forwarding from a veth dev
towards a device adding some kind of encapsulation.
When transmitting frames below the MTU size t
On bridge needed_headroom changes, the enslaved devices are
notified via the ndo_set_rx_headroom method
Signed-off-by: Paolo Abeni
---
v1 -> v2:
- use netdev_set_rx_headroom() to update the br ports headroom
- reset the dev rx headroom upon dev removal from bridge
---
net/bridge/br_if.c | 37
Fri, Feb 26, 2016 at 12:20:45AM CET, john.fastab...@gmail.com wrote:
>In the initial implementation the only way to stop a rule from being
>inserted into the hardware table was via the device feature flag.
>However this doesn't work well when working on an end host system
>where packets are expect
Signed-off-by: Alexandre TORGUE
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt
b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
new file mode 100644
index 000..67fceda
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt
@@ -0,0 +1,40 @@
+STMic
stm324xx family chips support Synopsys MAC 3.510 IP.
This patch adds settings for logical glue logic:
-clocks
-mode selection MII or RMII.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig
b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index cec147d..235d67
Adds support of Synopsys 3.50a MAC IP in stmmac driver.
Signed-off-by: Alexandre TORGUE
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 6a52fa1..6cca626 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platf
STM32F429 Chip embeds a Synopsys 3.50a MAC IP.
This series:
-enhance current stmmac driver to control it (code already
available) and adds basic glue for STM32F429 chip.
-Enable basic Net config in kernel.
Note that DT patches are not present because STM32 pinctrl code is not
yet avalaible.
Cha
Enable basic Ethernet support (IPV4) for stm32 defconfig.
Signed-off-by: Alexandre TORGUE
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index ec52505..8b8abe0 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -33,11 +33,20
Hannes Frederic Sowa wrote:
> On 26.02.2016 01:45, Wakko Warner wrote:
> >Now there's another one:
> >[ 777.315931] [ cut here ]
> >[ 777.316099] WARNING: CPU: 0 PID: 1404 at
> >/usr/src/linux/dist/4.4-nobklcd/net/ipv4/af_inet.c:155
> >inet_sock_destruct+0x1cb/0x1f0()
>
On Fri, Feb 26, 2016 at 2:16 PM, Ivan Vecera wrote:
> The FILTMGMT privilege is necessary on BE3 chip to manipulare filters
> like MC, UC list management, VLAN filter, promisc mode... This privilege
> is dropped for VFs when transparrent tagging is enabled on them. This
> prevents to make interfac
On Thu, Feb 25, 2016 at 10:11:36AM -0800, John Fastabend wrote:
> On 16-02-25 09:37 AM, Pablo Neira Ayuso wrote:
> > Hi,
> >
> > This patchset contains the core infrastructure for the generic
> > intermediate representation that I presented during NetDev 1.1's
> > nftables switchdev talk. This inc
On 26.2.2016 12:36, Sathya Perla wrote:
On Fri, Feb 26, 2016 at 2:16 PM, Ivan Vecera wrote:
The FILTMGMT privilege is necessary on BE3 chip to manipulare filters
like MC, UC list management, VLAN filter, promisc mode... This privilege
is dropped for VFs when transparrent tagging is enabled on t
On Fri, Feb 26, 2016 at 5:54 PM, Ivan Vecera wrote:
> On 26.2.2016 12:36, Sathya Perla wrote:
>>
>> On Fri, Feb 26, 2016 at 2:16 PM, Ivan Vecera wrote:
>>>
>>> The FILTMGMT privilege is necessary on BE3 chip to manipulare filters
>>> like MC, UC list management, VLAN filter, promisc mode... This
Since 11n aggregation become important to get the
best out of txops. However aggregation inherently
requires buffering and queuing. Once variable
medium conditions to different associated stations
is considered it became apparent that bufferbloat
can't be simply fought with qdiscs for wireless
driv
On 26.2.2016 13:44, Sathya Perla wrote:
On Fri, Feb 26, 2016 at 5:54 PM, Ivan Vecera wrote:
On 26.2.2016 12:36, Sathya Perla wrote:
On Fri, Feb 26, 2016 at 2:16 PM, Ivan Vecera wrote:
The FILTMGMT privilege is necessary on BE3 chip to manipulare filters
like MC, UC list management, VLAN fi
This patch adds the Makefile and Kconfig required to make the driver build.
Signed-off-by: John Crispin
Signed-off-by: Felix Fietkau
Signed-off-by: Michael Lee
---
drivers/net/ethernet/Kconfig |1 +
drivers/net/ethernet/Makefile |1 +
drivers/net/ethernet/mediatek/Kc
Add support for rt3883 and its smaller version rt3662. They both have a
single gBit port that will normally be attached to an external phy or
switch. There are not many rt3883 based routers in the field. I think
there is a second MAC on these SoCs. Due to lack of hardware utilizing this
I never add
On Thu, Feb 25, 2016 at 12:37:38PM -0800, John Fastabend wrote:
> On 16-02-25 09:37 AM, Pablo Neira Ayuso wrote:
> > This patch moves the u32 parser from the ixgbe that John has made to the
> > core u32. This parser has been adapted to build the intermediate
> > representation.
> >
> > To store th
The GSW is found in all of the 1000mbit SoCs. it has 5 external ports,
1-2 cpu ports and 1 further port that the internal HW offloading engine
connects to. The switch core used is a MT7530, which also exists as a
standalone chip. Although these SoCs (mt7620/1/3) share the same switch
core, the brin
Add support for SoCs from the mt7623 family. With this generation of SoCs
we have seen a change from MIPS to ARM cores. Due to the fact that ARM SoC
tend to be a bit more complex than MIPS, we need support for power domains.
The code should also run on MT2701, however this has not been tested yet
Add support for SoCs from the rt3050 family. This include rt3050, rt3052,
rt3352 and rt5350. These all have a builtin 5 port 100mbit switch (ESW).
There are a huge amount of CPEs in the wild that use this SoC as they were
some of the first to have builtin 802.11n wmacs.
rt5350 was an ultra low cos
Add myself and Felix as the Maintainers for the driver.
Signed-off-by: John Crispin
Signed-off-by: Felix Fietkau
---
MAINTAINERS |7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 156e1d3..4a51c66 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6908,6 +
rt2880 is the oldest SoC with this core. It has a single gBit port that
will normally be attached to an external phy or switch. The patch also
adds the code required to drive the mdio bus os these SoCs. According to
the datasheet, this SoC has has checksum offloading and 2 byte dma padding.
On devi
Add support for SoCs from the mt7621 family. These all have 2 GMAC ports,
both of which are attached to the same internal 1000MBit switch. Currently
we only support GMAC1 as the sole CPU port. MT7621 is very similar to
MT7620 with only a few registers having different offsets. MT7621 is the
first S
Add support for SoCs from the mt7620 family. These all have one dedicated
external gbit port and a builtin 5 port 100mbit switch. Additionally one
of the 5 switch ports can be changed to become an additional gbit port
that we can attach a phy to. MT7620 was the first SoC released after
Ralink was a
Add three files. One describes the actual frame engine, the other two
describe fast ethernet and gigabit switches bindings.
Signed-off-by: John Crispin
Signed-off-by: Felix Fietkau
Signed-off-by: Michael Lee
Cc: devicet...@vger.kernel.org
---
.../devicetree/bindings/net/mediatek-net-esw.txt
The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
external ports, 1 cpu port and 1 further port that the internal HW
offloading engine connects to.
This driver is very basic and only provides basic init and irq support.
The SoC and switch core both have support for a special ta
This series adds support for the Ralink/Mediatek ethernet core. The driver
works on all SoCs made by Ralink and all SoCs made by MTK/WCN that were
produced after the acquisition.
There have been a lot of changes since I posted this start of january. The
most important ones are listed below
Change
This patch adds the main chunk of the driver. The ethernet core is used in
all of the Mediatek/Ralink Wireless SoCs. Over the years we have seen
various changes to
* the register layout
* the type of ports (single/dual gbit, internal FE/Gbit switch)
* dma engine (PDMA/QDMA)
and new offloading feat
On 16-02-26 02:29 AM, Jiri Pirko wrote:
> Fri, Feb 26, 2016 at 12:20:45AM CET, john.fastab...@gmail.com wrote:
>> In the initial implementation the only way to stop a rule from being
>> inserted into the hardware table was via the device feature flag.
>> However this doesn't work well when working
The two header files got moved to include/linux, and most
users were already converted, this changes the remaining drivers
and removes the files.
Signed-off-by: Arnd Bergmann
---
drivers/dma/idma64.h| 2 +-
drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c | 2 +
On Thu, 2016-02-25 at 15:26 -0500, David Miller wrote:
> From: Heikki Hannikainen
> Date: Thu, 25 Feb 2016 21:36:07 +0200 (EET)
>
> > Commit 9c7077622dd9174 added a check, ll_header_truncated(), which
> > requires that a packet transmitted using sendmsg() with PF_PACKET,
> > SOCK_RAW must be long
On 16-02-26 06:24 AM, Pablo Neira Ayuso wrote:
> On Thu, Feb 25, 2016 at 12:37:38PM -0800, John Fastabend wrote:
>> On 16-02-25 09:37 AM, Pablo Neira Ayuso wrote:
>>> This patch moves the u32 parser from the ixgbe that John has made to the
>>> core u32. This parser has been adapted to build the int
On Fri, Feb 26, 2016 at 03:21:35PM +0100, John Crispin wrote:
> The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
> external ports, 1 cpu port and 1 further port that the internal HW
> offloading engine connects to.
>
> This driver is very basic and only provides basic init and
On 26/02/2016 16:18, Andrew Lunn wrote:
> On Fri, Feb 26, 2016 at 03:21:35PM +0100, John Crispin wrote:
>> The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
>> external ports, 1 cpu port and 1 further port that the internal HW
>> offloading engine connects to.
>>
>> This drive
On 16-02-26 03:47 AM, Pablo Neira Ayuso wrote:
> On Thu, Feb 25, 2016 at 10:11:36AM -0800, John Fastabend wrote:
>> On 16-02-25 09:37 AM, Pablo Neira Ayuso wrote:
>>> Hi,
>>>
>>> This patchset contains the core infrastructure for the generic
>>> intermediate representation that I presented during N
-Original Message-
From: Hiroshi Shimamoto [mailto:h-shimam...@ct.jp.nec.com]
Sent: Thursday, February 25, 2016 6:40 PM
To: Kirsher, Jeffrey T ; Stephen Hemminger
Cc: Rose, Gregory V ; Or Gerlitz
; Alexander Duyck ; Skidmore,
Donald C ; intel-wired-...@lists.osuosl.org;
nhor...@redhat
This adds a software only flag to tc but incorporates a bunch of comments
from the original attempt at this.
First instead of having the offload decision logic be embedded in cls_u32
I lifted into cls_pkt.h so it can be used anywhere and named the flag
TCA_CLS_FLAGS_SKIP_HW (Thanks Jiri ;)
In ord
In the original series drivers would get offload requests for cls_u32
rules even if the feature bit is disabled. This meant the driver had
to do a boiler plate check on the feature bit before adding/deleting
the rule.
This patch lifts the check into the core code and removes it from the
driver spe
The offload decision was originally very basic and tied to if the dev
implemented the appropriate ndo op hook. The next step is to allow
the user to more flexibly define if any paticular rule should be
offloaded or not. In order to have this logic in one function lift
the current check into a helpe
Fri, Feb 26, 2016 at 04:54:13PM CET, john.fastab...@gmail.com wrote:
>In the original series drivers would get offload requests for cls_u32
>rules even if the feature bit is disabled. This meant the driver had
>to do a boiler plate check on the feature bit before adding/deleting
>the rule.
>
>This
Fri, Feb 26, 2016 at 04:54:39PM CET, john.fastab...@gmail.com wrote:
>In the initial implementation the only way to stop a rule from being
>inserted into the hardware table was via the device feature flag.
>However this doesn't work well when working on an end host system
>where packets are expect
In the initial implementation the only way to stop a rule from being
inserted into the hardware table was via the device feature flag.
However this doesn't work well when working on an end host system
where packets are expect to hit both the hardware and software
datapaths.
For example we can imag
Fri, Feb 26, 2016 at 04:53:49PM CET, john.fastab...@gmail.com wrote:
>The offload decision was originally very basic and tied to if the dev
>implemented the appropriate ndo op hook. The next step is to allow
>the user to more flexibly define if any paticular rule should be
>offloaded or not. In ord
On Fri, Feb 26, 2016 at 06:53:11AM -0800, John Fastabend wrote:
> On 16-02-26 06:24 AM, Pablo Neira Ayuso wrote:
> > On Thu, Feb 25, 2016 at 12:37:38PM -0800, John Fastabend wrote:
> >> On 16-02-25 09:37 AM, Pablo Neira Ayuso wrote:
> >>> This patch moves the u32 parser from the ixgbe that John has
On Fri, Feb 26, 2016 at 07:42:25AM -0800, John Fastabend wrote:
> On 16-02-26 03:47 AM, Pablo Neira Ayuso wrote:
> > The parser on the backend is not the way to go. I would expect it
> > will not take long time until we see other people copying/pasting it
> > and adapting it to their need just bec
On 2016-02-26 16:18, Andrew Lunn wrote:
> On Fri, Feb 26, 2016 at 03:21:35PM +0100, John Crispin wrote:
>> The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
>> external ports, 1 cpu port and 1 further port that the internal HW
>> offloading engine connects to.
>>
>> This driver
From: Mikko Rapeli
Date: Fri, 26 Feb 2016 09:25:13 +0200
> (Adding libc-alpha list, review of https://lkml.org/lkml/2016/2/7/89 )
>
> On Wed, Feb 17, 2016 at 10:46:20AM -0500, David Miller wrote:
>> From: Mikko Rapeli
>> Date: Sun, 7 Feb 2016 16:03:21 +0200
>>
>> > @@ -68,6 +72,8 @@
>> > *
From: Jiri Pirko
Implement newly introduced devlink interface. Add devlink port instances
for every port and set the port types accordingly.
Signed-off-by: Jiri Pirko
v2->v3:
-add dev param to devlink_register (api change)
---
drivers/infiniband/hw/mlx4/main.c | 7
drivers/n
From: Ido Schimmel
The port netdevs are each associated with a different local port number
in the device. These local ports are grouped into groups of 4 (e.g.
(1-4), (5-8)) called clusters. The cluster constitutes the one of two
possible modules they can be mapped to. This mapping is board-specif
From: Jiri Pirko
Implement newly introduced devlink interface. Add devlink port instances
for every port and set the port types accordingly.
Signed-off-by: Jiri Pirko
Signed-off-by: Ido Schimmel
---
v2->v3:
-add dev param to devlink_register (api change)
v1->v2:
-removed SET_NETDEV_DEV set to
From: Ido Schimmel
Allow a user to split or unsplit a port using the newly introduced
devlink ops.
Once split, the original netdev is destroyed and 2 or 4 others are
created, according to user configuration. The new ports are like any
other port, with the sole difference of supporting a lower ma
From: Ido Schimmel
When splitting a port we replace it with 2 or 4 other ports. To be able
to do that we need to remove the original port netdev and unmap it from
its module. However, we first mark it as disabled, as active ports
cannot be unmapped.
Signed-off-by: Ido Schimmel
Signed-off-by: Ji
From: Ido Schimmel
When splitting and unsplitting we'll destroy usable ports on the fly, so
mark them using a NULL pointer to indicate that their local port number
is free and can be re-used.
Signed-off-by: Ido Schimmel
Signed-off-by: Jiri Pirko
---
drivers/net/ethernet/mellanox/mlxsw/spectru
From: Jiri Pirko
There a is need for some userspace API that would allow to expose things
that are not directly related to any device class like net_device of
ib_device, but rather chip-wide/switch-ASIC-wide stuff.
Use cases:
1) get/set of port type (Ethernet/InfiniBand)
2) setting up port split
From: Jiri Pirko
Introduce devlink infrastructure for drivers to register and expose to
userspace via generic Netlink interface.
There are two basic objects defined:
devlink - one instance for every "parent device", for example switch ASIC
devlink port - one instance for every physical port of t
From: Jiri Pirko
So far, there has been an mlx4-specific sysfs file allowing user to
change port type to either Ethernet of InfiniBand. This is very
inconvenient.
Allow to expose the same ability to set port type in a generic way
using devlink interface.
Signed-off-by: Jiri Pirko
---
drivers/
From: Jiri Pirko
Add middle layer in mlxsw core code to forward port split/unsplit calls
into specific ASIC drivers.
Signed-off-by: Jiri Pirko
Signed-off-by: Ido Schimmel
---
drivers/net/ethernet/mellanox/mlxsw/core.c | 34 +-
drivers/net/ethernet/mellanox/mlxsw/co
On 16-02-26 08:02 AM, Pablo Neira Ayuso wrote:
> On Fri, Feb 26, 2016 at 06:53:11AM -0800, John Fastabend wrote:
>> On 16-02-26 06:24 AM, Pablo Neira Ayuso wrote:
>>> On Thu, Feb 25, 2016 at 12:37:38PM -0800, John Fastabend wrote:
On 16-02-25 09:37 AM, Pablo Neira Ayuso wrote:
> This patch
From: Jason Wang
Date: Fri, 26 Feb 2016 16:42:41 +0800
> This series tries to add basic busy polling for vhost net. The idea is
> simple: at the end of tx/rx processing, busy polling for new tx added
> descriptor and rx receive socket for a while. The maximum number of
> time (in us) could be spe
On 16-02-26 08:19 AM, Pablo Neira Ayuso wrote:
> On Fri, Feb 26, 2016 at 07:42:25AM -0800, John Fastabend wrote:
>> On 16-02-26 03:47 AM, Pablo Neira Ayuso wrote:
>>> The parser on the backend is not the way to go. I would expect it
>>> will not take long time until we see other people copying/pas
On 2016-02-26 14:09, Michal Kazior wrote:
> Since 11n aggregation become important to get the
> best out of txops. However aggregation inherently
> requires buffering and queuing. Once variable
> medium conditions to different associated stations
> is considered it became apparent that bufferbloat
> the problem here is that on one side people complain about vendors not
> sending code upstream. once they start being a good citizen and provide
> funding to send stuff upstream the feedback tends to be very bad as seen
> here. we are planning on doing a DSA driver but one step at a time. this
>
From: Pablo Neira Ayuso
Date: Fri, 26 Feb 2016 12:47:14 +0100
> The frontend parser should be generic to everyone, it should be
> placed in the core, so everyone will take care of improving it.
Generic unfortunately means information loss and lots of wasted work.
And this is one of John's point
On Fri, Feb 26, 2016 at 05:25:38PM +0100, Felix Fietkau wrote:
> On 2016-02-26 16:18, Andrew Lunn wrote:
> > On Fri, Feb 26, 2016 at 03:21:35PM +0100, John Crispin wrote:
> >> The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
> >> external ports, 1 cpu port and 1 further port th
On Fri, Feb 26, 2016 at 9:44 AM, Alan Cox wrote:
> On Thu, 2016-02-25 at 15:26 -0500, David Miller wrote:
>> From: Heikki Hannikainen
>> Date: Thu, 25 Feb 2016 21:36:07 +0200 (EET)
>>
>> > Commit 9c7077622dd9174 added a check, ll_header_truncated(), which
>> > requires that a packet transmitted u
From: John Fastabend
Date: Fri, 26 Feb 2016 06:53:11 -0800
> sure but its easier for me to just consume u32 at the moment. And I
> am concerned about performance overhead with this IR. I'm going to need
> to have a performant solution eventually and I don't like converting
> into one IR only to g
From: Alan Cox
Date: Fri, 26 Feb 2016 14:44:34 +
> On Thu, 2016-02-25 at 15:26 -0500, David Miller wrote:
>> From: Heikki Hannikainen
>> Date: Thu, 25 Feb 2016 21:36:07 +0200 (EET)
>>
>> > Commit 9c7077622dd9174 added a check, ll_header_truncated(), which
>> > requires that a packet transmi
From: Andrew Lunn
Date: Fri, 26 Feb 2016 16:18:13 +0100
> On Fri, Feb 26, 2016 at 03:21:35PM +0100, John Crispin wrote:
>> The ESW is found in many of the old 100mbit MIPS based SoCs. it has 5
>> external ports, 1 cpu port and 1 further port that the internal HW
>> offloading engine connects to.
From: John Crispin
Date: Fri, 26 Feb 2016 16:24:47 +0100
> the problem here is that on one side people complain about vendors not
> sending code upstream. once they start being a good citizen and provide
> funding to send stuff upstream the feedback tends to be very bad as seen
> here.
The feedb
From: Pablo Neira Ayuso
Date: Fri, 26 Feb 2016 17:02:22 +0100
> Just because you want to early microoptimize this thing by saving a
> little of extra code that runs from the control plane path.
I don't think that's what he is doing at all.
We have classes of classifier etc. offloads that need I
On Fri, Feb 26, 2016 at 7:53 AM, John Fastabend
wrote:
> The offload decision was originally very basic and tied to if the dev
> implemented the appropriate ndo op hook. The next step is to allow
> the user to more flexibly define if any paticular rule should be
> offloaded or not. In order to hav
From: Pablo Neira Ayuso
Date: Fri, 26 Feb 2016 17:19:48 +0100
> I see no reason to have as many hooks as frontends to start with. If
> you find limitations with the IR that are unfixable for any of the
> existing frontends in the future, then we can add direct hook as final
> solution.
I see no
From: Felix Fietkau
Date: Fri, 26 Feb 2016 17:25:38 +0100
> In my opinion, leaving this part out does not make much sense and
> neither does deferring the entire patch series until we have a
> switchdev/DSA capable driver. This is just a starting point, which will
> be turned into a proper driver
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