Hi Geert,
On 12/1/2016, Sergei Shtylyov wrote:
>
> On 12/01/2016 05:42 PM, Geert Uytterhoeven wrote:
>
> >> --- a/drivers/net/ethernet/renesas/sh_eth.c
> >> +++ b/drivers/net/ethernet/renesas/sh_eth.c
> >> @@ -518,7 +518,7 @@ static struct sh_eth_cpu_data r7s72100_data = {
> >>
> >>
ot; option)
handlers:
[] sh_eth_interrupt
Disabling IRQ #21
Fixes: db893473d313a4ad ("sh_eth: Add support for r7s72100")
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Acked-by: Sergei Shtylyov <sergei.shtyl...@cogentembedded.com>
---
v3:
* add RZ/A1 to subject li
On 12/1/2016, Sergei Shtylyov wrote:
> One thing you've missed so far is mentioning R7S72100 (RZ/A1) in the
> subject. This driver supports many SoCs, you're only fixing one of them...
For the last sh_eth.c patch I submitted, I had:
"net: ethernet: renesas: sh_eth: add POST registers for rz"
)
handlers:
[] sh_eth_interrupt
Disabling IRQ #21
Fixes: db893473d313a4ad ("sh_eth: Add support for r7s72100")
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
v2:
* switched from modifying eesr_err_check to modifying eesipr_value
---
drivers/net/ethernet/renesas/sh_eth.c
On 12/1/2016, Sergei Shtylyov wrote:
> Hello!
>
> Please always CC me on the sh_eth/ravb driver patches as directed by
> scripts/get_maintainer.pl.
OK. I'm sorry.
> On 11/30/2016 11:01 PM, Chris Brandt wrote:
>
> > When streaming a lot of data and the RZ ca
)
handlers:
[] sh_eth_interrupt
Disabling IRQ #21
Fixes: db893473d313a4ad ("sh_eth: Add support for r7s72100")
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
drivers/net/ethernet/renesas/sh_eth.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dr
On 9/9/2016, Sergei Shtylyov wrote:
> > sh_eth_private *mdp) {
> > if (sh_eth_is_rz_fast_ether(mdp)) {
> > sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
> > + sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
> > +
As a follow up on this thread:
On 8/30/2016, Geert Uytterhoeven wrote:
> > I just looked at the RZ/A1 register space and there seems to be dummy
> > registers in the POST1-4 area. I can write to them and read back what I
> > wrote...which is all that the sh_eth driver cares about. I bet when the
can cause a memory
corruption or panic.
This patch fixes the panic and properly enables CAM.
Reported-by: Daniel Palmer <dan...@0x0f.com>
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
v2:
* POST registers really do exist, so just add them
---
drivers/net/ethernet/renesas/
Hello Sergei,
On Aug 29, 2016, Sergei Shtylyov wrote:
>SH7757 is not the only platform with TSU, there's e.g. R8A7740 ARM
> SoC which only has 1 GETHER channel...
I don't have the R8A7740 manual (R-Mobile A1) so I can't see. But even if it
does not have the POST registers, it might not hurt
On 08/28/2016, Sergei Shtylyov wrote:
>> The RZ/A1 has a TSU, but since it only has one Ethernet port, it does
>> not have POST registers.
>
>I'm not sure the reason is having one port... do you have the old SH
> manuals somewhere? :-)
Yes, I used to support the SH7757. It had dual ETHER
com>
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
drivers/net/ethernet/renesas/sh_eth.c | 7 +++
drivers/net/ethernet/renesas/sh_eth.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/renesas/sh_eth.c
b/drivers/net/ethernet/renesas/sh_eth.c
i
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