Hi Dave,
This patch (1/2) seems to have fallen through the cracks. The other
one (2/2), you already picked.
Thanks
On Mon, Apr 16, 2018 at 1:08 PM wrote:
>
> From: Jassi Brar
>
> Enable TX-irq as well during ndo_open() as we can not count upon
> RX to arrive early enough to t
Hi David,
On Wed, Apr 18, 2018 at 11:00 PM, David Miller wrote:
> From: Jassi Brar
> Date: Wed, 18 Apr 2018 18:27:59 +0530
>
>> Just to make sure, let me please mention that c009f413b79de52 and
>> 9a00b697ce31e are very much needed in stable kernel. Without these we
>&
On 26 May 2018 at 11:46, Ard Biesheuvel <ard.biesheu...@linaro.org> wrote:
> On 26 May 2018 at 05:44, Jassi Brar <jaswinder.si...@linaro.org> wrote:
>> On 26 May 2018 at 08:56, Jassi Brar <jaswinder.si...@linaro.org> wrote:
>>> On 26 May 2018 at 01:07, Robin
On 26 May 2018 at 08:56, Jassi Brar <jaswinder.si...@linaro.org> wrote:
> On 26 May 2018 at 01:07, Robin Murphy <robin.mur...@arm.com> wrote:
>> On Sat, 26 May 2018 00:33:05 +0530
>> Jassi Brar <jaswinder.si...@linaro.org> wrote:
>>
>>> On 2
On 26 May 2018 at 01:07, Robin Murphy <robin.mur...@arm.com> wrote:
> On Sat, 26 May 2018 00:33:05 +0530
> Jassi Brar <jaswinder.si...@linaro.org> wrote:
>
>> On 25 May 2018 at 18:20, Ard Biesheuvel <ard.biesheu...@linaro.org>
>> wrote:
>> > The n
On 25 May 2018 at 18:20, Ard Biesheuvel wrote:
> The netsec network controller IP can drive 64 address bits for DMA, and
> the DMA mask is set accordingly in the driver. However, the SynQuacer
> SoC, which is the only silicon incorporating this IP at the moment,
>
Hi Dave,
On Mon, Apr 16, 2018 at 11:16 PM, David Miller <da...@davemloft.net> wrote:
> From: jassisinghb...@gmail.com
> Date: Mon, 16 Apr 2018 12:52:16 +0530
>
>> From: Jassi Brar <jaswinder.si...@linaro.org>
>>
>> Enable TX-irq as well during ndo_open() a
On 3 January 2018 at 21:05, David Miller wrote:
> From: jassisinghb...@gmail.com
> Date: Mon, 1 Jan 2018 10:44:49 +0530
>
>> +#define DRING_TAIL(r)((r)->tail)
>> +
>> +#define DRING_HEAD(r)((r)->head)
>
> These macros do not help readability
Hi Ard,
On Thu, Jan 4, 2018 at 3:07 AM, Ard Biesheuvel
<ard.biesheu...@linaro.org> wrote:
> Hi Jassi,
>
> On 1 January 2018 at 05:14, <jassisinghb...@gmail.com> wrote:
>> From: Jassi Brar <jassisinghb...@gmail.com>
>>
>> This patch adds documentation
On Sat, Dec 23, 2017 at 4:09 PM, Ard Biesheuvel
<ard.biesheu...@linaro.org> wrote:
> On 23 December 2017 at 05:45, <jassisinghb...@gmail.com> wrote:
>> From: Jassi Brar <jaswinder.si...@linaro.org>
>>
>> This driver adds support for Socionext "
On 13 December 2017 at 02:07, Andrew Lunn <and...@lunn.ch> wrote:
> On Tue, Dec 12, 2017 at 10:45:21PM +0530, jassisinghb...@gmail.com wrote:
>> From: Jassi Brar <jassisinghb...@gmail.com>
>>
>> This patch adds documentation for Device-Tree bindings for the
>
Hi Mark,
On Tue, Dec 12, 2017 at 10:59 PM, Mark Rutland <mark.rutl...@arm.com> wrote:
> Hi,
>
> On Tue, Dec 12, 2017 at 10:45:21PM +0530, jassisinghb...@gmail.com wrote:
>> From: Jassi Brar <jassisinghb...@gmail.com>
>>
>> This patch adds
On Wed, Dec 13, 2017 at 2:18 AM, Andrew Lunn wrote:
>> > +static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
>> > +{
>> > + struct phy_device *phydev = priv->ndev->phydev;
>> > + u32 value = 0;
>> > +
>> > + value = phydev->duplex ?
On Tue, Dec 12, 2017 at 10:54 PM, Ard Biesheuvel
wrote:
> On 12 December 2017 at 17:15, wrote:
>> +
>> +static int netsec_netdev_load_microcode(struct netsec_priv *priv)
>> +{
>> + int err;
>> +
>> + err =
On Fri, Dec 1, 2017 at 2:42 PM, Ard Biesheuvel
<ard.biesheu...@linaro.org> wrote:
> Hi Jassi,
>
> On 30 November 2017 at 16:12, <jassisinghb...@gmail.com> wrote:
>> From: Jassi Brar <jassisinghb...@gmail.com>
>>
>> This patch adds documentation for Dev
On 9 September 2017 at 00:21, Florian Fainelli <f.faine...@gmail.com> wrote:
> On 09/08/2017 06:02 AM, Kunihiko Hayashi wrote:
>> From: Jassi Brar <jaswinder.si...@linaro.org>
>>
>> Add RTL8201F phy-id and the related functions to the driver.
>>
>&g
On Wed, Aug 30, 2017 at 10:47 PM, Andrew Lunn wrote:
>> +static int netsec_mac_update_to_phy_state(struct netsec_priv *priv)
>> +{
>> + struct phy_device *phydev = priv->ndev->phydev;
>> + u32 value = 0;
>> +
>> + value = phydev->duplex ?
On Thu, Aug 31, 2017 at 9:36 AM, Florian Fainelli <f.faine...@gmail.com> wrote:
> On August 30, 2017 3:24:17 AM PDT, Jassi Brar <jassisinghb...@gmail.com>
> wrote:
>>Hello,
>>
>>The OGMA/Netsec controller is used in latest SoC from
>>Socionext/
On Wed, Aug 30, 2017 at 8:49 PM, Andrew Lunn <and...@lunn.ch> wrote:
> On Wed, Aug 30, 2017 at 03:55:52PM +0530, Jassi Brar wrote:
>> This patch adds documentation for Device-Tree bindings for the
>> Socionext NetSec Controller driver.
>>
>> Signed-off-by: Jassi
This driver adds support for Socionext "netsec" IP Gigabit
Ethernet + PHY IP used in a variety of their ARM-based ASICs.
Signed-off-by: Jassi Brar <jaswinder.si...@linaro.org>
---
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile
This patch adds documentation for Device-Tree bindings for the
Socionext NetSec Controller driver.
Signed-off-by: Jassi Brar <jaswinder.si...@linaro.org>
---
.../devicetree/bindings/net/socionext-netsec.txt | 46 ++
1 file changed, 46 insertions(+)
create mode
(that could be) on the last revision -->
https://patchwork.kernel.org/patch/4540651/
Of course, I have scanned changes to the drivers/net/ethernet since
last submission and integrated whichever applicable and rebased the
driver on top of last rc.
Thanks.
Jassi Brar (2):
dt-bindings: net:
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