Re: [PATCH 5/7] net: stmmac: Program RX queue size and flow control

2017-03-09 Thread Stephen Warren
On 03/09/2017 12:42 PM, Thierry Reding wrote: On Mon, Feb 27, 2017 at 12:09:02PM +0200, Mikko Perttunen wrote: On 23.02.2017 19:24, Thierry Reding wrote: From: Thierry Reding Program the receive queue size based on the RX FIFO size and enable hardware flow control for

RE: Re: Synopsys Ethernet QoS

2016-12-12 Thread Stephen Warren
Niklas Cassel wrote at Monday, December 12, 2016 9:25 AM: ... > However, I've noticed that NVIDIA has extended the DWC EQoS DT binding, > I don't how easy it would be for them to switch to stmmac's DT binding. > (Adding Stephen Warren to CC.) I don't believe there's any issue switchin

Re: [PATCH V3] dt: net: enhance DWC EQoS binding to support Tegra186

2016-09-08 Thread Stephen Warren
On 09/01/2016 01:02 PM, Stephen Warren wrote: From: Stephen Warren <swar...@nvidia.com> The Synopsys DWC EQoS is a configurable IP block which supports multiple options for bus type, clocking and reset structure, and feature list. Extend the DT binding to define a "compa

Re: [PATCH V2] dt: net: enhance DWC EQoS binding to support Tegra186

2016-09-01 Thread Stephen Warren
On 09/01/2016 01:50 AM, Lars Persson wrote: On 08/31/2016 11:48 PM, Stephen Warren wrote: On 08/31/2016 03:15 AM, Lars Persson wrote: On 08/30/2016 10:50 PM, Stephen Warren wrote: On 08/30/2016 01:01 PM, Rob Herring wrote: On Wed, Aug 24, 2016 at 03:20:46PM -0600, Stephen Warren wrote

[PATCH V3] dt: net: enhance DWC EQoS binding to support Tegra186

2016-09-01 Thread Stephen Warren
From: Stephen Warren <swar...@nvidia.com> The Synopsys DWC EQoS is a configurable IP block which supports multiple options for bus type, clocking and reset structure, and feature list. Extend the DT binding to define a "compatible value" for the configuration contained in NVIDI

Re: [PATCH V2] dt: net: enhance DWC EQoS binding to support Tegra186

2016-08-31 Thread Stephen Warren
On 08/31/2016 03:15 AM, Lars Persson wrote: On 08/30/2016 10:50 PM, Stephen Warren wrote: On 08/30/2016 01:01 PM, Rob Herring wrote: On Wed, Aug 24, 2016 at 03:20:46PM -0600, Stephen Warren wrote: The Synopsys DWC EQoS is a configurable IP block which supports multiple options for bus type

Re: [PATCH V2] dt: net: enhance DWC EQoS binding to support Tegra186

2016-08-30 Thread Stephen Warren
On 08/30/2016 01:01 PM, Rob Herring wrote: On Wed, Aug 24, 2016 at 03:20:46PM -0600, Stephen Warren wrote: From: Stephen Warren <swar...@nvidia.com> The Synopsys DWC EQoS is a configurable IP block which supports multiple options for bus type, clocking and reset structure, and featur

[PATCH V2] dt: net: enhance DWC EQoS binding to support Tegra186

2016-08-24 Thread Stephen Warren
From: Stephen Warren <swar...@nvidia.com> The Synopsys DWC EQoS is a configurable IP block which supports multiple options for bus type, clocking and reset structure, and feature list. Extend the DT binding to define a "compatible value" for the configuration contained in NVIDI

Re: [PATCH] dt: net: enhance DWC EQoS binding to support Tegra186

2016-08-24 Thread Stephen Warren
On 08/24/2016 02:10 AM, Lars Persson wrote: On 08/23/2016 10:47 PM, Stephen Warren wrote: The Synopsys DWC EQoS is a configurable IP block which supports multiple options for bus type, clocking and reset structure, and feature list. Extend the DT binding to define a "compatible

[PATCH] dt: net: enhance DWC EQoS binding to support Tegra186

2016-08-23 Thread Stephen Warren
From: Stephen Warren <swar...@nvidia.com> The Synopsys DWC EQoS is a configurable IP block which supports multiple options for bus type, clocking and reset structure, and feature list. Extend the DT binding to define a "compatible value" for the configuration contained in NVIDI