Re: [PATCH] net: ethernet: ti: cpsw: adjust cpsw fifos depth for fullduplex flow control

2017-05-08 Thread David Miller
From: Grygorii Strashko Date: Mon, 8 May 2017 14:21:21 -0500 > When users set flow control using ethtool the bits are set properly in the > CPGMAC_SL MACCONTROL register, but the FIFO depth in the respective Port n > Maximum FIFO Blocks (Pn_MAX_BLKS) registers remains set to the minimum size > re

[PATCH] net: ethernet: ti: cpsw: adjust cpsw fifos depth for fullduplex flow control

2017-05-08 Thread Grygorii Strashko
When users set flow control using ethtool the bits are set properly in the CPGMAC_SL MACCONTROL register, but the FIFO depth in the respective Port n Maximum FIFO Blocks (Pn_MAX_BLKS) registers remains set to the minimum size reset value. When receive flow control is enabled on a port, the port's a