STA control register has areas of mode and opcodes for opeations. 18 bit is
using for mode selection, where 0 is old MIO/MDIO access method and 1 is
indirect access mode. 19-20 bits are using for setting up read/write
operation(STA opcodes). In current state 'read' is set into old MIO/MDIO mode
wit
On Monday, January 22, 2018 5:00:38 PM CET Ivan Mikhaylov wrote:
> STA control register has areas of mode and opcodes for opeations. 18 bit is
> using for mode selection, where 0 is old MIO/MDIO access method and 1 is
> indirect access mode. 19-20 bits are using for setting up read/write
> operatio
>Something looks wrong here?! The commit message talks about bit 18, 19 and 20.
>However, 0x0800, 0x1000, 0x2000 and are like bit 11, 12 and 13? Furthermore,
>what about the EMAC_STACR_STAC_MASK? shouldn't it be 0x1800 now (or delete it
>since it doesn't look like it's used anywhere?).
Christian, n
On Monday, January 22, 2018 8:01:46 PM CET Ivan Mikhaylov wrote:
> >Something looks wrong here?! The commit message talks about bit 18, 19 and
> >20.
> >However, 0x0800, 0x1000, 0x2000 and are like bit 11, 12 and 13? Furthermore,
> >what about the EMAC_STACR_STAC_MASK? shouldn't it be 0x1800 now (
> So if someone tries to #define EMAC_STACR_STAC_WRITE BIT(18) it would be
> 0x4 instead. This is where the confusion is coming from. Can you please
> at least mention this somewhere that all the bits in the commit message are
> in "MSB 0" format? It's confusing enough as it is ;).
Yeap, sure,
