While this series is more correct from the DMA API point of view, it
is also much heavier as it strictly disables the use of any cache on
all user-space mapped BOs, and is also much more restricted in terms
of which memory it can use.
I have a v4 in the works that lets us use TTM for user-mapped
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
Based on a recent discussion in #radeon, and also my own observation that the
'full' scaling causes no end of confusion among users.
See https://bugs.freedesktop.org/show_bug.cgi?id=80868 for some more details,
although it is more
Signed-off-by: Tobias Klausmann tobias.johannes.klausm...@mni.thm.de
---
.../drivers/nouveau/codegen/nv50_ir_build_util.cpp | 17 +
.../drivers/nouveau/codegen/nv50_ir_build_util.h| 2 ++
2 files changed, 19 insertions(+)
diff --git
Folding for conversions: F32/64-(U16/32, S16/32) and (U16/32, S16/32)-F32
No piglit regressions observed on nv50 and nvc0!
Signed-off-by: Tobias Klausmann tobias.johannes.klausm...@mni.thm.de
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 74 ++
1 file changed, 74
On 2014/7/3 11:20, Ilia Mirkin wrote:
Hello,
A user (cc'd) reported that nouveau's enabling of MSI causes the card
to not work on his setup [1]. I think the situation is that MSI is
just not supported by the underlying motherboard, even though the
card, and probably bridge, support it just
https://bugs.freedesktop.org/show_bug.cgi?id=80865
Aaron Plattner aplatt...@nvidia.com changed:
What|Removed |Added
Assignee|aplatt...@nvidia.com
https://bugs.freedesktop.org/show_bug.cgi?id=80865
Ilia Mirkin imir...@alum.mit.edu changed:
What|Removed |Added
Summary|Hard hang (GPC0/TPC0/MP |[NVE7] Hard hang
On Fri, Jul 4, 2014 at 5:27 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
Based on a recent discussion in #radeon, and also my own observation that the
'full' scaling causes no end of confusion among users.
See
On Thu, Jul 3, 2014 at 8:27 PM, Ben Skeggs skeg...@gmail.com wrote:
On Fri, Jul 4, 2014 at 5:27 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
Signed-off-by: Ilia Mirkin imir...@alum.mit.edu
---
Based on a recent discussion in #radeon, and also my own observation that the
'full' scaling causes
Hi Brian,
From your 01:00.0 VGA compatible controller PCI config register, it supports
1 MSI vector, so I think this
card has no problem. But you didn't answer what's the pci_enable_msi() return
during it enable MSI fail.
You can check PCI bus whether support MSI like:
cat
On Thu, Jul 3, 2014 at 10:35 PM, Yijing Wang wangyij...@huawei.com wrote:
Hi Brian,
From your 01:00.0 VGA compatible controller PCI config register, it
supports 1 MSI vector, so I think this
card has no problem. But you didn't answer what's the pci_enable_msi() return
during it enable
On 2014/7/4 10:43, Ilia Mirkin wrote:
On Thu, Jul 3, 2014 at 10:35 PM, Yijing Wang wangyij...@huawei.com wrote:
Hi Brian,
From your 01:00.0 VGA compatible controller PCI config register, it
supports 1 MSI vector, so I think this
card has no problem. But you didn't answer what's the
On 2014/7/4 10:45, Brian Becker wrote:
Yijing,
cat /sys/bus/pci/devices/\:00\:0e.0/msi_bus returns 1, suggesting
that it supports MSI. However, this 00:0e.0 PCI bridge: PLX
Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa)
is a component of the addin card. Wouldn't the
On Thu, Jul 3, 2014 at 11:09 PM, Yijing Wang wangyij...@huawei.com wrote:
On 2014/7/4 10:43, Ilia Mirkin wrote:
On Thu, Jul 3, 2014 at 10:35 PM, Yijing Wang wangyij...@huawei.com wrote:
Hi Brian,
From your 01:00.0 VGA compatible controller PCI config register, it
supports 1 MSI vector, so
On 2014/7/4 11:30, Ilia Mirkin wrote:
On Thu, Jul 3, 2014 at 11:09 PM, Yijing Wang wangyij...@huawei.com wrote:
On 2014/7/4 10:43, Ilia Mirkin wrote:
On Thu, Jul 3, 2014 at 10:35 PM, Yijing Wang wangyij...@huawei.com wrote:
Hi Brian,
From your 01:00.0 VGA compatible controller PCI config
On Thu, Jul 3, 2014 at 11:56 PM, Yijing Wang wangyij...@huawei.com wrote:
On 2014/7/4 11:30, Ilia Mirkin wrote:
On Thu, Jul 3, 2014 at 11:09 PM, Yijing Wang wangyij...@huawei.com wrote:
On 2014/7/4 10:43, Ilia Mirkin wrote:
On Thu, Jul 3, 2014 at 10:35 PM, Yijing Wang wangyij...@huawei.com
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