flash
(MBM29SL800TE). I attached a patch that adds support for this flash. I
hope it can be included in the main repository. If there is something
that needs to be changed with the patch before inclusion please let me
know.
-Karl Kurbjun
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
that were involved at one point (omap3530.cfg and am3517evm.cfg).
This patch also adds support for the TI Beagleboard xM.
Let me know if you would like anything corrected.
-Karl
>From 1908b27c19905a18a9fa6111694a4df7271b8eef Mon Sep 17 00:00:00 2001
From: Karl Kurbjun
Date: Sat, 18 Sep 2010 09
On 09/18/2010 09:43 AM, Karl Kurbjun wrote:
Hi everyone,
I have included a patch to add support for the DM37x by creating a
unified configuration with the AM35x initial support that was added
with the AM3517evm board configuration file. I added copyrights to
the unified file from what I
On 09/17/2010 03:08 PM, David Brownell wrote:
Presently, I would like to hear about the perceived status> of Cortex-A8,
It gets through OMAP3 bringup. The ROM table
scanning embeds various assumptions; see the
comments in the ARM ADI_V5.c file. I'm not sure
whether it's good to assu
I have been able to run a similar function on the DM37x without halting
the processor. The DM37x is very similar to the OMAP. One thing I
noticed is that the write did not work when the processor was halted
unless I called "mww phys" to set DBGEN. For some reason just "mww" was
failing even
Hi all,
I am trying to use watchpoints with the A8, but they do not appear to be
working. I have some simple test code that demonstrates this:
---
void main()
{
while(1)
{
test_data++;
delay_count =
On 11/09/2010 06:37 PM, David Brownell wrote:
--- On Tue, 11/9/10, 韦东山 wrote:
From: 韦东山
Yes, it can't enable the Cortex core. I delete this line in
the cofigration file:
" jtag configure $_CHIPNAME.jrc -event setup "jtag
tapenable $_CHIPNAME.dap" "
and run "jtag tapenable omap3530.dap"
On Sat, Nov 6, 2010 at 8:42 AM, Øyvind Harboe wrote:
> I've merged Marek's work:
>
> http://repo.or.cz/w/openocd/cortex.git
>
> I'm pleased not only with the result, but how the set of patches
> came about through a great discussion on the list and
> improvement of Marek's original solution!
>
> (
On Wed, Nov 24, 2010 at 10:32 PM, Antonio Borneo
wrote:
> Jon,
> this issue has already been reported by Karl in
> https://lists.berlios.de/pipermail/openocd-development/2010-November/017056.html
>
> the issue is linked with patch in
> https://lists.berlios.de/pipermail/openocd-development/2010-No
On Tue, Nov 30, 2010 at 12:18 AM, Øyvind Harboe wrote:
> If iMX51 is broken and the current CortexA8 workaround code for it
> breaks other CPUs, then I think that the automatic workaround code
> for iMX51 has to be either fixed or removed.
>
> Thoughts?
>
> --
> Øyvind Harboe
>
> Can Zylin Consult
On Mon, Dec 6, 2010 at 12:33 PM, Øyvind Harboe wrote:
> I believe that there might exist a safe default or autodetection
> scheme for a specific family of parts.
>
> Such parts could use a common configuration file which
> did the autodetect/set the robust default frequency.
>
> The responsibility
On 09/28/2011 03:08 AM, Karl Kurbjun wrote:
Hi all,
I have an A9 target where the memory map visible over the AHB versus
what is visible to the processor is slightly different.
On this target the lower 512 kByte block of DDR is not accessible from
the AHB, but the processor is able to see
This patch adds in support to assert warm reset through the ICEPick
controller. The added functionality has been primarily tested on the
AM/DM37x, but it has also been used some on the OMAP4.
-Karl
>From 0347f5ad23786080331ee4d09788c947c7126c28 Mon Sep 17 00:00:00 2001
From: Karl Kurb
rom 69c031d9c515d9f82f5fd6054d980f7b484c759f Mon Sep 17 00:00:00 2001
From: Karl Kurbjun
Date: Sun, 2 Oct 2011 11:28:11 -0600
Subject: [PATCH 3/3] FT2232: Add additional debug information with libftdi when cable connection
fails.
This additional output was helpful when debugging a FTDI device with a broken
EEP
Using the ICEPick reset seems to allow the processor to be halted sooner
and the halt on gdb connection makes the connect process more robust.
>From a69fdf6a0756633a6b562fda34b2cafb070b393f Mon Sep 17 00:00:00 2001
From: Karl Kurbjun
Date: Sun, 2 Oct 2011 11:41:33 -0600
Subject: [PATCH] AM/DM
On 09/29/2011 09:40 AM, Michel JAOUEN wrote:
Hello,
I implemented the flush of L1 and L2 cache for cortex_a.
I added the support of phys memory access through dap apsel 1,
(for this access, a flush is performed, and mmu is disabled)
I also implement va_to_pa mechanism for virt_to_phys.
For
On 10/05/2011 05:32 AM, Michel JAOUEN wrote:
Hello,
Below , you find the answer to your question :
* Is the address supposed to point to the base PL310 address? Yes
, you have to provide the physical address of PL310.
* Why do you call this operation if the target status is unkn
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