Hello All,
> There is another bmp to protel converter from a user in New Zealand. It
> must be obtained from him, it's illegal to pass it on, as I recall. He
> sends it on request, at least he did in the past. I don't have quick
access
> to the information, perhaps someone else does.
It is PCBLO
Yes I think so. I've received Traxmaker files, and if I remember correctly I
had to read them into Protel 2.8, save it, then into 99.
Tony
> -Original Message-
> From: Phillip Stevens [mailto:[EMAIL PROTECTED]]
> Sent: Thursday, April 25, 2002 8:17 PM
> To: Protel EDA Forum
> Subject: [
I have a PCB design which was done in Traxmaker. We are looking to
migrate it to Protel99SE, (and perhaps Cadence).
Has anyone had success importing a Traxmaker design into Protel99SE?
Thanks,
---Phil
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Thanks to all who replied to my question. I'm satisfied now that we should
not have any problems with our PCBs as far as the gold plating is
concerned - although other errors are always possible :)
Thanks also to Brad Verlander. I will chase down that HP article you
mentioned.
Our production de
Dan,
have you found some certain condition where the Short circuit
constraint works? Previously most of us have thought it was broke (a bug),
because we could not get it to do anything correctly in the circumstances
that we tried.
Sincerely,
Brad Velander.
Lead PCB Designer
Norsat Intern
Yes. In Design Rules go to Other tab and select Short Circuit Constraint.
When you pull it up, change both of the Objects Filtered boxes to say Net
Class rather than Whole Board and select All Nets. That will get rid of the
error. However, I would wait until the rest of the DRC is clean, becaus
Michael,
there is a little trick that I have used once and a while when
necessary. Warning, it is not without some perils of it's own though.
You can change your general Board - Board and Different Nets
clearance rule to one for All Nets - All Nets, and Different Nets. The
danger c
I just ran into this, Michael. What worked for me was to use the "Place
Track" command to create a tag trace with no net name, then dropped a Via
on it. Apparently the DRC sees it as copper with No Net, connected to
a via with No Net. Expansions and Spacing rules continue to be observed.
Hope it
I am working with a design that has a large FBGA and each pad on this part
has a via fanout from it. Not all the pads are assigned a net name on this
FBGA. The pins that are not used have no net name and therefore the pad has
no net name but I am still giving it a fan out with a small connection t
Thanks for all the help guys.
In the end I went with gold plating, and specified that the PCB's are
delivered heatshrinked in plastic.
Wayne Bickers
Electronics Engineer
Tru-Test Ltd
> -Original Message-
> From: Waldemar Kulajew [SMTP:[EMAIL PROTECTED]]
> Sent: Wednesday, 24 April 2002
what did you find?
Jerry Fisher
Assoc. Engineer
Pelco
10 Corporate Dr.
Orangeburg NY 10962
(845) 398-8700
[EMAIL PROTECTED]
-Original Message-
From: Jim Vegh [mailto:[EMAIL PROTECTED]]
Sent: Thursday, April 25, 2002 3:13 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Importing a large ima
Thanks for all the responses. I have found what I need and it works great.
Thanks,
Jim
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At 02:58 PM 4/25/2002 +0100, Michael Binning wrote:
>Dave, I have just tried creating a simple design using tracks in arc mode,
>as a test.
>Got to print preview OK, but as soon as I hit the print button, bye bye
>Protel. Locked solid.
The problem may be file-specific, so it is crucial to save
At 11:05 AM 4/25/2002 -0400, Jim Vegh wrote:
>I have search all over the web and the previous forum posts and cannot
>find bmptopcb anywhere.
There is a program which was donated to the user's group in the filespace
for [EMAIL PROTECTED]
http://groups.yahoo.com/group/protel-users/files/Conve
maybe this site will help. It's called the converters paradise.
http://hem.spray.se/joakim.slettengren/
Jerry Fisher
Assoc. Engineer
Pelco
10 Corporate Dr.
Orangeburg NY 10962
(845) 398-8700
[EMAIL PROTECTED]
-Original Message-
From: Jim Vegh [mailto:[EMAIL PROTECTED]]
Sent: Thursday, A
Miker,
Thanks for the info. I have search all over the web and the previous forum
posts and cannot find bmptopcb anywhere. Would you be willing to send it to
me?
Jim
>From: "Robison Michael R CNIN" <[EMAIL PROTECTED]>
>Reply-To: "Protel EDA Forum" <[EMAIL PROTECTED]>
>To: "'Protel EDA Forum'
Dave, I have just tried creating a simple design using tracks in arc mode,
as a test.
Got to print preview OK, but as soon as I hit the print button, bye bye
Protel. Locked solid.
Most odd.
Mike.
I'm having a somewhat similar problem when trying to print
schematics to Adobe Acrobat. Arcs on the right 20% of the
schematic are not printed to the PDF. The effect removes the
rounded portion of gate symbols (And, Or, etc). Anyone seen
this, or have any tips?
I'm running 99SE SP6 on Win'98 with
David,
I cannot support your experience. I am just doing a board containing routes
using arcs on different layers, and the print preview works just fine.
Protel 99 SE SP6, Win2K SP2.
Gisbert Auge
Hi again,
I have deleted and re- routed the arcs in the same way and the bug has
evaporated. What a funny world we live in...
Regards
David Watling
David.Watling@z
> I have just discovered a bug. When using the print-preview tool to print a PCB
>containing 'Arc-mode' tracking, it locks up the application and I have to re-start
>Protel. Otherwise, I have found the print preview tool to be almost excellent.
> 2 questions:
> Is this old news, or have I foun
We are using Protel 99SE with service pack 6 and no problem with the
printing pcb with Arc tracking. Must be some setting or your printer is not
supporting arcs.
Regards
Narinder
- Original Message -
From: <[EMAIL PROTECTED]>
To: "Protel EDA Forum" <[EMAIL PROTECTED]>
Sent: Thursday, Apr
I have just discovered a bug. When using the print-preview tool to print a
PCB containing 'Arc-mode' tracking, it locks up the application and I have
to re-start Protel. Otherwise, I have found the print preview tool to be
almost excellent.
2 questions:
Is this old news, or have I found somethi
Protel99SE SP6 & Win98SE
open a ddb and open a project that is hierarchical.
now Menue -> Tools -> Database Links and perform an update of the schematics
from an DB4 file. A report BOM shows that the partfields have been updated
(they were empty before the Update)
so now close the sch files by
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