In my experience, it can be a bit more complicated than a simple
matter of Track width/Space requirements. Many Euro safety specs are
_much_ tighter than North American specs, in part (I believe) to exclude
foreign competition. Many items, such as connectors, relays, opto-
isolators and other AC ma
Thanks, Dave...
Brian
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Afshin,
Addition of the secondary planes has to be done in a certain way,
or Protel has trouble allocating the plane areas. To add secondary
Split Planes, it's necesary to create "holes" on the Primary Plane
by editing its vertices (ie, by doing Edit Move Polygon Vertices,
selecting the polygon,
Is it the Drill Report that's telling you about the holes?
Or the DRC?
What does the Hole Size Editor Tool list as holes? Anything odd?
Can you locate a zero sized hole on the board from data in the
Text Drill File? One thing to try is to select all zero holes and attempt a
global change to,
Thanks, Robert.
I tried to import it both the ASCII (.PDF) and the default (.PCB) formats.
he .PCB attempt produced the "Unrecognised File Format" error, with a
suggestion that ACCEL files should be loaded as ASCII. So I renamed
the file .PDF and tried to import. All I got was a black screen, and
files are dated 10/06/01, so may be in a pre- P-CAD 2001
format.
Has anyone successfully imported older P-CAD PCB or .SCH files?
Thanks-
Brian Sherer
Foothill Services LLC
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Hi-
Some annotation is mysterious!
>
>1) PLCS = "Places"
>2) BSC = "Between Successive Contacts"; like, "between pad centers".
>
Do these make sense? You'll have to check the drawing to see
Brian
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It's a reference to an e.e. cummings poem called "Buffalo Bill's Defunct";
"How do you like your blue-eyed boy now, Mr. Death?"
At 10:13 AM 11/15/02 -0500, you wrote:
>> From: Rene Tschaggelar [mailto:tschaggelar@;dplanet.ch]
>>
>> Just assuming a mice to
>> be a trivial device that
>> always wo
Glennn, is it possible that with all the reinstalling that the shortcut
is pointing at a secondary link or even a second (possibly backup) copy
of '99SE? It sounds like it's pointing at a link rather than the
executable, in any case.
Brian
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>I'm glad that Mr Rohmberg got his fills filled, but I don't think it was
>from Mr. Sherer's advice, which is, unfortunately, incorrect, I just
>verified it.
I stand correctedThanks. Can't understand how I've never run
into the problem!
Brian
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Chris-
I had second thoughts. You may not be copying, but creating a
polygon on a board having an existing polygon.
Protel gets confused if you create a polygon which lies within
or overlaps another polygon (with a different net name) on the same layer.
See Protel's Help topics. A Split Plane mus
Hi, Chris-
I asume you're doing a Copy of an existing Polygon.
After dropping the polygon, in the Properties Box that appears,
assing it to Net "GND". It will connect to Gnd after repouring.
Alternatively, instead of doing a normal paste, use the "Paste
Special" option, checking the box for "Kee
Ben, we've had good results storing bare boards for many months
in the Saran Wrap sheeting that many fabricators use to bundle
boards for shipping.
Saran has the unique property among commonly available materials
that it is a very good gas and vapor barrier, and will exclude oxygen
from the pac
Hi, Mike-
UL will be happy with spacings that will lead to disaster in
practical application. Use at least the VDE spacing of 8mm
edge to edge. In fact, though, even this is marginal for 1KV;
eventual contamination will cause tracking across the PCB surface.
Motorola had a good Apps Note on apply
JaMi;
To date, all releases of Protel I've loaded have caused .PCB
and .SCH files to open under the highest level Protel installed.
Maybe it simply changes the file type association option under
Windows?? I can't speak to the other issues (which might have
sprung from "The Fog of War" at 5:49 AM
No, he always thought BIG...
see:http://olympicpc.com/quotes/dirksen_senator_everett.html
http://olympicpc.com/quotes/dirksen_senator_everett.html
At 08:50 PM 9/16/02 -0700, you wrote:
>he may be your senator but it was WAY before billions
>it was 'million'
>
>still it makes my point
>
>Dennis
Scott-
If I read your post correctly, it appears that you are placing the
polygons and _then_ assigning them to the selected net, rather
than assigning the polygon to its final net while in the polygon
placement dialog box.
I've gotten mysterious results when trying this for overlapping
polygon
A simple method I've used several times is to indicate on the schematic
the two "select" resistors, calling them out as 0805s, then simply placed
them such that the ends which are commoned on the schematic physically
lie on top of each other with their bodies in-line. Selection is by loading
one o
Hi, all;
A client is having trouble locating a reasonably priced assembly
house for a precision analog PCI card having fairly high density
and requiring scrupulous attention to processing cleanliness.
Board has a few 19mil lead pitch chips along with 26mil and
larger chips, and about 30% throughh
Michael, I've handled this issue by offsetting the Keep Out tracks/arcs
outside the physical edge of the board by a fixed amount, say 10mils.
If the board is to have Polygons or Planes, you may have to create a
temporary set of keepouts to control polygon/plane pours to a wider
clearance; if these
Edi,
I have Eudora 4.0.1 and can find no option for supressing display
of HTML. Where do I find that switch?
Brian
At 09:53 AM 8/16/02 +0200, you wrote:
>
>>
>>I have been trying to use Mozilla for e-mail also, but it seems to have a
>>bug that crashes when trying to import large message folder
Deselect "Remove Dead Copper" on Polygon Pour Setup Dialog box.
Repour Polygon(s).
Brian
At 12:10 PM 8/9/02 -0500, you wrote:
>At 12:41 AM 8/10/2002 +0800, Katinka Mills wrote:
>>Hi all,
>>
>>Quick Q,
>>
>>I have a 2 layer PCB with top and bottom ground planes (like to balance up
>>my copper) ho
Yves, I've found that a sure-fire way to avoid netlist conflicts in this
situation is to create a second Schematic part for each IC to be
decoupled, changing its power pin Name from "VCC" or "VDD" to
something like "U25_PWR". Replace the original Sch component
with this part. This will netlist cor
Brad-
The "1mil" shop was located in Europe. They claimed to
be doing precision fab at die level, so may have been
sputtering the plating (or some other James Bond type
method). Needless to say, their quote was astronomical
and went directly to the circular file
As the old saying goes, "Be c
Tim-
I use a method very similar to Mr. Velander with good results
(ie, no calls from the Fab CAM operators). My Fab drawing is
added to the Drill Drawing Layer so as to be included with the
Drill Size listing, and is included with all jobs.
A few notes:
1- Explicitly call out all hole sizes use
InterestingIn my neck of the woods (NW US), to "bag" something is to
abandon it
as useless, but without extreme prejudice
Brian
At 07:32 PM 7/30/02 -0700, you wrote:
>In the US, 'to bag' generally means the same thing. I think some places it
>means to 'capture' or 'get lucky' but I'm not
I guess I'm in the minority, but I find the Protel user interface quite
powerful
and, for the most part, intuitively consistent across servers. The
labyrinthine
command interface of Autocad and PCB packages using a similar interface
(like Pads) are tedious and extremely trying.
Protel is missing
I have Adobe Acrobat v5.0.5 under Win'98 and '99SE SP6 with 512 MB RAM,
and it works OK on Schematic files with the exception that arcs of certain
diameters located within 20% of the right edge of the sheet are not
rendered at all.
This includes such objects as the arcs used to create AND gates
Not quite.We provide a service, not manufacture a product. Our
clients set the target product functionality, and specify performance.
If the computer trade were based on a service model, I'm sure we'd
have much better software functionality.
Brian
>you forgot: "Buy this new PCB. It has new
Thanks, Matt. I think you should have prefaced your attachment
by saying "Now, don't shoot the messenger, but"
Does anyone know if the offending driver might have been included
in one of Microsoft's "Critical Updates"? I'm still running Win'98 with
99SE SP6, but suddenly began to experience s
With Protel open to a .ddb and Documents tab selected,
choose "New PCB Document", then select "Wizards" tab.
This will allow you to generate a standard card in several
formats. You'll want the AT card, either long or short.
The Schematic symbol may be available, but I wasn't able
to find it quick
>It is a female
>by nature and has mood swings to boot.
!
Vive la difference!
Think of autorouters as as job security
-Brian
* Tracking #: 19A89E2E4577644A85AD72E9AF83E5AB58E45961
*
***
Ken, I've done this by creating cutouts of the proper size (tiny)
using say four 1mil holes on 5mil pads. I included on the Drill Drawing
a detail showing routing a rectangular cutout from these sets of
1mil holes. You _must specify_ "Plate Through" for all these special
cutouts. Note that you wo
Mike, I agree with your comments regarding M$. Much of the software
industry is adopting what I think of as the "Exploding Menu" school of
software design. I don't _want_ an animated desktop. Like you, I
have a service bureau. My machine is a tool, not a gameboy, and anything
that distracts from
My personal reservation to Altium's new pricing structure is that
both Microsoft and Protel have historically used a "Toss it and catch it"
model for software development: Write the code and release it with known
bugs, and repair such bugs as become negative sales issues. No other
type of prod
Sure. Begin placing a Graphical Line (NOT a wire) on the schematic,
then hit the Tab key to open the polyline properties dialog box. Pull
down the line style tab and select dashed or dotted as desired.
Once finished with the dashed line, you'll have to reselect solid line.
You can also edit ex
Hi, Dennis;
I use, and have often seen used, the slash (/) for negation on
pin signal names as well as Net names. Seems to work OK.
eg: "/OUTPUT" for negative output.
Brian
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Thanks to both Jon and Jason. Think I'll give it a try, next
major crash.
Brian
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Hi, all;
Has anyone successfully run 99SE SP6 on any flavor of Linux?
Any tips on Linux version/vendor, or GUI?
Thanks for any info
Brian Sherer
Foothill Services LLC
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Be sure the active screen is maximized, too; at times it may appear
to be maximized but is not. I've seem some unusual effects when
the cursor reaches the edge of a non-maximized screen in PCB and SCH.
Brian
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Hi, Matt;
Let me ask first how you created the circular board with the
segmented Planes. Did you draw a circle using a 50mil arc of,
say, Internal Plane 1, then add 50 mil Tracks of Internal Plane 1
copper to force segmentation of the circle? If so, you are creating
endless headaches for yoursel
I just ran into this, Michael. What worked for me was to use the "Place
Track" command to create a tag trace with no net name, then dropped a Via
on it. Apparently the DRC sees it as copper with No Net, connected to
a via with No Net. Expansions and Spacing rules continue to be observed.
Hope it
I'm having a somewhat similar problem when trying to print
schematics to Adobe Acrobat. Arcs on the right 20% of the
schematic are not printed to the PDF. The effect removes the
rounded portion of gate symbols (And, Or, etc). Anyone seen
this, or have any tips?
I'm running 99SE SP6 on Win'98 with
Another quick method is to do top and bottom pours with the "Remove
Dead Copper" option turned off, then simply drop vias on dead copper
that should be connected to the opposite side Ground pour. Most areas
can be dealt with quickly this way. Of course, one side or the other
must be connected t
Yes. This is how the Fab houses have historically spec'd expansions.
Brian
At 03:01 PM 4/19/02 -0700, you wrote:
>
>Has anyone noticed that you get exactly half the clearance you specify on a
>power plane clearance rule? In other words to get a 10 mil ring around a
>pad or via that does not c
Ian Wilson's questions are good ones. Did you enter the schematic and
generate the Netlist? If you entered the schematic, and if it is an option,
I would begin by resetting all Identifiers to ?. That is, do a global change
of all R's to R?, all C's to C?, etc, for all components. Then use Tools/
Shuping, I've had similar problems in Protel'98 which were
traced to duplicate Identifiers giving duplicate pins; apparently
causing a database that was too large for either Protel or my
machine to handle in available memory. Something similar
happened reloading a netlist to an existing layout ha
Here in the land of Microsoft, we call it Vaporware.
Not to be confused with bugs, which are called "Undocumented Features"
Brian
At 07:42 AM 4/12/02 +1000, you wrote:
>Isn't the real reason that it's release will be later than first
>announced the fact that it clearly isn't ready yet!
>
>I
It's useful to have a pad of finite size so that it'll be visible as a
reminder
in case you have "(Show) Pad Holes" turned off on the Design\Options
panel. Best to make an NPT pad up as a single-layer pad on the Drill
Drawing Layer; this avoids creating objects on the Mask Layers during
Gerber ge
There are several technologies used for keypads; among them are
snap-domes (metal domes with 3 tabs that enter plated holes, and
a bump that contacts a center pcb pad); elastomeric (an insulating
plastic sheet with round conductive rubber pads that contact
matching conductive grids located on the
Not _this_ BrianThe Library Brian logged on as a visitor.
Brian Sherer
Foothill Services LLC
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A useful guideline is to look to the various standards for conductor spacing
to yeild a safe voltage standoff. A reasonable minimum of 8mm for 2500V
standoff between conductors on the same side of the board will give you
a good chance to avoid "tracking" or arcing along the surface due to
normal
It's done in PCB rather than Schematic.
If you only want to hide the Part Types normally shown on the
PCB Footprint, you can globally change them to hidden, by
clicking on any component on the PCB to pullup the edit panel,
select global, go to the Comment Tab, and check the Hidden box.
This will
Hi, Kiernan;
Using Mid Layers with Polygon Pours and routed tracks works fairly well.
Obviously, breaks in the Internal Plane can wreak havoc with controlled-
impedance traces, switching-supply circuitry and the like, so it's good
to confine this approach to areas where Plane continuity isn't cri
Try Flexibox, distributed by Powerbox USA:
http://www.powerbox.se/
They have a range of sizes. Somewhat pricey, but sturdy and well
thought out. Can't screen the front panel, though, so plan on added
label cost.
Brian
At 01:43 PM 3/12/02 -0500, you wrote:
>I looking for a North American su
Tim, in my experience DXF problems with splines and arcs seem
to be import round-off errors.
I've had some luck in regenerating the complex curve by manually re-entering
the arcs by opening the original file in Autocad while the imported file is
open
in Protel, then editing the arcs one by one
LLoyd, I'd still suspect a hidden Identifier or Component Type
associated with one of the parts that select when you Select
Outside the board. Be sure to have Used Layers turned on,
on the display options panel.
Select the few components within the board that seem to have
some part of them outsi
Geoff, my experience with mirroring layouts (now several years in the past)
was so disasterous that I gave it up. Connectivity of all copper objects
became completely unreliable, not to say trash.
Can 99SE/SP6 in fact mirror layouts and retain connectivity? Or are you
referring to mirroring as an
Mike, I've run into trouble by assuming the board house
would equalize dielectric thickness in the layer stack.
Some do, some don't.
I now add a fab note to "equalize dielectric thickness +/- 10%"
to get an approximately known dielectric thickness. Or you
can specify the prepreg thickness between
if that's what you're seeing, can be deleted if un-needed.
Brian Sherer
Foothill Services LLC
At 08:47 AM 2/15/02 -0800, you wrote:
>Sean,
> could you explain a bit better. I have not seen anything which comes
>close to your description.
>You are talking about Paste S
y an issue; unless a schematic
is _heavily annotated, a Tango-format netlist usually suffices for PCB
input data, along with the necessary mechanical and electrical
requirements. But ask for references!
Brian Sherer
At 05:56 PM 1/29/02 -0500, you wrote:
>Any Protel designers in the Toronto are
Thanks to Phil and Mark - found it with no problem. I'll have
to check the list of tools carefully; maybe there's a tool for
Associative Dimensioning hidden in there.:)
Brian
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Hi-
I find the Length of Selected Trace function in v2.8 very
useful for adjusting clock lines and microstrips, and keep 2.8
around for this sole purpose.
Has anyone located this function in 99SE?
Brian Sherer
Foothill Services LLC
the extra polygon
as a
clearance
errors at each point of the polygon.
This is the only way I have found to remove Phantom objects regardless of
their
size/complexity, and is useful for designs where repeated polygon edits have
trashed the database.
Brian Sherer
Foothill Services LLC
[EMAIL PR
forced to mirror. But it may work to first
lay out all bottom components, flip the board, add top components,
then route all.
Brian Sherer
Foothill Services LLC
Kenmore WA
(425) 483-1546
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