On 17/09/2024 17:31, Peter Xu wrote:
On Tue, Sep 17, 2024 at 08:25:06AM +0200, Mattias Nissler wrote:
Mark, thanks for testing and confirming that this doesn't cause any
obvious breakage.
For my curiosity, which path should this patch take to get into
master? Peter, are you going to respin you
;ve given it a quick spin around various PPC
Mac images and it looks good to me, so:
Reviewed-by: Mark Cave-Ayland
Tested-by: Mark Cave-Ayland
My guess is that the current use of dma_memory_unmap() was a misunderstanding/bug
when porting the macio IDE device over to use the byte-aligned block DM
This prevents the IRQs from being leaked when the macio IDE device is used.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Peter Maydell
---
hw/ide/macio.c| 10 ++
include/hw/misc/macio/macio.h | 7 +--
2 files changed, 11 insertions(+), 6 deletions(-)
v2:
- Delete
On 28/06/2024 16:28, Peter Maydell wrote:
On Fri, 28 Jun 2024 at 11:55, Mark Cave-Ayland
wrote:
This prevents the IRQs from being leaked when the macio IDE device is used.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/macio.c| 10 ++
include/hw/misc/macio/macio.h
This prevents the IRQs from being leaked when the macio IDE device is used.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/macio.c| 10 ++
include/hw/misc/macio/macio.h | 5 +
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide
On 27/06/2024 14:37, Akihiko Odaki wrote:
This fixes qemu_irq array leak.
Signed-off-by: Akihiko Odaki
---
hw/isa/vt82c686.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 8582ac0322eb..629d2d568137 100644
--- a/hw/isa/
On 27/06/2024 14:37, Akihiko Odaki wrote:
A function pointer is sufficient for internal usage. Replacing qemu_irq
with one fixes the leak of qemu_irq.
Signed-off-by: Akihiko Odaki
---
include/hw/ppc/mac_dbdma.h | 5 +++--
hw/ide/macio.c | 11 +++
hw/misc/macio/mac_dbdm
On 27/06/2024 14:37, Akihiko Odaki wrote:
macio ide_irq is connected to the IDE bus. This fixes the leak of
ide_irq.
Signed-off-by: Akihiko Odaki
---
hw/ide/macio.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index aca90d04
On 26/06/2024 13:59, Peter Maydell wrote:
On Wed, 26 Jun 2024 at 12:09, Akihiko Odaki wrote:
This suppresses LeakSanitizer warnings.
Signed-off-by: Akihiko Odaki
---
hw/ide/macio.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index aca90d04
ooks like a good tidy-up to me so:
Acked-by: Mark Cave-Ayland
ATB,
Mark.
qdev_init_gpio_in_named() in the commit message above instead.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Reviewed-by: Mark Cave-Ayland
---
hw/sparc/leon3.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c
index d2be900988
On 13/02/2024 13:03, Philippe Mathieu-Daudé wrote:
By passing a DeviceState context to a QDev IRQ handler,
we can simplify and use qdev_init_gpio_in_named() instead
of qdev_init_gpio_in_named_with_opaque().
Suggested-by: Mark Cave-Ayland
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc
On 09/02/2024 11:37, Peter Maydell wrote:
On Thu, 8 Feb 2024 at 18:14, Philippe Mathieu-Daudé wrote:
We should not wire IRQs on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/sun4m.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/spar
On 09/02/2024 11:34, Peter Maydell wrote:
On Thu, 8 Feb 2024 at 18:14, Philippe Mathieu-Daudé wrote:
Inline cpu_create() in order to call
qdev_init_gpio_in_named_with_opaque()
before the CPU is realized.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc64/sparc64.c | 4 +++-
1 file chan
ject_new(cpu_type));
qdev_init_gpio_in_named(DEVICE(cpu), sparc64_cpu_set_ivec_irq,
"ivec-irq", IVEC_MAX);
+qdev_realize(DEVICE(cpu), NULL, &error_fatal);
env = &cpu->env;
env->tick = cpu_timer_create("tick", cpu, tick_irq,
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET);
qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", 0,
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
_unref(SYS_BUS_DEVICE(dma), &error_fatal);
+
+sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
+
+sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
+
sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
ntry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
d_realize(PCIDevice *d, Error **errp)
I see that Zoltan has already commented about checking the success of qdev_realise()
before wiring the sysbus IRQs, so with that fixed:
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
us(i82378_dev, "isa.0"));
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
On 08/01/2024 20:07, Bernhard Beschow wrote:
Am 7. Januar 2024 14:13:44 UTC schrieb Mark Cave-Ayland
:
On 06/01/2024 21:05, Bernhard Beschow wrote:
This series implements relocation of the SuperI/O functions of the VIA south
bridges which resolves some FIXME's. It is part of my via-a
On 06/01/2024 21:05, Bernhard Beschow wrote:
This series implements relocation of the SuperI/O functions of the VIA south
bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t
branch [1] which is an extension of bringing the VIA south bridges to the PC
machine [2]. This branc
On 21/11/2023 09:12, Kevin Wolf wrote:
Am 20.11.2023 um 16:02 hat BALATON Zoltan geschrieben:
On Mon, 20 Nov 2023, Mark Cave-Ayland wrote:
On 20/11/2023 13:42, Kevin Wolf wrote:
Am 20.11.2023 um 14:09 hat BALATON Zoltan geschrieben:
On Mon, 20 Nov 2023, Mark Cave-Ayland wrote:
On 19/11
On 20/11/2023 13:42, Kevin Wolf wrote:
Am 20.11.2023 um 14:09 hat BALATON Zoltan geschrieben:
On Mon, 20 Nov 2023, Mark Cave-Ayland wrote:
On 19/11/2023 21:43, BALATON Zoltan wrote:
On Thu, 16 Nov 2023, Mark Cave-Ayland wrote:
This series adds a simple implementation of legacy/native mode
On 20/11/2023 13:30, BALATON Zoltan wrote:
On Mon, 20 Nov 2023, BALATON Zoltan wrote:
On Mon, 20 Nov 2023, Mark Cave-Ayland wrote:
On 19/11/2023 21:43, BALATON Zoltan wrote:
On Thu, 16 Nov 2023, Mark Cave-Ayland wrote:
This series adds a simple implementation of legacy/native mode switching
On 19/11/2023 21:43, BALATON Zoltan wrote:
On Thu, 16 Nov 2023, Mark Cave-Ayland wrote:
This series adds a simple implementation of legacy/native mode switching for PCI
IDE controllers and updates the via-ide device to use it.
The approach I take here is to add a new pci_ide_update_mode
On 19/11/2023 21:43, BALATON Zoltan wrote:
On Thu, 16 Nov 2023, Mark Cave-Ayland wrote:
This series adds a simple implementation of legacy/native mode switching for PCI
IDE controllers and updates the via-ide device to use it.
The approach I take here is to add a new pci_ide_update_mode
h for Zoltan's PPC
images whilst paving the way for future improvements after 8.2.
Signed-off-by: Mark Cave-Ayland
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-10/msg05403.html
v3:
- Rebase onto master
- Move ide_portio_list[] and ide_portio_list2[] to IDE core to prevent
duplication i
These definitions are present in ioport.c which is currently only available when
CONFIG_IDE_ISA is enabled. Move them to the IDE core so that they can be made
available to PCI IDE controllers that support switching to legacy mode.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/core.c
evice BARs
after the device itself has been reset.
Remove the setting of the default BAR addresses from via_ide_reset() to ensure
there is no doubt that these values are never exposed to the guest.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/via.c | 5 -
1 file changed, 5 deletions(-)
diff --
setting of PCI_INTERRUPT_PIN during PCI
bus reset since this is now managed by pci_ide_update_mode(). This ensures that
the device configuration is always consistent with respect to the currently
selected mode.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/via.c | 39
t an issue since if a PCI IDE
controller has been switched to native mode then its BARs will need to be
programmed.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/pci.c | 84
include/hw/ide/pci.h | 1 +
2 files changed, 85 insertions(+)
diff --gi
On 07/11/2023 11:11, Kevin Wolf wrote:
Am 06.11.2023 um 23:41 hat Mark Cave-Ayland geschrieben:
On 06/11/2023 14:12, Kevin Wolf wrote:
Hi Kevin,
Thanks for taking the time to review this. I'll reply inline below.
Am 25.10.2023 um 00:40 hat Mark Cave-Ayland geschrieben:
This function
On 07/11/2023 10:43, Kevin Wolf wrote:
Am 06.11.2023 um 17:13 hat BALATON Zoltan geschrieben:
On Mon, 6 Nov 2023, Kevin Wolf wrote:
Am 25.10.2023 um 00:40 hat Mark Cave-Ayland geschrieben:
Allow the VIA IDE controller to switch between both legacy and native modes by
calling
On 06/11/2023 19:15, Alex Bennée wrote:
A lot of our vhost-user stubs are large chunks of boilerplate that do
(mostly) the same thing. This series continues the cleanups by
splitting the vhost-user-base and vhost-user-generic implementations.
After adding a new vq_size property the rng, gpio and
On 06/11/2023 14:12, Kevin Wolf wrote:
Hi Kevin,
Thanks for taking the time to review this. I'll reply inline below.
Am 25.10.2023 um 00:40 hat Mark Cave-Ayland geschrieben:
This function reads the value of the PCI_CLASS_PROG register for PCI IDE
controllers and configures the PCI BAR
setting of PCI_INTERRUPT_PIN during PCI
bus reset since this is now managed by pci_ide_update_mode(). This ensures that
the device configuration is always consistent with respect to the currently
selected mode.
Signed-off-by: Mark Cave-Ayland
Tested-by: BALATON Zoltan
Tested-by: Bernhard Beschow
evice BARs
after the device itself has been reset.
Remove the setting of the default BAR addresses from via_ide_reset() to ensure
there is no doubt that these values are never exposed to the guest.
Signed-off-by: Mark Cave-Ayland
Tested-by: BALATON Zoltan
Tested-by: Bernhard Beschow
---
hw/ide/
h for Zoltan's PPC
images whilst paving the way for future improvements after 8.2.
Signed-off-by: Mark Cave-Ayland
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-10/msg05403.html
v2:
- Rebase onto master
- Mask the bottom 4 bits of PCI_CLASS_PROG in pci_ide_update_mode() in patch 1
- Add
t an issue since if a PCI IDE
controller has been switched to native mode then its BARs will need to be
programmed.
Signed-off-by: Mark Cave-Ayland
Tested-by: BALATON Zoltan
Tested-by: Bernhard Beschow
---
hw/ide/pci.c | 90
include/hw/ide/
On 24/10/2023 08:08, Bernhard Beschow wrote:
Am 23. Oktober 2023 21:06:11 UTC schrieb Mark Cave-Ayland
:
On 23/10/2023 18:19, Bernhard Beschow wrote:
Am 22. Oktober 2023 22:06:30 UTC schrieb Bernhard Beschow :
Am 19. Oktober 2023 13:04:51 UTC schrieb Mark Cave-Ayland
:
This function
On 20/10/2023 00:09, BALATON Zoltan wrote:
On Thu, 19 Oct 2023, Mark Cave-Ayland wrote:
Allow the VIA IDE controller to switch between both legacy and native modes by
calling pci_ide_update_mode() to reconfigure the device whenever PCI_CLASS_PROG
is updated.
This patch also moves the setting
On 23/10/2023 18:19, Bernhard Beschow wrote:
Am 22. Oktober 2023 22:06:30 UTC schrieb Bernhard Beschow :
Am 19. Oktober 2023 13:04:51 UTC schrieb Mark Cave-Ayland
:
This function reads the value of the PCI_CLASS_PROG register for PCI IDE
controllers and configures the PCI BARs and/or IDE
On 22/10/2023 23:10, Bernhard Beschow wrote:
Am 19. Oktober 2023 13:04:50 UTC schrieb Mark Cave-Ayland
:
This series adds a simple implementation of legacy/native mode switching for PCI
IDE controllers and updates the via-ide device to use it.
The approach I take here is to add a new
On 22/10/2023 23:06, Bernhard Beschow wrote:
Am 19. Oktober 2023 13:04:51 UTC schrieb Mark Cave-Ayland
:
This function reads the value of the PCI_CLASS_PROG register for PCI IDE
controllers and configures the PCI BARs and/or IDE ioports accordingly.
In the case where we switch to legacy mode
ensure that if a PCI device
reset occurs then the device configuration is always consistent.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/via.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/hw/ide/via.c b/hw/ide/via.c
index fff23803a6..e6278dd419 100644
h for Zoltan's PPC
images whilst paving the way for future improvements after 8.2.
Signed-off-by: Mark Cave-Ayland
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-10/msg05403.html
Mark Cave-Ayland (2):
ide/pci.c: introduce pci_ide_update_mode() function
hw/ide/via: implement legacy/n
t an issue since if a PCI IDE
controller has been switched to native mode then its BARs will need to be
programmed.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/pci.c | 90
include/hw/ide/pci.h | 1 +
2 files changed, 91 insertions(+)
diff --gi
On 17/10/2023 15:01, Philippe Mathieu-Daudé wrote:
Pull the 'dma' property to the core XHCI type, declare
its link statically using DEFINE_PROP_LINK().
Signed-off-by: Philippe Mathieu-Daudé
---
hw/usb/hcd-xhci-sysbus.c | 4
hw/usb/hcd-xhci.c| 2 ++
2 files changed, 2 insertion
r,
+ TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
qdev_prop_allow_set_link_before_realize,
- OBJ_PROP_LINK_STRONG);
-object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
- (Object **)&s->dma_mr,
- qdev_prop_allow_set_link_before_realize,
- OBJ_PROP_LINK_STRONG);
}
static const TypeInfo xlnx_csu_dma_info = {
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
mp;s->parent_obj;
+VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(s);
SCSIDevice *d;
int rc;
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
(&g->parent_obj.parent_obj, g->ctrl_vq);
+vgc->handle_ctrl(VIRTIO_DEVICE(g), g->ctrl_vq);
}
static void virtio_gpu_handle_cursor(VirtIODevice *vdev, VirtQueue *vq)
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
;s->dev, (uint8_t *)&s->blkcfg,
- s->parent_obj.config_len, errp);
+ VIRTIO_DEVICE(s)->config_len, errp);
if (ret < 0) {
qemu_chr_fe_disconnect(&s->chardev);
vhost_dev_cleanup(&s->dev);
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
On 09/10/2023 10:59, Alex Bennée wrote:
A lot of our vhost-user stubs are large chunks of boilerplate that do
(mostly) the same thing. This series continues the cleanups by
splitting the vhost-user-base and vhost-user-generic implementations.
After adding a new vq_size property the rng, gpio and
On 09/10/2023 10:59, Alex Bennée wrote:
Lets keep a cleaner split between the base class and the derived
vhost-user-device which we can use for generic vhost-user stubs. This
includes an update to introduce the vq_size property so the number of
entries in a virtq can be defined.
Signed-off-by:
On 30/08/2023 17:14, Alexander Graf wrote:
Hi Alex,
Apple defines a new "vmapple" machine type as part of its proprietary
macOS Virtualization.Framework vmm. This machine type is similar to the
virt one, but with subtle differences in base devices, a few special
vmapple device additions and a v
On 30/08/2023 17:14, Alexander Graf wrote:
Hi Alex,
Apple has its own virtio-blk PCI device ID where it deviates from the
official virtio-pci spec slightly: It puts a new "apple type"
field at a static offset in config space and introduces a new barrier
command.
This patch first creates a mech
On 30/08/2023 17:14, Alexander Graf wrote:
Hi Alex,
Instead of device tree or other more standardized means, VMApple passes
platform configuration to the first stage boot loader in a binary encoded
format that resides at a dedicated RAM region in physical address space.
This patch models this
On 30/08/2023 17:14, Alexander Graf wrote:
Hi Alex,
The VMApple machine exposes AUX and ROOT block devices (as well as USB OTG
emulation) via virtio-pci as well as a special, simple backdoor platform
device.
This patch implements this backdoor platform device to the best of my
understanding. I
On 30/08/2023 17:14, Alexander Graf wrote:
Hi Alex,
VMApple contains an "aes" engine device that it uses to encrypt and
decrypt its nvram. It has trivial hard coded keys it uses for that
purpose.
Add device emulation for this device model.
Signed-off-by: Alexander Graf
---
hw/vmapple/aes.c
On 30/08/2023 17:14, Alexander Graf wrote:
Hi Alex,
In addition to the ISA and PCI variants of pvpanic, let's add an MMIO
platform device that we can use in embedded arm environments.
Signed-off-by: Alexander Graf
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
v
On 16/08/2023 12:30, Waldemar Brodkorb wrote:
Hi,
Philippe Mathieu-Daudé wrote,
Hi Waldemar
On 13/8/23 09:46, Waldemar Brodkorb wrote:
Hi,
I am using Qemu 8.0.3 and getting this error:
qemu-system-m68k: ../hw/scsi/scsi-disk.c:557: scsi_write_data: Assertion
`r->req.aiocb == NULL' failed.
On 12/06/2023 10:21, Bernhard Beschow wrote:
Am 9. Juni 2023 18:51:16 UTC schrieb Mark Cave-Ayland
:
This will enable CMD646-specific fields to be added to CMD6464IDEState in
future.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/cmd646.c | 4 +++-
include/hw/ide/cmd646.h | 38
This will enable CMD646-specific fields to be added to CMD6464IDEState in
future.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/cmd646.c | 4 +++-
include/hw/ide/cmd646.h | 38 ++
2 files changed, 41 insertions(+), 1 deletion(-)
create mode 100644
This is to allow us to use the cmd646_bmdma_ops name for the CMD646
device-specific registers in the next commit.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/cmd646.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index a3e227fba7
Signed-off-by: Mark Cave-Ayland
---
hw/ide/cmd646.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index a68357c1c5..20f1e41d57 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -96,7 +96,7 @@ static uint64_t bmdma_read
using aliases onto the
existing BMDMAState memory region.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/cmd646.c | 111 +++-
include/hw/ide/cmd646.h | 4 ++
2 files changed, 90 insertions(+), 25 deletions(-)
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
Signed-off-by: Mark Cave-Ayland
---
hw/alpha/dp264.c | 4 ++--
hw/sparc64/sun4u.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c
index 03495e1e60..f2affecad9 100644
--- a/hw/alpha/dp264.c
+++ b/hw/alpha/dp264.c
@@ -13,7 +13,7
20f (prio 0, i/o): cmd646-bmdma-ioport
The series was tested by confirming that breakpoints on the CMD646-specific
BMDMA registers were being hit and that my test Debian install ISO still
boots under qemu-system-sparc64.
Signed-off-by: Mark Cave-Ayland
[1] https://patchew.org/QEMU/20230422150728.1
DeviceClass *k = PCI_DEVICE_CLASS(klass);
dc->reset = piix_ide_reset;
+dc->vmsd = &vmstate_ide_pci;
k->realize = pci_piix_ide_realize;
k->exit = pci_piix_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_INTEL;
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
+ | (bm->status & ~val & (BM_STATUS_ERROR | BM_STATUS_INT));
}
static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
CI_DEVICE_CLASS(klass);
dc->reset = piix_ide_reset;
+dc->vmsd = &vmstate_ide_pci;
k->realize = pci_piix_ide_realize;
k->exit = pci_piix_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_INTEL;
Thanks for confirming that the migration still works!
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
al & 0x60) | (bm->status & 1) | (bm->status & ~val &
0x06);
+bmdma_status_writeb(bm, val);
break;
default:;
}
Otherwise looks good to me:
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
On 13/05/2023 13:21, Bernhard Beschow wrote:
Am 3. Mai 2023 19:52:41 UTC schrieb Mark Cave-Ayland
:
On 27/04/2023 19:15, Bernhard Beschow wrote:
Am 27. April 2023 10:52:17 UTC schrieb Mark Cave-Ayland
:
On 26/04/2023 21:14, Bernhard Beschow wrote:
Am 26. April 2023 18:18:35 UTC schrieb
On 13/05/2023 12:53, Bernhard Beschow wrote:
Am 27. April 2023 12:31:10 UTC schrieb Mark Cave-Ayland
:
On 26/04/2023 19:25, Bernhard Beschow wrote:
Am 26. April 2023 11:33:40 UTC schrieb Mark Cave-Ayland
:
On 22/04/2023 16:07, Bernhard Beschow wrote:
isa_get_irq() asks for an ISADevice
On 27/04/2023 13:55, BALATON Zoltan wrote:
On Thu, 27 Apr 2023, Mark Cave-Ayland wrote:
On 27/04/2023 00:24, BALATON Zoltan wrote:
On Wed, 26 Apr 2023, Bernhard Beschow wrote:
Am 26. April 2023 11:41:54 UTC schrieb Mark Cave-Ayland
:
On 22/04/2023 16:07, Bernhard Beschow wrote:
Allows to
On 27/04/2023 19:15, Bernhard Beschow wrote:
Am 27. April 2023 10:52:17 UTC schrieb Mark Cave-Ayland
:
On 26/04/2023 21:14, Bernhard Beschow wrote:
Am 26. April 2023 18:18:35 UTC schrieb Bernhard Beschow :
Am 26. April 2023 11:37:48 UTC schrieb Mark Cave-Ayland
:
On 22/04/2023 16:07
On 26/04/2023 19:25, Bernhard Beschow wrote:
Am 26. April 2023 11:33:40 UTC schrieb Mark Cave-Ayland
:
On 22/04/2023 16:07, Bernhard Beschow wrote:
isa_get_irq() asks for an ISADevice which piix-ide doesn't provide.
Passing a NULL pointer works but causes the isabus global to be used
On 27/04/2023 00:24, BALATON Zoltan wrote:
On Wed, 26 Apr 2023, Bernhard Beschow wrote:
Am 26. April 2023 11:41:54 UTC schrieb Mark Cave-Ayland
:
On 22/04/2023 16:07, Bernhard Beschow wrote:
Allows to unexport pci_ide_{cmd,data}_le_ops and models TYPE_SII3112_PCI as a
standard-compliant PCI
On 26/04/2023 19:29, Bernhard Beschow wrote:
Am 26. April 2023 11:21:28 UTC schrieb Mark Cave-Ayland
:
On 22/04/2023 16:07, Bernhard Beschow wrote:
The attributes represent memory regions containing operations which are mapped
by the device models into PCI BARs. Reflect this by changing the
On 26/04/2023 21:14, Bernhard Beschow wrote:
Am 26. April 2023 18:18:35 UTC schrieb Bernhard Beschow :
Am 26. April 2023 11:37:48 UTC schrieb Mark Cave-Ayland
:
On 22/04/2023 16:07, Bernhard Beschow wrote:
Now that PCIIDEState::{cmd,data}_ops are initialized in the base class
constructor
piolist, owner, callbacks,
opaque, name, mr, offset, true);
}
+
+void portio_list_register(PortioList *piolist, Object *owner,
+ const MemoryRegionPortio *callbacks,
+ void *opaque, const char *name,
+ MemoryRegion *mr, uint32_t offset)
+{
+do_portio_list_register(piolist, owner, callbacks,
+opaque, name, mr, offset, false);
+}
Ah, and you beat me to it :) I'm not 100% sold on the previous patch, but this makes
sense so:
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
On 02/03/2023 22:40, Philippe Mathieu-Daudé wrote:
Add ide_init_ioport() which is not restricted to the ISA bus.
(Next commit will use it for a PCI device).
Inspired-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ide/ioport.c
On 02/03/2023 22:40, Philippe Mathieu-Daudé wrote:
Ensure both IDE output IRQ lines are wired.
We can remove the last use of isa_get_irq(NULL).
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ide/piix.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/ide/p
On 02/03/2023 22:40, Philippe Mathieu-Daudé wrote:
Rename ide_init_ioport() as ide_bus_init_ioport_isa() to make
explicit it expects an ISA device. Move the declaration to
"hw/ide/isa.h" where it belongs.
Message-Id: <20230215161641.32663-13-phi...@linaro.org>
Reviewed-by: Richard Henderson
Si
On 02/03/2023 22:40, Philippe Mathieu-Daudé wrote:
In order to allow Frankenstein uses such plugging a PIIX3
IDE function on a ICH9 chipset (which already exposes AHCI
ports...) as:
$ qemu-system-x86_64 -M q35 -device piix3-ide
add a kludge to automatically wires the IDE IRQs on an ISA
bus
On 22/04/2023 16:07, Bernhard Beschow wrote:
Extract bmdma_clear_status() mirroring bmdma_cmd_writeb().
Signed-off-by: Bernhard Beschow
---
include/hw/ide/pci.h | 1 +
hw/ide/cmd646.c | 2 +-
hw/ide/pci.c | 7 +++
hw/ide/piix.c| 2 +-
hw/ide/sii3112.c | 1
quot; : 0x%02"PRIx64
-sii3112_write(int size, uint64_t addr, uint64_t val) "bmdma: write (size %d)
0x%"PRIx64" : 0x%02"PRIx64
+sii3112_bmdma_read(int size, uint64_t addr, uint64_t val) "read (size %d)
0x%"PRIx64" : 0x%02"PRIx64
+sii3112_bmdma_write(int size, uint64_t addr, uint64_t val) "write (size %d)
0x%"PRIx64" : 0x%02"PRIx64
+sii3112_read(int size, uint64_t addr, uint64_t val) "read (size %d) 0x%"PRIx64" :
0x%02"PRIx64
+sii3112_write(int size, uint64_t addr, uint64_t val) "write (size %d) 0x%"PRIx64" :
0x%02"PRIx64
sii3112_set_irq(int channel, int level) "channel %d level %d"
# via.c
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
as(mr, OBJECT(d), "sii3112.bar3", &s->cmd_ops[1], 0,
+ memory_region_size(&s->cmd_ops[1]));
+memory_region_add_subregion_overlap(&d->mmio, 0xc8, mr, 1);
+
mr = g_new(MemoryRegion, 1);
memory_region_init_alias(mr, OBJECT(
On 22/04/2023 16:07, Bernhard Beschow wrote:
Now that PCIIDEState::{cmd,data}_ops are initialized in the base class
constructor there is an opportunity for PIIX to reuse these attributes. This
resolves usage of ide_init_ioport() which would fall back internally to using
the isabus global due to
On 22/04/2023 16:07, Bernhard Beschow wrote:
isa_get_irq() asks for an ISADevice which piix-ide doesn't provide.
Passing a NULL pointer works but causes the isabus global to be used
then. By fishing out TYPE_ISA_BUS from the QOM tree it is possible to
achieve the same as using isa_get_irq().
Th
On 22/04/2023 16:07, Bernhard Beschow wrote:
The attributes represent memory regions containing operations which are mapped
by the device models into PCI BARs. Reflect this by changing the suffic into
"_ops".
Note that in a few commits piix will also use the {cmd,data}_ops but won't map
them in
ster_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);
-
- memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
- &d->bus[1], "via-ide1-cmd", 4);
pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);
bmdma_init_ops(d, &via_bmdma_ops);
I'd also be inclined to agree with Phil/Zoltan re: dropping the trailing "-ops" in
the name, otherwise:
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
per-implementation ops and move everything into hw/ide/pci.c.
The main reason this is a bit difficult now is because of the "Device specific"
registers intertwined with the BMDMA registers, but there's no reason that CMD646
couldn't manually attach a fallback MemoryRegion to PCIIDEState::bmdma_bar and
implement its device-specific registers there.
Unfortunately this isn't just a cut/paste job because there is also some mirroring of
the BMDMA in PCI configuration space which will need some extra untangling: let's
leave this as-is for now since it makes it easier for a follow-up patch to improve
this later. On that basis:
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
On 22/04/2023 16:07, Bernhard Beschow wrote:
Resolves redundant code in every PCI IDE device model.
I think this needs to mention that it's moving the PCIDeviceClass::exit() function
from all of the PCI IDE controller implementations to a common implementation in the
parent PCI_IDE type.
_realize(PCIDevice *dev, Error **errp)
ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
bmdma_init(&d->bus[i], &d->bmdma[i], d);
-d->bmdma[i].bus = &d->bus[i];
ide_bus_register_restart_cb(&d->bus[i]);
}
}
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
n[n], level);
-}
-
static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
{
ViaISAState *s = opaque;
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
] = 0x08; /* Fast IR Config */
pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */
I see there is still some further discussion on the exact datasheet being used,
however the basic mechanism of wiring up the IDE IRQs using
qdev_connect_gpio_out{_named}() in via_isa_realize():
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
CI_DEVICE },
Otherwise:
Reviewed-by: Mark Cave-Ayland
ATB,
Mark.
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