CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook 06/11/12 23:54:39
Modified files:
target-mips: op.c translate.c
Log message:
MIPS FPU fixes (Daniel Jacobowitz).
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=
On Sun, Nov 12, 2006 at 07:02:55PM +0100, Dirk Behme wrote:
> Daniel Jacobowitz wrote:
> >This is with all of the patches I've posted to the
> >list applied
>
> If patches settle down would be nice to get a list of
> patches or a summary patch to be applied in which order
> against which basis.
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook 06/11/12 21:31:18
Modified files:
target-m68k: op.c translate.c
Log message:
M68k build fix.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-m68k/op.c?cvsroot=qemu&r1=1.1&r2=1.2
h
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook 06/11/12 20:55:05
Modified files:
target-mips: op_helper.c
Log message:
Avoid redundant TLB flushes (Daniel Jacobowitz).
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_he
> A patch which flushes up to 1/32nd of the jump buffer indiscriminately
> cuts it to 1:11-1:13.
>
> Here's that last patch. It changes the hash function so that entries
> from a particular page are always grouped together in tb_jmp_cache,
> then finds the possibly two affected ranges and memsets
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Paul Brook 06/11/12 20:40:55
Modified files:
. : cpu-defs.h exec-all.h exec.c
Log message:
Speed up tlb_flush_page (Daniel Jacobowitz).
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-
Daniel Jacobowitz wrote:
This is with all of the patches I've posted to the
list applied
If patches settle down would be nice to get a list of
patches or a summary patch to be applied in which order
against which basis. Seems that I mixed up finding the
correct ones in the correct order ;)
On Sun, Nov 12, 2006 at 11:56:35AM -0500, Daniel Jacobowitz wrote:
> ---
> target-mips/cpu.h |3 ++-
> target-mips/exec.h |1 +
> target-mips/helper.c|2 +-
> target-mips/mips-defs.h |1 +
> target-mips/op_helper.c | 43 +--
>
On Sun, Nov 12, 2006 at 02:29:38PM +, Thiemo Seufer wrote:
> JFTR, increasing the TLB size from 16 to 64 entries made no performance
> difference whatsoever.
I suspect that's because we do about as much eviction. Here's a
different approach. Whenever an entry is evicted by tlbwr, the guest
c
I tried with both pic_set_irq and pic_set_irq_new but nothing happen
(the irq number is 13 and I verified with info irq in qemu monitor).
I tried also to hack i8259.c and the function is not called (I think).
What the first parameter of pic_set_irq_new is referred to?
Another question: why a new v
Paul Brook wrote:
> > > Other targets have a hardware managed TLB. On a hardware managed TLB the
> > > OS treats it as if it were infinite size, and invalidation only occurs
> > > when a OS changes the mappings. On a software managed TLB "flushes" are
> > > more likely to occur during normal operat
On Sun, Nov 12, 2006 at 10:07:15AM -0500, Daniel Jacobowitz wrote:
> > Actually that gives me an idea. When a TLB entry with a different ASID gets
> > evicted we currently flush that page. This should be a no-op because we
> > already did a full flush when the ASID changed.
>
> Let me see if thi
On Sun, Nov 12, 2006 at 02:44:46PM +, Paul Brook wrote:
> > > Other targets have a hardware managed TLB. On a hardware managed TLB the
> > > OS treats it as if it were infinite size, and invalidation only occurs
> > > when a OS changes the mappings. On a software managed TLB "flushes" are
> > >
> > Other targets have a hardware managed TLB. On a hardware managed TLB the
> > OS treats it as if it were infinite size, and invalidation only occurs
> > when a OS changes the mappings. On a software managed TLB "flushes" are
> > more likely to occur during normal operation as TLB slots are reuse
Paul Brook wrote:
> On Sunday 12 November 2006 11:49, Laurent Desnogues wrote:
> > Daniel Jacobowitz a écrit :
> > > Straight qemu with my previously posted MIPS patches takes 6:13 to
> > > start and reboot a MIPS userspace (through init, so lots of fork/exec).
> > >
> > > Thiemo's patch, which flu
On Sunday 12 November 2006 11:49, Laurent Desnogues wrote:
> Daniel Jacobowitz a écrit :
> > Straight qemu with my previously posted MIPS patches takes 6:13 to
> > start and reboot a MIPS userspace (through init, so lots of fork/exec).
> >
> > Thiemo's patch, which flushes the whole jump buffer, cu
Laurent Desnogues wrote:
> Daniel Jacobowitz a écrit :
> >
> >Straight qemu with my previously posted MIPS patches takes 6:13 to
> >start and reboot a MIPS userspace (through init, so lots of fork/exec).
> >
> >Thiemo's patch, which flushes the whole jump buffer, cuts it to 1:40.
> >
> >A patch whi
Daniel Jacobowitz a écrit :
Straight qemu with my previously posted MIPS patches takes 6:13 to
start and reboot a MIPS userspace (through init, so lots of fork/exec).
Thiemo's patch, which flushes the whole jump buffer, cuts it to 1:40.
A patch which finds the entries which need to be flushed
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