Hi everyone,
Here comes a batch of patches for the sh4 user space emulator. I have
another 10 patches in my local queue that are specific to the sh4 user
space emulator, and when I'm done with them I'll spend time on fixing
up the sh4 system emulator. Maybe it's time for some CVS write access?
Un
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/06/12 12:43:48
Modified files:
target-mips: translate_init.c
Log message:
Change 20Kc PRID to a later version.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate
Hello,
Let us see "jal R_MIPS_26":
in current CVS version, op.o, -fno-PIC -mno-abicalls
004eb0d4 :
...
4eb104: afa50010 sw a1,16(sp)
4eb108: 1463 bnez v1,4eb118
4eb10c: nop
4eb110: 0c140e12 jal 503848
4eb114: nop
4eb118: 8fa30010 lw v1,16(sp)
4eb11c: 2021 move a
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/06/12 21:06:52
Modified files:
hw : gt64xxx.c mips_malta.c
Log message:
Revert the Gallileo PCI mapping patch, it conflicts with the supposedly
"generic" PC-style implemen
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/06/12 21:22:17
Modified files:
linux-user/alpha: termbits.h
Log message:
Fix alpha user build failure.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/linux-user/alpha/termbits.h?cvsro
Hi all,
According to the MIPS documentation, the K0 bits in Config0 should be
writable by the software. Currently QEMU only allow to write the low
bit of this field which has three bits. Even if this value is ignored by
QEMU, it should be writable the same way as on real hardware. At least
it shou