CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/09/27 04:47:25
Modified files:
target-ppc : translate.c
Log message:
Implement size bit in PowerPC 64 comparisons.
Allow 'weight' field in sync instruction.
CVSWeb URLs:
http://cvs.s
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/09/27 04:10:43
Modified files:
linux-user : elfload.c mmap.c
Log message:
memset string pages to zero to avoid putting random data on the stack
that may make some program crash at st
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/09/27 01:52:01
Modified files:
. : cpu-exec.c
target-i386: helper.c translate.c
Log message:
SVM VINTR fix, by Alexander Graf.
CVSWeb URLs:
http://cvs.savannah.gnu.
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/09/27 01:32:19
Modified files:
target-ppc : op.c translate.c
Log message:
Fixes for PowerPC 64 rotate and mask instructions.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-ppc/
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/09/27 01:14:15
Modified files:
. : configure
linux-user : elfload.c qemu.h
linux-user/ppc64: syscall.h
target-ppc : translate_init.c
Log message:
N
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/09/26 23:55:32
Modified files:
hw : ppc405.h ppc405_boards.c ppc405_uc.c
Log message:
Add flags to support PowerPC 405 bootinfos variations.
CVSWeb URLs:
http://cvs.savannah.gnu.org/
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/09/26 23:54:22
Modified files:
hw : ppc.c
linux-user : main.c
target-ppc : STATUS cpu.h exec.h helper.c op.c op_helper.c
op_helper.h translat
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/09/26 23:52:07
Modified files:
target-mips: exec.h helper.c op.c
Log message:
hflags computation cleanup, by Aurelien Jarno.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer 07/09/26 23:50:39
Modified files:
target-mips: translate.c
Log message:
Wrap a few often used tests with unlikely(), by Aurelien Jarno.
CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu
Andreas Färber a écrit :
> Am 23.09.2007 um 01:11 schrieb Aurelien Jarno:
>
Aurelien Jarno a écrit :
> Thanks, that's helpful, it looks like the "lduba" instructions
> is not
> working correctly in your case. Now I have to find why.
I don't really understand, because that i
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Jocelyn Mayer 07/09/26 23:01:49
Modified files:
linux-user : qemu.h syscall.c
Log message:
Convert syscall arguments and return value from long to int or
target_long.
CVSWeb URLs:
http://cvs.savannah.gnu.or
The linux-user getpriority() syscall goes through the libc wrapper.
This causes a problem because the libc wrapper remaps the return value
from the kernel. This patch calls the kernel getpriority syscall
directly.
Index: qemu/linux-user/syscall.c
==
On 9/26/07, Alexander Voropay <[EMAIL PROTECTED]> wrote:
> <[EMAIL PROTECTED]> wrote:
>
> >>> - QEMU malta emulation is not really complete, to put it mildly
> >> Out of curiosity, what parts did you miss?
> > Like, for example, the PCI stuff. So I can use the network card.
>
> PCI stuff in the QE
On Wed, Sep 26, 2007 at 08:25:18PM +0400, Alexander Voropay wrote:
> >>>- QEMU malta emulation is not really complete, to put it mildly
> >>Out of curiosity, what parts did you miss?
> >Like, for example, the PCI stuff. So I can use the network card.
>
> PCI stuff in the QEMU/Malta works fine, bu
<[EMAIL PROTECTED]> wrote:
- QEMU malta emulation is not really complete, to put it mildly
Out of curiosity, what parts did you miss?
Like, for example, the PCI stuff. So I can use the network card.
PCI stuff in the QEMU/Malta works fine, but pseudo-bootrom
does not perform PCI enumeration a
On Wed, Sep 26, 2007 at 06:02:21PM +0200, Laurent Vivier wrote:
> Daniel P. Berrange wrote:
> > On Wed, Sep 26, 2007 at 05:47:20PM +0200, Laurent Vivier wrote:
> >> Hi,
> >>
> >> I think there is a bug in qemu RTL8139.
> >>
> >> RTL8139 uses:
> >>
> >> cpu_register_physical_memory(addr + 0, 0x100,
Daniel P. Berrange wrote:
> On Wed, Sep 26, 2007 at 05:47:20PM +0200, Laurent Vivier wrote:
>> Hi,
>>
>> I think there is a bug in qemu RTL8139.
>>
>> RTL8139 uses:
>>
>> cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
>>
>> But in the comment of cpu_register_physical_memory
On Wed, Sep 26, 2007 at 05:47:20PM +0200, Laurent Vivier wrote:
> Hi,
>
> I think there is a bug in qemu RTL8139.
>
> RTL8139 uses:
>
> cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
>
> But in the comment of cpu_register_physical_memory() we have:
>
> "'size' must be
Hi,
I think there is a bug in qemu RTL8139.
RTL8139 uses:
cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
But in the comment of cpu_register_physical_memory() we have:
"'size' must be a multiple of the target page size."
And I think 0x100 is not a multiple of target pa
On Tue, Sep 25, 2007 at 11:06:58PM +0100, Daniel P. Berrange wrote:
>
> By an unfortunate co-incidence I've just hit a similar problem myself. It
> turns out QEMU mouse handling is more complex than I realized. QEMU can
> export several different input devices to a guest OS, PS/2 mouse, VMWare
> m
Fabrice Bellard a écrit :
> Aurelien Jarno wrote:
>> Hi,
>>
>> As written in the MIPS TODO file, the lwl, lwr, ldl, ldr, swl, swr,
>> sdl and sdr instructions are not correctly implemented. In case of
>> exception the BadVAddr register gets the aligned address instead of the
>> unaligned original
Fabrice Bellard a écrit :
> Aurelien Jarno wrote:
>> Hi,
>>
>> As written in the MIPS TODO file, the lwl, lwr, ldl, ldr, swl, swr,
>> sdl and sdr instructions are not correctly implemented. In case of
>> exception the BadVAddr register gets the aligned address instead of the
>> unaligned original
Aurelien Jarno wrote:
Hi,
As written in the MIPS TODO file, the lwl, lwr, ldl, ldr, swl, swr,
sdl and sdr instructions are not correctly implemented. In case of
exception the BadVAddr register gets the aligned address instead of the
unaligned original address.
In addition to that, the store i
Aurelien Jarno wrote:
Hi,
As written in the MIPS TODO file, the lwl, lwr, ldl, ldr, swl, swr,
sdl and sdr instructions are not correctly implemented. In case of
exception the BadVAddr register gets the aligned address instead of the
unaligned original address.
In addition to that, the store i
Hi,
As written in the MIPS TODO file, the lwl, lwr, ldl, ldr, swl, swr,
sdl and sdr instructions are not correctly implemented. In case of
exception the BadVAddr register gets the aligned address instead of the
unaligned original address.
In addition to that, the store instructions are generatin
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