On 12/19/2013 08:37 AM, Peter Crosthwaite wrote:
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov wrote:
Banked coprocessor registers are switched on two cases:
1) Entering or leaving CPU monitor mode with SCR.NS bit set;
2) Setting SCR.NS bit not from CPU monitor mode
Coprocessor register bank
"Aneesh Kumar K.V" writes:
> From: "Aneesh Kumar K.V"
>
> Targets like ppc64 support different typed of KVM, one which use
> hypervisor mode and the other which doesn't. Add a new machine
> property kvm_type that helps in selecting the respective ones
> We also add a new QEMUMachine callback get
On Thu, Dec 19, 2013 at 04:37:22PM +1000, Peter Crosthwaite wrote:
> On Thu, Dec 19, 2013 at 3:51 PM, wrote:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > hw/microblaze/petalogix_ml605_mmu.c | 17 -
> > 1 file changed, 16 insertions(+), 1
On Thu, Dec 19, 2013 at 04:22:47PM +1000, Peter Crosthwaite wrote:
> On Thu, Dec 19, 2013 at 3:51 PM, wrote:
> > From: "Edgar E. Iglesias"
> >
> > Signed-off-by: Edgar E. Iglesias
> > ---
> > target-microblaze/cpu.c |6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/target
Alexander Graf writes:
> On 07.11.2013, at 15:31, Aneesh Kumar K.V
> wrote:
>
>> From: "Aneesh Kumar K.V"
>>
>> With kvm enabled, we store the hash page table information in the hypervisor.
>> Use ioctl to read the htab contents. Without this we get the below error when
>> trying to read the
On Thu, Dec 19, 2013 at 3:51 PM, wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> hw/microblaze/petalogix_ml605_mmu.c | 17 -
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/hw/microblaze/petalogix_ml605_mmu.c
> b/hw/microbla
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov wrote:
> Use c13_context field instead of c13_fcse for CONTEXTIDR register
> definition.
>
> Signed-off-by: Sergey Fedorov
Reviewed-by: Peter Crosthwaite
Add this to your commit msg on your planned single-send. Thanks for
catching this.
Regards,
On 12/19/2013 08:31 AM, Peter Crosthwaite wrote:
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov wrote:
Use c13_context field instead of c13_fcse for CONTEXTIDR register
definition.
This a standalone (I.E. not TZ related) bug?
Regards,
peter
Yes, I think so. Then I will submit this patch se
From: "Aneesh Kumar K.V"
Targets like ppc64 support different typed of KVM, one which use
hypervisor mode and the other which doesn't. Add a new machine
property kvm_type that helps in selecting the respective ones
We also add a new QEMUMachine callback get_vm_type that helps
in mapping the strin
On 12/19/2013 07:12 AM, Peter Crosthwaite wrote:
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov wrote:
Define a new ARM CP register info list for TrustZone Security Extension
feature. Register that list only for ARM cores with TrustZone support.
SCR and VBAR are security extension registers. S
On Thu, Dec 19, 2013 at 3:51 PM, wrote:
> From: "Edgar E. Iglesias"
>
> Signed-off-by: Edgar E. Iglesias
> ---
> target-microblaze/cpu.c |6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index 0ef9aa4..6d39d3d 100644
> --- a/t
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c|8
hw/core/loader.c |3 ++-
hw/intc/apic.c|3 ++-
hw/sparc/sun4m.c |3 ++-
include/exec/cpu-common.h |2 +-
5 files changed, 11 insertions(+), 8 d
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
target-microblaze/cpu.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 0ef9aa4..6d39d3d 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -93,
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
hw/core/qdev-properties-system.c | 46 ++
include/hw/qdev-properties.h |5 +
2 files changed, 51 insertions(+)
diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-propertie
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
hw/microblaze/petalogix_ml605_mmu.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/microblaze/petalogix_ml605_mmu.c
b/hw/microblaze/petalogix_ml605_mmu.c
index 4009ff5..0a13b0e 100644
---
From: "Edgar E. Iglesias"
This is to allow future patches to set properties before cpu::realize().
Reviewed-by: Andreas Färber
Signed-off-by: Edgar E. Iglesias
---
hw/microblaze/petalogix_ml605_mmu.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/microbla
Andreas Färber writes:
> Am 18.12.2013 18:00, schrieb Luiz Capitulino:
>> From: Paolo Bonzini
>>
>> Signed-off-by: Paolo Bonzini
>> Reviewed-By: Igor Mammedov
>> Signed-off-by: Luiz Capitulino
>> ---
>> qom/object.c | 9 +++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> di
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/exec.c b/exec.c
index f606376..2872b86 100644
--- a/exec.c
+++ b/exec.c
@@ -2677,11 +2677,11 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ul
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
include/exec/memory.h |8
memory.c | 12
2 files changed, 20 insertions(+)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 2d0b614..02f4012 100644
--- a/include/exec/memory.
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |6 +++---
hw/net/vmware_utils.h |2 +-
hw/ppc/ppc405_uc.c | 10 +-
hw/ppc/spapr_hcall.c |6 +++---
hw/s390x/s390-virtio-bus.c | 16 +++-
hw/s390x/s39
On Wed, Dec 18, 2013 at 1:12 AM, Peter Maydell wrote:
> Update the generic cpreg support code to also handle AArch64:
> AArch64-visible registers coexist in the same hash table with
> AArch32-visible ones, with a bit in the hash key distinguishing
> them.
>
> Signed-off-by: Peter Maydell
> ---
>
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c|4 ++--
hw/arm/boot.c |9 +
hw/arm/highbank.c |6 +++---
include/exec/cpu-common.h |2 +-
target-i386/helper.c | 16
target-sparc/mmu_hel
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 20 ++--
hw/net/vmware_utils.h |2 +-
hw/ppc/ppc405_uc.c |2 +-
hw/ppc/spapr_hcall.c |4 ++--
hw/s390x/css.c |3 ++-
hw/s390x/s390-virtio-
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 19 +
hw/net/vmware_utils.h |2 +-
hw/pci/msi.c |2 +-
hw/pci/msix.c |2 +-
hw/ppc/ppc405_uc.c | 33 ---
hw/ppc/spapr_hcall.c
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 12 +++---
hw/alpha/dp264.c |5 ++-
hw/net/vmware_utils.h |2 +-
hw/ppc/spapr_hcall.c |6 ++-
hw/s390x/s390-virtio-bus.c |3 +-
hw/s390x/virtio-ccw.c |4 +-
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c| 22 +++
hw/alpha/typhoon.c|2 +-
hw/display/sm501.c|1 +
hw/display/sm501_template.h |2 +-
hw/net/vmware_utils.h |4 +-
hw/
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c | 18 +-
hw/net/vmware_utils.h |2 +-
hw/ppc/spapr_hcall.c |6 +++---
hw/s390x/css.c |3 ++-
hw/s390x/virtio-ccw.c |8 +---
hw/virtio/virti
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cpu-exec.c|5 +-
exec.c| 19 ---
hw/dma/pl080.c|9 ++--
hw/dma/sun4m_iommu.c |3 +-
hw/net/vmware_utils.h |2 +-
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |5 +
1 file changed, 5 insertions(+)
diff --git a/exec.c b/exec.c
index eba889a..8fa63b7 100644
--- a/exec.c
+++ b/exec.c
@@ -1809,6 +1809,11 @@ static void tcg_commit(MemoryListener *listener)
CPU_FOREACH(cpu)
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
include/exec/memory.h |2 --
include/qemu/typedefs.h |1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 480dfbf..2d0b614 100644
--- a/include/exec/memory
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cputlb.c|7 ---
exec.c | 28
include/exec/exec-all.h |1 +
include/exec/softmmu_template.h |6 --
include/qom/cpu.h
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
cputlb.c|2 +-
exec.c |5 ++---
include/exec/exec-all.h |2 +-
include/exec/softmmu_template.h |5 +++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/exec.c b/exec.c
index c34f642..6d88931 100644
--- a/exec.c
+++ b/exec.c
@@ -878,6 +878,7 @@ static void register_subpage(AddressSpaceDispatch *d,
MemoryRegionSection *
From: "Edgar E. Iglesias"
Signed-off-by: Edgar E. Iglesias
---
exec.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/exec.c b/exec.c
index 6d88931..803bbde 100644
--- a/exec.c
+++ b/exec.c
@@ -782,7 +782,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
From: "Edgar E. Iglesias"
No functional change.
Signed-off-by: Edgar E. Iglesias
---
exec.c|3 ++-
include/exec/exec-all.h |2 +-
target-xtensa/op_helper.c |3 ++-
translate-all.c |4 ++--
4 files changed, 7 insertions(+), 5 deletions(-)
diff --
于 12/19/2013 02:03 AM, Andreas Färber 写道:
Am 05.11.2013 11:16, schrieb xiaoqiang zhao:
changes:
1. use type constant for kvm_ioapic and ioapic
2. convert 'init' to QOM's 'realize' for ioapic and kvm_ioapic
For QOM'ify, I move variable 'ioapic_no' from static to global.
Then we can drop the 'inst
From: "Edgar E. Iglesias"
Hi,
I'm looking at modeling systems where multiple CPUs co-exist with
different views of their attached buses/devs.
With this series I'm trying to take some steps towards having
an address-space per CPU. It's not complete but good enough for
making it possible to model
On Thu, Nov 28, 2013 at 05:43:54PM +, Peter Maydell wrote:
> On 28 November 2013 16:17, Peter Maydell wrote:
> > On 19 November 2013 06:18, Christoffer Dall
> > wrote:
> > So I think this is a correct change in the sense that
> > it's fixing the behaviour of this function. However
> > we see
On Thu, Nov 28, 2013 at 04:17:43PM +, Peter Maydell wrote:
> On 19 November 2013 06:18, Christoffer Dall
> wrote:
> > For some reason only edge-triggered or enabled level-triggered
> > interrupts would set the pending state of a raised IRQ. This is not in
> > compliance with the specs, which
Ok so read a bit further,
I was assuming MRC and MRRC were able to access the same register
subset but it turns out that the code is enforcing mutually
exclusivity of two sets via the ENCODE_CP_REG hash table. Sorry for
the noise.
Regards,
Peter
On Thu, Dec 19, 2013 at 3:17 PM, Peter Crosthwaite
Hi Peter,
I've been reviewing the ARM CP TCG handing code trying to get my head
around it, and I found this a little suspicious (translate.c):
6476 static int disas_coproc_insn(CPUARMState * env, DisasContext *s,
uint32_t insn)
6477 {
...
6502 is64 = (insn & (1 << 25)) == 0;
...
6552
On Wed, Dec 4, 2013 at 10:48 PM, Fedorov Sergey wrote:
>
> On 12/04/2013 03:13 PM, Peter Maydell wrote:
>>
>> On 4 December 2013 10:08, Fedorov Sergey wrote:
>>>
>>> On 12/03/2013 12:48 PM, Sergey Fedorov wrote:
This patch set implements a basic support of CPU core TrustZone feature.
>>
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov wrote:
> MVBAR register provides an exception vector base address for exceptions
> taking to CPU monitor mode.
>
> Signed-off-by: Sergey Fedorov
> ---
> target-arm/cpu.h|1 +
> target-arm/helper.c | 16 +++-
> 2 files changed,
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov wrote:
> Banked coprocessor registers are switched on two cases:
> 1) Entering or leaving CPU monitor mode with SCR.NS bit set;
> 2) Setting SCR.NS bit not from CPU monitor mode
>
> Coprocessor register banking is done similar to CPU core register
> b
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov wrote:
> Use c13_context field instead of c13_fcse for CONTEXTIDR register
> definition.
This a standalone (I.E. not TZ related) bug?
Regards,
peter
>
> Signed-off-by: Sergey Fedorov
> ---
> target-arm/helper.c |2 +-
> 1 file changed, 1 inse
On Wed, 2013-12-18 at 23:07 +0100, Alexander Graf wrote:
> On 18.12.2013, at 23:04, Benjamin Herrenschmidt
> wrote:
>
> > On Wed, 2013-12-18 at 22:24 +0100, Alexander Graf wrote:
> >> Then I don't understand why we break when we limit the data region to
> >> 4 bytes.
> >
> > This is old uninort
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov wrote:
>
> Signed-off-by: Sergey Fedorov
> ---
> target-arm/helper.c |3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index d4407cf..e406ec9 100644
> --- a/target-arm/helper.c
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov wrote:
> arm_is_secure() helper allows to determine CPU security state.
>
Helper in the target-foo context usually refers to a TCG->C code
helper fn, whereas you are using in a general sense. Just
s/helper/function.
> Signed-off-by: Sergey Fedorov
On Wed, Dec 4, 2013 at 10:35 PM, Peter Maydell wrote:
> On 4 December 2013 12:33, Fedorov Sergey wrote:
>>
>> On 12/04/2013 03:18 PM, Peter Maydell wrote:
>>>
>>> On 4 December 2013 10:58, Peter Crosthwaite
>>> wrote:
So what im proposing is just a slightly more general patch. Is it
>>
On Wed, Dec 4, 2013 at 7:55 PM, Fedorov Sergey wrote:
>
> On 12/03/2013 04:17 PM, Peter Crosthwaite wrote:
>>
>> On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov
>> wrote:
>>>
>>> From: Svetlana Fedoseeva
>>>
>>> Signed-off-by: Svetlana Fedoseeva
>>> Signed-off-by: Sergey Fedorov
>>> ---
>>> t
On Wed, Dec 4, 2013 at 8:52 PM, Peter Crosthwaite
wrote:
> On Wed, Dec 4, 2013 at 7:50 PM, Fedorov Sergey wrote:
>>
>> On 12/03/2013 04:15 PM, Peter Crosthwaite wrote:
>>>
>>> On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov
>>> wrote:
TTBCR has additional fields PD0 and PD1 when using S
On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov wrote:
> Define a new ARM CP register info list for TrustZone Security Extension
> feature. Register that list only for ARM cores with TrustZone support.
> SCR and VBAR are security extension registers. So move them into
> TrustZone feature register l
于 12/19/2013 10:28 AM, Chen Fan 写道:
On Wed, 2013-12-18 at 19:03 +0100, Andreas Färber wrote:
Am 05.11.2013 11:16, schrieb xiaoqiang zhao:
changes:
1. use type constant for kvm_ioapic and ioapic
2. convert 'init' to QOM's 'realize' for ioapic and kvm_ioapic
For QOM'ify, I move variable 'ioapic_n
This field is used to preallocate disk space for block device.
Signed-off-by: Hu Tao
---
block.c | 13 +
include/block/block.h | 1 +
include/block/block_int.h | 3 +++
3 files changed, 17 insertions(+)
diff --git a/block.c b/block.c
index 64e7d22..b901587 10
Signed-off-by: Hu Tao
---
block/raw-posix.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/block/raw-posix.c b/block/raw-posix.c
index 10c6b34..19181f2 100644
--- a/block/raw-posix.c
+++ b/block/raw-posix.c
@@ -1160,6 +1160,39 @@ static int64_t
raw_get_al
This patch adds a new option preallocation for raw format, and implements
full preallocation.
Signed-off-by: Hu Tao
---
block/raw-posix.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/block/raw-posix.c b/block/raw-posix.c
index 19181f2..e09e170 100644
--- a/block/ra
Signed-off-by: Hu Tao
---
block/qcow2.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/block/qcow2.c b/block/qcow2.c
index 32cb39f..487a595 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
@@ -2188,6 +2188,12 @@ static int qcow2_amend_options(BlockDriverState *bs,
return 0;
}
+s
On Wed, 2013-12-18 at 19:03 +0100, Andreas Färber wrote:
> Am 05.11.2013 11:16, schrieb xiaoqiang zhao:
> > changes:
> > 1. use type constant for kvm_ioapic and ioapic
> > 2. convert 'init' to QOM's 'realize' for ioapic and kvm_ioapic
> > For QOM'ify, I move variable 'ioapic_no' from static to glob
This adds a preallocation=full mode to qcow2 image creation, which
creates a non-sparse image file.
Signed-off-by: Hu Tao
---
block/qcow2.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/block/qcow2.c b/block/qcow2.c
index 487a595..3c41d4a 100644
--- a/
This patch prepares for the subsequent patches.
Signed-off-by: Hu Tao
---
block/qcow2.c | 6 +++---
include/block/block.h | 6 ++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/block/qcow2.c b/block/qcow2.c
index f29aa88..32cb39f 100644
--- a/block/qcow2.c
+++ b/block
This series implements full image preallocation to create a non-sparse image
file at creation time, both for raw and qcow2 format. The purpose is to avoid
performance deterioration of the guest cause by sparse image.
v3: - Fix comments to v2 by Fam.
- qcow2: first fallocate disk space, then
On Wed, Dec 18, 2013 at 11:48 PM, Alexander Graf wrote:
>
> On 11.11.2013, at 09:16, peter.crosthwa...@xilinx.com wrote:
>
>> From: Peter Crosthwaite
>>
>> There are a mix of usages of the qemu_fdt_* API calls, some which
>> wish to assert and abort QEMU on failure and some of which wish to do
>>
Il 18/12/2013 23:10, Laszlo Ersek ha scritto:
>
> So, if PEI must do something after S3 resume that is independent of any
> DXE drivers, it can simply do it. The boot script is only necessary when
> the S3 resume PEI actions (in step 6) need to depend on earlier actions
> during DXE (step 3).
In
On Thu, Dec 19, 2013 at 9:15 AM, Andreas Färber wrote:
> Am 17.12.2013 02:40, schrieb Peter Crosthwaite:
>> As per current QOM conventions.
>>
>> Signed-off-by: Peter Crosthwaite
>> ---
>>
>> hw/char/cadence_uart.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/hw/char/cadence_uar
Am 17.12.2013 02:40, schrieb Peter Crosthwaite:
> As per current QOM conventions.
>
> Signed-off-by: Peter Crosthwaite
> ---
>
> hw/char/cadence_uart.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> index f18db53..2f19a53 100644
> -
> Am 18.12.2013 um 23:11 schrieb Scott Wood :
>
>> On Wed, 2013-12-18 at 23:09 +0100, Alexander Graf wrote:
>>> On 18.12.2013, at 23:02, Scott Wood wrote:
>>>
On Mon, 2013-12-09 at 09:46 -0600, Tom Musta wrote:
This patch adds a flag for base instruction additions to Power ISA
2
On Wed, Dec 18, 2013 at 10:53:32PM +0100, Alexander Graf wrote:
>
> On 28.11.2013, at 07:35, Bharat Bhushan wrote:
>
> > This patch adds pci pin to irq_num routing callback
> > Without this patch we gets below warning
> >
> > "
> > PCI: Bug - unimplemented PCI INTx routing (e500-pcihost)
> >
On Wed, 18 Dec 2013 20:09:03 +0100
Andreas Färber wrote:
> Am 18.12.2013 18:00, schrieb Luiz Capitulino:
> > From: Paolo Bonzini
> >
> > Signed-off-by: Paolo Bonzini
> > Reviewed-By: Igor Mammedov
> > Signed-off-by: Luiz Capitulino
> > ---
> > qom/object.c | 9 +++--
> > 1 file changed,
On 12/18/13 23:10, Laszlo Ersek wrote:
> 1. SEC after cold boot
> 2. PEI after cold boot
> 2.5 DXE IPL PEIM loads DXE core
> 3. DXE after cold boot
> 4. BDS after cold boot
> 5. runtime (OSPM), normal entry
> 6. PEI after S3 resume
> 6.5 DXE IPL PEIM branches to S3 resume PEIM
> 7. runtime (OSPM),
On Wed, 2013-12-18 at 23:09 +0100, Alexander Graf wrote:
> On 18.12.2013, at 23:02, Scott Wood wrote:
>
> > On Mon, 2013-12-09 at 09:46 -0600, Tom Musta wrote:
> >> This patch adds a flag for base instruction additions to Power ISA
> >> 2.06B. The flag will be used to identify/select basic Book
On 12/18/13 17:34, Paolo Bonzini wrote:
>
>
> - Messaggio originale -
>> Da: "Michael S. Tsirkin"
>> A: "marcel a"
>> Cc: "Paolo Bonzini" , "Gal Hammer"
>> , seab...@seabios.org,
>> qemu-devel@nongnu.org
>> Inviato: Mercoledì, 18 dicembre 2013 17:33:06
>> Oggetto: Re: [Qemu-devel] [PAT
This patch adds the floating point addition and subtraction
instructions defined by V2.06 of the PowerPC ISA: xssubdp,
xvsubdp and xvsubsp.
V2: re-implemented helper macro and combined add and substract.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
target-ppc/fpu_helper.c | 51
On 18.12.2013, at 23:07, Alexander Graf wrote:
>
> On 18.12.2013, at 23:04, Benjamin Herrenschmidt
> wrote:
>
>> On Wed, 2013-12-18 at 22:24 +0100, Alexander Graf wrote:
>>> Then I don't understand why we break when we limit the data region to
>>> 4 bytes.
>>
>> This is old uninorth, not U3
On 18.12.2013, at 23:02, Scott Wood wrote:
> On Mon, 2013-12-09 at 09:46 -0600, Tom Musta wrote:
>> This patch adds a flag for base instruction additions to Power ISA
>> 2.06B. The flag will be used to identify/select basic Book I and
>> Book II instructions that were newly added in that revisi
On 18.12.2013, at 23:04, Benjamin Herrenschmidt
wrote:
> On Wed, 2013-12-18 at 22:24 +0100, Alexander Graf wrote:
>> Then I don't understand why we break when we limit the data region to
>> 4 bytes.
>
> This is old uninorth, not U3 HT right ? The latter is memory mapped.
Depends, we use the s
On Wed, 2013-12-18 at 22:24 +0100, Alexander Graf wrote:
> Then I don't understand why we break when we limit the data region to
> 4 bytes.
This is old uninorth, not U3 HT right ? The latter is memory mapped.
Ben.
From: "Michael R. Hines"
As far as we can tell, all known bugs have been fixed:
1. Parallel migrations are working
2. IPv6 migration is working
3. virt-test is working
I'm not comfortable sending the revised libvirt patch
until this is accepted or review suggestions are addressed,
(including pi
On Mon, 2013-12-09 at 09:46 -0600, Tom Musta wrote:
> This patch adds a flag for base instruction additions to Power ISA
> 2.06B. The flag will be used to identify/select basic Book I and
> Book II instructions that were newly added in that revision of the
> architecture. The flag will not be use
This patch adds the byte and halfword variants of the Store Conditional
instructions. A common macro is introduced and the existing implementations
of stwcx. and stdcx. are re-implemented using this macro.
V2: Re-implemented gen_conditional_store() and STCX macro per comments
from Richard.
Sign
On 12/18/13 15:19, Paolo Bonzini wrote:
> Il 11/12/2013 12:04, Gal Hammer ha scritto:
>> Michael,
>>
>> True, I haven't figure it out yet, but the current status is that recover
>> from sleep doesn't work.
>>
>> As far as I can tell it could be either:
>>
>> 1. piix4_reset shouldn't be call on res
On 28.11.2013, at 07:35, Bharat Bhushan wrote:
> This patch adds pci pin to irq_num routing callback
> Without this patch we gets below warning
>
> "
> PCI: Bug - unimplemented PCI INTx routing (e500-pcihost)
> qemu-system-ppc64: PCI: Bug - unimplemented PCI INTx routing (e500-pcihost)
> "
>
This patch adds the VSX floating point test for software square
root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp,
xvtsqrtdp, xvtsqrtsp.
V2: (a) using locally implemented ppc_float*_get_unbiased_exp
routines (b) eliminated dependency on float*_is_denormal().
Signed-off-by: Tom Mus
This patch adds the VSX floating point reciprocal estimate instructions
defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
target-ppc/fpu_helper.c | 35 +++
target-ppc/helper.h |3 +++
This patch adds the Divide Doubleword Extended Unsigned
instructions. This instruction requires dividing a 128-bit
value by a 64 bit value. Since 128 bit integer division is
not supported in TCG, a helper is used, providing a
repeated difference algorithm.
V2: Moved the 128-bit divide routine in
This patch addes the Signed and Unsigned Divide Word Extended
instructions which were introduced in Power ISA 2.06.
V2: Eliminating extraneous code in the overflow case per comments
from Richard Henderson. Fixed corner case bug in divweu (check
for (RA) >= (RB)).
Signed-off-by: Tom Musta
---
On 28.11.2013, at 07:35, Bharat Bhushan wrote:
> - Use PCI_NUM_PINS rather than hardcoding
> - use "pin" wherever possible
I assume you mean the PCI A/B/C/D pin with "pin".
>
> Signed-off-by: Bharat Bhushan
> ---
> hw/pci-host/ppce500.c | 14 +++---
> hw/ppc/e500.c | 12 ++
On 10.12.2013, at 09:32, Alexey Kardashevskiy wrote:
> On 12/03/2013 02:45 PM, Alexey Kardashevskiy wrote:
>> On 11/25/2013 02:14 PM, Alexey Kardashevskiy wrote:
>>> This fixes a bug in patch#1 and mistype in patch#2, details are in
>>> the commit messages.
>>>
>>> Alexey Kardashevsksy (1):
>>>
The QEMU emulation models for Power7 and Power8 are still missing some
of the base instructions that were introduced in Power ISA 2.06 and
even a few that were introduced prior to that.
This patch series gets these models caught up with respect to the
base 2.06 ISA. That is, the Book I and Book I
The help message uses $python and displays its value, so that macro
should be tested and set early.
With this modification, configure --help displays the correct value
(usually python -B) and no longer creates several *.pyc files.
Signed-off-by: Stefan Weil
---
There still remains a problem wit
This patch adds the VSX floating point square root instructions
defined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp.
V2: re-implemented the VSX_SQRT macro.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
target-ppc/fpu_helper.c | 44 +
This patch adds the Divide Doubleword Extended instructions.
The implementation builds on the unsigned helper provided in
the previous patch.
V2: Updated to use the host-utils 128 bit divide.
Signed-off-by: Tom Musta
---
include/qemu/host-utils.h | 14 ++
target-ppc/helper.h
On 18.12.2013, at 22:04, Benjamin Herrenschmidt
wrote:
> On Wed, 2013-12-18 at 13:34 +0100, Alexander Graf wrote:
>> Hrm. Are you 100% sure this correct? This UniNorth is a real headache.
>> The closest thing to a spec for it is the U4 spec which is generations
>> ahead:
>>
>> http://www.data
This patch adds a flag for base instruction additions to Power ISA
2.06B. The flag will be used to identify/select basic Book I and
Book II instructions that were newly added in that revision of the
architecture. The flag will not be used for VSX or Altivec.
Signed-off-by: Tom Musta
---
target
This patch adds the Bit Permute Doubleword (bpermd) instruction,
which was introduced in Power ISA 2.06 as part of the base 64-bit
architecture.
V2: Addressing stylistic comments from Richard Henderson.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
target-ppc/helper.h |1
In the new form most lines of the code now look like the final output:
there is no leading echo command and the lines are shorter.
The resulting output is nearly identical: the only difference is a blank
character which was deliberately removed:
@@ -8,7 +8,7 @@
--interp-prefix=PREFIX where t
On Wed, 2013-12-18 at 13:34 +0100, Alexander Graf wrote:
> Hrm. Are you 100% sure this correct? This UniNorth is a real headache.
> The closest thing to a spec for it is the U4 spec which is generations
> ahead:
>
> http://www.datasheetarchive.com/dl/Datasheets-SW3/DSASW0048084.pdf
>
> On that
This patch adds the VSX instructions that convert between floating
point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
target-ppc/fpu_helper.c | 46 ++
target-ppc/helper.h |4 +++
On 12/18/2013 09:51 PM, Eric Blake wrote:
On 12/17/2013 10:43 PM, mrhi...@linux.vnet.ibm.com wrote:
From: "Michael R. Hines"
As far as we can tell, all known bugs have been fixed:
1. Parallel migrations are working
2. IPv6 migration is working
3. virt-test is working
+++ b/qapi-schema.json
@
This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 31 +++
target-ppc/helper.h |1 +
target-ppc/translate.c | 14 ++
3 files change
This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06.
Signed-off-by: Tom Musta
---
target-ppc/fpu_helper.c | 56 ++
target-ppc/helper.h |2 +
target-ppc/translate.c | 17 ++
3 fi
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