On Jan 13, 2014, at 7:25 PM, Tomoki Sekiyama tomoki.sekiy...@hds.com wrote:
When a VSS requester such as vshadow.exe or diskshadow.exe requests to
delete snapshots, qemu-ga VSS provider's DeleteSnapshots() is also called
and returns E_NOTIMPL, that makes the deletion fail.
To avoid this
On Jan 13, 2014, at 7:25 PM, Tomoki Sekiyama tomoki.sekiy...@hds.com wrote:
When a VSS requester such as vshadow.exe or diskshadow.exe requests to
create disk snapshots, Windows may choose qemu-ga VSS provider if it is
only provider registered on the system. However, because it provides only
On Jan 13, 2014, at 7:25 PM, Tomoki Sekiyama tomoki.sekiy...@hds.com wrote:
OpenEvent and CreateEvent WinAPI return NULL when failed to open/create
events handles, instead of INVALID_HANDLE_VALUE (although their return
types are HANDLE).
This replaces INVALID_HANDLE_VALUE related to event
On 19 January 2014 01:39, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Sun, Jan 19, 2014 at 11:06 AM, Peter Maydell
peter.mayd...@linaro.org wrote:
So it doesn't
IMHO make much difference in terms of code complexity, and it
keeps the CPUState tidy (in particular, you don't end up
On 19 January 2014 01:46, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Sun, Jan 19, 2014 at 11:12 AM, Peter Maydell
peter.mayd...@linaro.org wrote:
IIRC ARMv4 and earlier didn't define the MIDR, but we don't
actually emulate any of those. In general, my intent with all these
Hi Anthony,
Michael said he had applied the typo patch, then I waited it for days
and didn't find it in master,
so I resend the same patch in my pull request queue.
It is my fault, sorry Michael.
And, Anthony, please applied this one, please.
On Sat, Dec 14, 2013 at 4:45 PM, Jia Liu
On Sun, 2014-01-19 at 22:03 +0800, Kai Huang wrote:
On Sat, Jan 18, 2014 at 3:25 AM, Alex Williamson
alex.william...@redhat.com wrote:
From: Alexey Kardashevskiy a...@ozlabs.ru
VFIO virtualizes MSIX table for the guest but not mapping the part of
a BAR which contains an MSIX table. Since
On Sat, Jan 18, 2014 at 3:25 AM, Alex Williamson
alex.william...@redhat.com wrote:
From: Alexey Kardashevskiy a...@ozlabs.ru
VFIO virtualizes MSIX table for the guest but not mapping the part of
a BAR which contains an MSIX table. Since vfio_mmap_bar() mmaps chunks
before and after the MSIX
On Sun, Jan 19, 2014 at 10:11 PM, Alex Williamson
alex.william...@redhat.com wrote:
On Sun, 2014-01-19 at 22:03 +0800, Kai Huang wrote:
On Sat, Jan 18, 2014 at 3:25 AM, Alex Williamson
alex.william...@redhat.com wrote:
From: Alexey Kardashevskiy a...@ozlabs.ru
VFIO virtualizes MSIX table
We have cache pools of temporaries that we can reuse later when they've
already been allocated before.
These cache pools differenciate between the target TCG variable type they
contain. So we have one pool for I32 and one pool for I64 variables.
On a 32bit system, we can't work with 64bit
On 30.12.2013 06:29, Hu Tao wrote:
n_start can be actually calculated from offset. The number of
sectors to be allocated(n_end - n_start) can be passed in in
num. By removing n_start and n_end, we can save two parameters.
The side effect is there is a bug in qcow2.c:preallocate() that
passes
On 30.12.2013 06:29, Hu Tao wrote:
When cluster size is big enough it can lead offset overflow
in qcow2_alloc_clusters_at(). This patch fixes it.
Signed-off-by: Hu Tao hu...@cn.fujitsu.com
---
block/qcow2-refcount.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git
On 30.12.2013 06:29, Hu Tao wrote:
In case of do preallocating metadata with a large cluster size,
qcow2_alloc_cluster_offset() can allocate nothing and returns
a NULL l2meta. This patch checks for it and link2 l2 with only
valid l2meta.
Signed-off-by: Hu Tao hu...@cn.fujitsu.com
---
While running qemu-system-ppc64 on my 32bit system I ran into cases where
TCG just stopped because it was running out of temporaries to allocate from.
Obviously this meant there were instructions not freeing their temporaries
properly, so I went ahead and implemented the same mechanism ARM uses
When QEMU gets compiled with --enable-debug-tcg we can check for temporary
leakage. Implement the necessary target code for this and fail emulation
when we hit a leakage.
This hopefully ensures that we don't get new leaks.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-ppc/translate.c |
We want to make sure that every instruction cleans up after itself and
clears every temporary it allocated.
While checking whether this is already the case, I came across a few
cases where it isn't. This patch fixes every translation I found that
doesn't free their allocated temporaries.
Support for pci-serial-2x and pci-serial-4x
was added to inf file.
Standard Windows driver mf.sys used to
split single function device into per-port nodes.
Changes since V2:
* Removed ntamd64 sections since the device
does not have operating system-specific
Support for pci-serial-2x and pci-serial-4x
was added to the inf file.
Standard Windows driver mf.sys used to
split single function device into per-port nodes.
Signed-off-by: Miki Mishael mmish...@redhat.com
Signed-off-by: Dmitry Fleytman dfley...@redhat.com
---
On 19 January 2014 16:32, Alexander Graf ag...@suse.de wrote:
When QEMU gets compiled with --enable-debug-tcg we can check for temporary
leakage. Implement the necessary target code for this and fail emulation
when we hit a leakage.
This hopefully ensures that we don't get new leaks.
On Sun, 2014-01-19 at 23:46 +0800, Kai Huang wrote:
On Sun, Jan 19, 2014 at 10:11 PM, Alex Williamson
alex.william...@redhat.com wrote:
On Sun, 2014-01-19 at 22:03 +0800, Kai Huang wrote:
On Sat, Jan 18, 2014 at 3:25 AM, Alex Williamson
alex.william...@redhat.com wrote:
From: Alexey
On 21 December 2013 06:09, Christoffer Dall christoffer.d...@linaro.org wrote:
The existing implementation of the pending behavior in gic_set_irq,
gic_acknowledge_irq, gic_complete_irq, and the distributor pending
set/clear registers does not follow the semantics of the GICv2.0 specs,
but may
On 19.01.2014, at 17:51, Peter Maydell peter.mayd...@linaro.org wrote:
On 19 January 2014 16:32, Alexander Graf ag...@suse.de wrote:
When QEMU gets compiled with --enable-debug-tcg we can check for temporary
leakage. Implement the necessary target code for this and fail emulation
when we hit
On 21 December 2013 06:09, Christoffer Dall christoffer.d...@linaro.org wrote:
The GICC_APRn registers are not currently supported by the ARM GIC v2.0
emulation. This patch adds the missing state.
Note that we also change the number of APRs to use a define GIC_NR_APRS
based on the maximum
On 21 December 2013 06:09, Christoffer Dall christoffer.d...@linaro.org wrote:
Right now the arm gic emulation doesn't keep track of the source of an
SGI (which apparently Linux guests don't use, or they're fine with
assuming CPU 0 always).
Add the necessary matrix on the GICState structure
On 19 January 2014 20:15, Alexander Graf ag...@suse.de wrote:
On 19.01.2014, at 17:51, Peter Maydell peter.mayd...@linaro.org wrote:
Exiting is pretty harsh; ARM just warns and continues.
Well, the check only ever happens when QEMU gets compiled
with --enable-debug-tcg, so I figured it's
On 19.01.2014, at 21:52, Peter Maydell peter.mayd...@linaro.org wrote:
On 19 January 2014 20:15, Alexander Graf ag...@suse.de wrote:
On 19.01.2014, at 17:51, Peter Maydell peter.mayd...@linaro.org wrote:
Exiting is pretty harsh; ARM just warns and continues.
Well, the check only ever
On 19 January 2014 20:55, Alexander Graf ag...@suse.de wrote:
On 19.01.2014, at 21:52, Peter Maydell peter.mayd...@linaro.org wrote:
Longer term I was wondering if we should define the concept
of a 'scope object' for TCG temporaries, so you create a scope
object and then we have versions of
On 19.01.2014, at 22:04, Peter Maydell peter.mayd...@linaro.org wrote:
On 19 January 2014 20:55, Alexander Graf ag...@suse.de wrote:
On 19.01.2014, at 21:52, Peter Maydell peter.mayd...@linaro.org wrote:
Longer term I was wondering if we should define the concept
of a 'scope object' for TCG
Am 10.01.2014 20:02, schrieb Stefan Weil:
Am 18.12.2013 19:14, schrieb Stefan Weil:
Am 07.12.2013 16:25, schrieb Stefan Weil:
GTK uses different hardware keycodes on Windows hosts, so some special
handling is needed to get the QEMU keycode.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
This patch adds support for the Fast Ethernet MAC found on Allwinner
SoCs, together with a basic emulation of Realtek RTL8201CP PHY.
Since there is no public documentation of the Allwinner controller, the
implementation is based on Linux kernel driver.
Signed-off-by: Beniamino Galvani
This patch series adds support for the EMAC Fast Ethernet controller
found on Allwinner SoCs to the Allwinner A10.
The main change in this version is the use of a single rx fifo instead
of multiple per-packet fifos. I added functions to manipulate the rx
fifo and, for consistency, also functions
Signed-off-by: Beniamino Galvani b.galv...@gmail.com
---
hw/arm/allwinner-a10.c | 16
hw/arm/cubieboard.c|7 +++
include/hw/arm/allwinner-a10.h |3 +++
3 files changed, 26 insertions(+)
diff --git a/hw/arm/allwinner-a10.c
We want to move to a model where firmware loads our kernel. To achieve
this we need to be able to tell firmware where the kernel lies.
Let's copy the mechanism we already use for -M pseries and expose the
kernel load address and size through the device tree.
Signed-off-by: Alexander Graf
Almost all platforms QEMU emulates have some sort of firmware they can load
to expose a guest environment that closely resembles the way it would look
like on real hardware.
This patch introduces such a firmware on our e500 platforms. U-boot is the
default firmware for most of these systems and
In addition to the L1 data cache configuration register L1CFG0 there is
also another one for the L1 instruction cache called L1CFG1.
Emulate that one with the same values as the data one.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-ppc/cpu.h| 1 +
The dcbtls instruction is able to lock data inside the L1 cache.
Unfortunately we don't emulate any caches, so we have to tell the guest
that its locking attempt failed.
However, by implementing the instruction we at least don't give the
guest a program exception which it definitely does not
The GUTS device is used by system software to find out about hardware
details of the current system.
We only emulate the bare minimum to be able to reboot a guest which is
not sufficient to make u-boot happy.
Add a few more registers to our portfolio with dummy values.
Signed-off-by: Alexander
There are 2 L1 cache control registers - one for data (L1CSR0) and
one for instructions (L1CSR1).
Emulate both of them well enough to give the guest the illusion that
it could actually do anything about its caches.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-ppc/cpu.h| 12
The HDBCR0 register is available for hardware debuggers which we don't
emulate.
However, we can treat it as a generic storage register that doesn't
have any effect, making guests happy.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-ppc/cpu.h| 1 +
Our pre-e500mc e500 CPU types didn't get instanciated with SVR information,
even though those systems do support the SVR register.
Spawn them with the SVR tag so that they don't get confused when someone tries
to read SPR_SVR.
Signed-off-by: Alexander Graf ag...@suse.de
---
We're missing SPR definitions for GIVORs. Add them to the list of SPRs.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-ppc/cpu.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 51bcd4a..70708d4 100644
--- a/target-ppc/cpu.h
+++
Today we don't run any firmware on our e500 platform. You're either running
a Linux kernel directly through -kernel or you don't boot the VM at all.
This is bad for multiple reasons. The normal firmware on e500 based systems
is u-boot. Some OSes (IIRC FreeBSD) rely on u-boot for their 2nd stage
This series converts cpu-midr (the MIDR register) to a property.
This allows it to be set after init which is useful for specific
boards (such as Zynq). The change has been done in such a way that
it doesn't break compatibility with boards that don't need a
custom MIDR.
V3: Removed the
This patch uses the fact that the midr variable is now a property
This patch sets the midr variable to the boards custom midr
Signed-off-by: Alistair Francis alistair.fran...@xilinx.com
---
hw/arm/xilinx_zynq.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git
Convert the MIDR register to a property. This allows boards to later set
a custom MIDR value. This has been done in such a way to maintain
compatibility with all existing CPUs and boards
Signed-off-by: Alistair Francis alistair.fran...@xilinx.com
---
I originally added the properties to the
On Sun, Jan 19, 2014 at 9:21 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 19 January 2014 01:46, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
On Sun, Jan 19, 2014 at 11:12 AM, Peter Maydell
peter.mayd...@linaro.org wrote:
IIRC ARMv4 and earlier didn't define the MIDR, but we
On 19 January 2014 23:44, Alexander Graf ag...@suse.de wrote:
This adds a special build of u-boot tailored for the e500 platforms we
emulate. It is based on patches that are currently in the review process,
so there's no hash commit to refer to yet.
This binary is provided purely for
This patch implements the ARM PMCCNTR register including
the disable and reset components of the PMCR register.
Signed-off-by: Alistair Francis alistair.fran...@xilinx.com
---
This patch assumes that non-invasive debugging is not permitted
when determing if the counter is disabled
V2:
I have made those changes you both mentioned above and submitted v2 of
my series. There is now only one extra variable in the CPUARMState
struct.
On Sun, Jan 19, 2014 at 9:20 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 19 January 2014 01:39, Peter Crosthwaite
On 01/17/2014 06:02 PM, Daniel P. Berrange wrote:
On Wed, Jan 08, 2014 at 05:12:51PM +0800, Lei Li wrote:
Signed-off-by: Lei Li li...@linux.vnet.ibm.com
---
include/qemu/fd-exchange.h | 25 +++
util/Makefile.objs |1 +
util/qemu-fd-exchange.c| 97
Stefan,
On Fri, Jan 17, 2014 at 04:48:16PM +0800, Stefan Hajnoczi wrote:
On Fri, Dec 27, 2013 at 11:05:54AM +0800, Hu Tao wrote:
This approach seems okay but the calculation isn't quite right yet.
On Windows an error would be raised since we don't have preallocate=full
support. That's
On Fri, Jan 17, 2014 at 04:25:14PM +0800, Stefan Hajnoczi wrote:
On Fri, Dec 27, 2013 at 11:05:53AM +0800, Hu Tao wrote:
This patch adds a new option preallocation for raw format, and implements
full preallocation.
Signed-off-by: Hu Tao hu...@cn.fujitsu.com
---
block/raw-posix.c |
On Fri, Jan 17, 2014 at 04:56:42PM +0800, Stefan Hajnoczi wrote:
On Fri, Dec 27, 2013 at 11:05:53AM +0800, Hu Tao wrote:
diff --git a/block/raw-posix.c b/block/raw-posix.c
index 6f6b8c1..a722d27 100644
--- a/block/raw-posix.c
+++ b/block/raw-posix.c
@@ -1160,17 +1160,52 @@ static
On Fri, 01/17 17:25, Stefan Hajnoczi wrote:
On Mon, Jan 13, 2014 at 06:39:39PM +0800, Fam Zheng wrote:
This implements incremental backup.
A few new QMP commands related to dirty bitmap are added:
dirty-bitmap-add *
dirty-bitmap-disable *
dirty-bitmap-remove
On 01/17/2014 07:51 AM, Michael Roth wrote:
Quoting Alexey Kardashevskiy (2013-12-15 22:54:42)
On 12/16/2013 01:59 PM, Alexey Kardashevskiy wrote:
On 12/06/2013 09:32 AM, Michael Roth wrote:
From: Nathan Fontenot nf...@linux.vnet.ibm.com
This add entries to the root OF node to advertise our
On Sun, Jan 19, 2014 at 05:18:05PM +0100, Max Reitz wrote:
On 30.12.2013 06:29, Hu Tao wrote:
In case of do preallocating metadata with a large cluster size,
qcow2_alloc_cluster_offset() can allocate nothing and returns
a NULL l2meta. This patch checks for it and link2 l2 with only
valid
This series fixes several bugs when doing preallocation with a cluster_size
larger than the default value.
Hu Tao (3):
qcow2: remove n_start and n_end of qcow2_alloc_cluster_offset()
qcow2: fix offset overflow in qcow2_alloc_clusters_at()
qcow2: check for NULL l2meta
block/qcow2-cluster.c
n_start can be actually calculated from offset. The number of
sectors to be allocated(n_end - n_start) can be passed in in
num. By removing n_start and n_end, we can save two parameters.
The side effect is there is a bug in qcow2.c:preallocate() that
passes incorrect n_start to
When cluster size is big enough it can lead offset overflow
in qcow2_alloc_clusters_at(). This patch fixes it.
The allocation each time is stopped at L2 table boundary
(see handle_alloc()), so the possible maximum bytes could be
2^(cluster_bits - 3 + cluster_bits)
so int is safe for
In case of do preallocating metadata with a large cluster size,
qcow2_alloc_cluster_offset() can allocate nothing and returns
a NULL l2meta. This patch checks for it and link2 l2 with only
valid l2meta.
Replace 9 and 512 with BDRV_SECTOR_BITS, BDRV_SECTOR_SIZE
respectively while at the function.
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