On 2014/6/2 20:16, Chen Gang wrote:
Call g_free() after cache_fini() in migration_end(), but do not call
g_free() after call cache_fini() in xbzrle_cache_resize() which will
cause memory leak.
cache_init() and cache_fini() are pair, so need let cache_fini() call
g_free(cache) to match
On 2014/6/2 20:35, Chen Gang wrote:
'encoded_buf' and 'current_buf' are lock protected during using in
save_xbzrle_page() in ram_save_page(), and during freeing in
migration_end().
So recommend to let them lock protected during starting, just like we
have done to 'cache'.
Il 02/06/2014 04:40, Peter Crosthwaite ha scritto:
{
MemoryRegion *mr = MEMORY_REGION(obj);
+gchar *container_link_type = g_strdup_printf(link%s,
+ TYPE_MEMORY_REGION);
Since TYPE_MEMORY_REGION is a literal string constant, this can
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
ui/gtk.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/ui/gtk.c b/ui/gtk.c
index 544126c..b02fcd6 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -1005,12 +1005,14 @@ static void gd_menu_switch_vc(GtkMenuItem *item, void
*opaque)
static void
Make configure detect gtk x11 backend and link libX11 then. Make
gtk backend specific code properly #ifdef'ed on the GTK_WINDOWING_*
backends at runtime). Our gtk ui code should build and run fine on
any platform now.
This also fixes the linker failute due to the new XkbGetKeyboard call
added
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
ui/gtk.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/ui/gtk.c b/ui/gtk.c
index b908936..01d48cc 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -877,22 +877,18 @@ static gboolean gd_scroll_event(GtkWidget
Hi,
Current gtk patch queue. A bunch of cleanups and fixes.
Most notable change is patch #5 which winds up qemu text
terminal emulation in gtk, so '-chardev vc' works even
when building without vte (i.e. on windows).
Gerd Hoffmann (5):
gtk: factor out keycode mapping
gtk: cleanup backend
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
ui/gtk.c | 100 +++
1 file changed, 36 insertions(+), 64 deletions(-)
diff --git a/ui/gtk.c b/ui/gtk.c
index d201190..544126c 100644
--- a/ui/gtk.c
+++ b/ui/gtk.c
@@ -1162,28 +1162,39
This way gtk has text terminal consoles even when building without vte.
Most notably you'll get a monitor tab on windows now.
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
ui/gtk.c | 109 ++-
1 file changed, 73 insertions(+), 36
On Mon, Jun 02, 2014 at 12:17:48PM -0400, Gabriel L. Somlo wrote:
I was looking over my submission, and have one remaining question:
On Mon, Jun 02, 2014 at 09:33:27AM -0400, Gabriel L. Somlo wrote:
Allow selection of different card models from the qemu
command line, to better accomodate a
On Mon, Jun 02, 2014 at 09:33:26AM -0400, Gabriel L. Somlo wrote:
Allow selection of different card models from the qemu
command line, to better accomodate a wider range of guests.
New in v4:
- s/E1000Info_st/E1000Info/
- s/E1000DeviceClass/E1000BaseClass/
- keeping removal
Hi all
Anybody got some infos about gnemul? I've googled the internet, just some
pages about old and out of date versions about gnemul, and they are built
for ARM32, and I need gnemul for AARCH64, does anybody know how to build it?
Thanks
Chaos
The Monday 02 Jun 2014 à 22:15:21 (+0200), Max Reitz wrote :
The exit code 63 (check not supported by image format) was not even
documented in the comment above the check command in the source code;
add it, as it does indeed seem useful.
Also, document all of check's exit codes in the
Il 30/05/2014 10:59, Tiejun Chen ha scritto:
+static int create_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
+{
+struct PCIDevice *dev;
+
+char rid;
+
+dev = pci_create(bus, PCI_DEVFN(0x1f, 0), intel-pch-isa-bridge);
This is really a huge hack. You're going to have two ISA
Hi,
This series adds virtio input support to qemu. virtio
input basically sends linux evdev events over virtio.
Patch #1 is just the pci id. Patch #2 adds the core code
as abstract qom class. Patch #3 adds emulated devices on
top of that, and patch #4 adds evdev passthrough.
The
Using 0x1012 because virtio id is 18 (0x12).
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
docs/specs/pci-ids.txt | 1 +
include/hw/pci/pci.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/specs/pci-ids.txt b/docs/specs/pci-ids.txt
index 3c65e1a..3b0a448 100644
---
This allows to assign host input devices to the guest:
qemu -device virto-input-host-pci,evdev=/dev/input/eventnr
The guest gets exclusive access to the input device, so be careful
with assigning the keyboard if you have only one connected to your
machine.
Signed-off-by: Gerd Hoffmann
This patch adds the virtio-input-hid base class and
virtio-{keyboard,mouse,tablet} subclasses building on the base class.
They are hooked up to the qemu input core and deliver input events
to the guest like all other hid devices (ps/2 kbd, usb tablet, ...).
Using them is as simple as adding
On Tue, Jun 3, 2014 at 5:51 PM, Paolo Bonzini pbonz...@redhat.com wrote:
Il 02/06/2014 04:40, Peter Crosthwaite ha scritto:
{
MemoryRegion *mr = MEMORY_REGION(obj);
+gchar *container_link_type = g_strdup_printf(link%s,
+
This patch adds virtio-input support to qemu. It brings a abstract
base class providing core support, other classes can build on it to
actually implement input devices.
virtio-input basically sends linux input layer events (evdev) over
virtio.
Signed-off-by: Gerd Hoffmann kra...@redhat.com
---
On Mon, 2014-06-02 at 12:58 -0400, Konrad Rzeszutek Wilk wrote:
Yes, which most likely involves preseeding the guest RAM with the files
at a discoverable location. Icky.
Or some form of FTP over XenBus :-)
I'll file that one in the round filing cabinet next to my desk ;-)
Ian
On Mon, 2014-06-02 at 21:35 -0600, Chun Yan Liu wrote:
Now I wonder how does it handle device? (A backend file or partition is also
a place
on host.) Stubdom uses qemu-xen-traditional, maybe there is some special
handling?
Will have a look.
The stubdom VM has access to PV Xen devices via
Am 02.06.2014 um 22:15 hat Max Reitz geschrieben:
The exit code 63 (check not supported by image format) was not even
documented in the comment above the check command in the source code;
add it, as it does indeed seem useful.
Also, document all of check's exit codes in the manpage.
On Mon, 2014-06-02 at 22:49 -0600, Chun Yan Liu wrote:
On 6/2/2014 at 11:24 PM, in message
1401722652.30097.9.ca...@kazak.uk.xensource.com, Ian Campbell
ian.campb...@citrix.com wrote:
On Thu, 2014-05-29 at 11:23 +0800, Chunyan Liu wrote:
[support xen HVM direct kernel boot]
Can you give this patch a try? Should read the guest TSC values after
stopping the VM.
Yes, this patch fixes that.
Thanks,
--
mg
Am 30.05.2014 um 13:18 hat Benoît Canet geschrieben:
On read operations when this parameter is set and some replicas are corrupted
while quorum can be reached quorum will proceed to rewrite the correct version
of the data to fix the corrupted replicas.
This will shine with SSD where the FTL
On Mon, Jun 02, 2014 at 09:32:55PM +0200, Stefan Priebe wrote:
Am 02.06.2014 15:40, schrieb Stefan Hajnoczi:
On Fri, May 30, 2014 at 04:10:39PM +0200, Stefan Priebe wrote:
new trace:
(gdb) bt
#0 0x7f69e421c43f in event_notifier_set (e=0x124) at
util/event_notifier-posix.c:97
#1
On 6/2/2014 at 11:14 PM, in message
alpine.deb.2.02.1406021610070.4...@kaball.uk.xensource.com, Stefano
Stabellini stefano.stabell...@eu.citrix.com wrote:
On Fri, 30 May 2014, Konrad Rzeszutek Wilk wrote:
On Thu, May 29, 2014 at 11:23:22AM +0800, Chunyan Liu wrote:
Following previous
On 6/3/2014 at 05:06 PM, in message
1401786392.8841.44.ca...@kazak.uk.xensource.com, Ian Campbell
ian.campb...@citrix.com wrote:
On Mon, 2014-06-02 at 22:49 -0600, Chun Yan Liu wrote:
On 6/2/2014 at 11:24 PM, in message
1401722652.30097.9.ca...@kazak.uk.xensource.com, Ian Campbell
On Mon, 2 Jun 2014, Peter Crosthwaite wrote:
From: Andreas Färber afaer...@suse.de
Replace qemu_allocate_irqs(foo, bar, 1)[0]
with qemu_allocate_irq(foo, bar, 0).
You missed one occurrence in hw/sh4/sh7750.c in function sh7750_irl.
--
Kirill
qemu_bh_schedule() is supposed to be thread-safe at least the first time
it is called. Unfortunately this is not quite true:
bh-scheduled = 1;
aio_notify(bh-ctx);
Since another thread may run the BH callback once it has been scheduled,
there is a race condition if the callback frees the BH
Il 02/06/2014 19:28, Alex Williamson ha scritto:
The latest Nvidia driver (337.88) specifically checks for KVM as the
hypervisor and reports Code 43 for the driver in a Windows guest when
found. Removing or changing the KVM signature is sufficient for the
driver to load and work. This patch
On 6/3/2014 at 05:04 PM, in message
1401786258.8841.42.ca...@kazak.uk.xensource.com, Ian Campbell
ian.campb...@citrix.com wrote:
On Mon, 2014-06-02 at 21:35 -0600, Chun Yan Liu wrote:
Now I wonder how does it handle device? (A backend file or partition is
also a place
on host.)
This moves PIR/PURR/SPURR SPRs to helpers. Later these helpers will be
called from generalized init_proc_book3s_64().
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
target-ppc/translate_init.c | 40 ++--
1 file changed, 26 insertions(+), 14
Previously LPCR was registered for the 970 class which was wrong as
it does not have LPCR. Instead, HID4 is used which this patch registers.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
target-ppc/cpu.h| 1 +
target-ppc/translate_init.c | 11 +++
2 files changed,
This splits one init_proc_970() into a set of small helpers. Later
init_proc_970() will be generalized and will call different set of helpers
depending on the current CPU class.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
target-ppc/translate_init.c | 97
The differences between classes were:
1. SLB size, was 32 for 970 and 64 for others, should be 64 for all;
2. check_pow() callback, HID0 format is the same so should be the same
0x01C0 which means deep nap, doze and nap bits set;
3. LPCR - 970 does not have it but 970MP had one (by mistake).
Started as POWER7/8 SPRs patchset, this became a rework of book3s/970 CPU
classes initialization.
The aim is to boot little endian guests in TCG mode with -cpu POWER8
(ironically, POWER8 emulation still fails, debugging it now but most of the set
is still valid).
Individual patches have change
This replaces gen_spr_7xx() call (which registers 32bit SPRs) with
gen_spr_book3s_pmu() call.
This removes SPR_7XX_PMC5/6 as they are for 32bit and gen_spr_book3s_pmu()
already registers correct PMC5/6 SPRs.
This removes explicit MMCRA registration as gen_spr_book3s_pmu() does it
anyway.
At the moment every POWER CPU family has its own init_proc_POWERX function.
E500 already has common init function so we try to do the same thing.
This introduces BOOK3S_CPU_TYPE enum with 2 values - 970 and POWER5+.
This introduces generalized init_proc_book3s_64() which accepts a CPU type
as a
This makes use of generic gen_spr_book3s_lpar() which registers LPCR SPR.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
target-ppc/translate_init.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index
On Tue, 2014-06-03 at 03:16 -0600, Chun Yan Liu wrote:
On 6/2/2014 at 11:14 PM, in message
alpine.deb.2.02.1406021610070.4...@kaball.uk.xensource.com, Stefano
Stabellini stefano.stabell...@eu.citrix.com wrote:
On Fri, 30 May 2014, Konrad Rzeszutek Wilk wrote:
On Thu, May 29, 2014 at
This adds migration support for registers saved before Transactional
Memory (TM) transaction started.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
target-ppc/cpu.h | 14 ++
target-ppc/kvm.c | 38 ++
target-ppc/machine.c | 35
As defined in Linux kernel, PMC*, SIAR, MMCR0/1 have different numbers
for 32 and 64 bit POWERPC. We are going to support 64bit versions too so
let's rename 32bit ones to avoid confusion.
This is a mechanical patch so it does not fix obvious mistake with these
registers in POWER7 yet, this will
This hooks SPR with theit KVM set_one_reg counterparts which enables
their migration.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
target-ppc/translate_init.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-ppc/translate_init.c
This adds TM (Transactional Memory) SPRs.
This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
Since this is not the only register like that and their numbers go
consequently, it makes sense to generalize the
On 02/06/14 20:16, Aurelien Jarno wrote:
-case OPC_DADDI:
+case OPC_DADDI: /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
+if (ctx-insn_flags ISA_MIPS32R6) {
+/* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
+gen_compute_compact_branch(ctx, op, rs, rt, imm 2);
+
This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
This defines AIL flags for LPCR special register.
This changes @excp_prefix according to the mode, takes effect in TCG.
This turns support of a new capability PPC2_ISA207S flag for
Il 02/06/2014 18:17, Peter Maydell ha scritto:
Um. This feels like we're wrongly overloading this flag for
more than one thing. Is the user-mode binary BE8? is
definitely not a property of the CPU, so it shouldn't be
a CPU state flag. (Conversely, is the iside endianness the
opposite way round
This adds POWER8 specific PMU MMCR2/MMCRS SPRs.
This adds a spr_write_ureg helper for changing a hypv-privileged SPR when
it is accessed via its user-privileged mirror. A spr_read_ureg() is
already there. Since the new helper is only used by book3s CPUs, it is
limited to TARGET_PPC64 to make gcc
This moves H_SET_MODE_RESOURCE_LE handler to a separate function
as there are other resources coming and this is going to become ugly.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Changes:
v2:
* s/becode/become/ in commit log
---
hw/ppc/spapr_hcall.c | 67
On Mon, 2 Jun 2014, Gerd Hoffmann wrote:
Call get_alloc_displaystate() for proper initialization
instead of allocating with g_new().
Signed-off-by: Gerd Hoffmann kra...@redhat.com
Tested-by: BALATON Zoltan bala...@eik.bme.hu
---
ui/console.c | 5 +
1 file changed, 1 insertion(+), 4
On 3 June 2014 04:52, Alexey Kardashevskiy a...@ozlabs.ru wrote:
Is there anything I can do to help with this? Chase someone down? :)
Confirming that your lawyers are happy with the approach
Anthony proposed to take to fixing this would probably
be useful :-)
-- PMM
This adds an FSCR (Facility Status and Control Register) SPR. This defines
names for FSCR bits.
This defines new exception type - POWERPC_EXCP_FU - facility unavailable (FU).
This registers an interrupt vector for it at 0xF60 as PowerISA defines.
This adds a TCG helper_fscr_facility_check()
On 3 June 2014 10:23, Paolo Bonzini pbonz...@redhat.com wrote:
Il 02/06/2014 18:17, Peter Maydell ha scritto:
Um. This feels like we're wrongly overloading this flag for
more than one thing. Is the user-mode binary BE8? is
definitely not a property of the CPU, so it shouldn't be
a CPU state
On 06/03/2014 11:14 AM, Tristan Gingold wrote:
Remove the code that reduce the result to float32 as the frsqrte
instruction is defined to return a double-precision estimate of
the reciprocal square root.
Although reducing the fractional part is harmless (as the estimation
must have at least 12
This adds DABRX SPR.
As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not
have them (as it implements more powerful facility instead), this limits
DABR/DABRX registration by POWER7 (inclusive).
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Alex Bennée writes:
This converts all users of pstate_write to use the common state
save/restore functionality.
Oops, now I'll clean that up. I need to decide if it worth merge the
xpsr_ stuff anyway?
There is also some commented out code in the main save_state_to_spsr()
function which I
On 6/3/2014 at 05:31 PM, in message
1401787863.8841.55.ca...@kazak.uk.xensource.com, Ian Campbell
ian.campb...@citrix.com wrote:
On Tue, 2014-06-03 at 03:16 -0600, Chun Yan Liu wrote:
On 6/2/2014 at 11:14 PM, in message
alpine.deb.2.02.1406021610070.4...@kaball.uk.xensource.com,
Edgar E. Iglesias writes:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
No functional change.
Prepares for future additions of the EL2 and 3 versions of this reg.
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
target-arm/cpu.c| 2 +-
target-arm/cpu.h
Edgar E. Iglesias writes:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
target-arm/cpu.h| 2 +-
target-arm/helper.c | 6 ++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h
Edgar E. Iglesias writes:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
target-arm/cpu.h| 35 +++
target-arm/helper.c | 27 +++
2 files changed, 62 insertions(+)
Edgar E. Iglesias writes:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
target-arm/cpu.h| 15 +++
target-arm/helper.c | 20
2 files changed, 35 insertions(+)
diff --git
Edgar E. Iglesias writes:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
cpu-exec.c | 5 ++---
target-arm/cpu.h | 16
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/cpu-exec.c
This replaces VRSAVE registration and vscr_init() call with
gen_spr_book3s_altivec() which is generic and does the same thing if
insns_flags has PPC_ALTIVEC bit set (which POWER7/8 have set).
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Here is the function for the reference:
static
Edgar E. Iglesias writes:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Not all exception types update both FAR and ESR.
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
target-arm/helper-a64.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
This moves TAR SPR to a helper. Later this helper will be
called from generalized init_proc_book3s_64().
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
target-ppc/translate_init.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git
This moves SCFAR/DSCR/CTRL/PPR/PCR PRs to helpers. Later these helpers
will be called from generalized init_proc_book3s_64().
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
target-ppc/translate_init.c | 70 ++---
1 file changed, 40 insertions(+),
This makes user-privileged read/write fail if TAR facility is not enabled
in FSCR.
Since this is the very first check for enabled in FSCR facility,
this also adds gen_fscr_facility_check() for using in spr_write_tar()/
spr_read_tar().
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Edgar E. Iglesias writes:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
target-arm/cpu.h | 7 ++-
target-arm/helper-a64.c| 1 +
target-arm/helper.c| 39 +++
POWER8 supports Event-Based Branch Facility (EBB). It is controlled via
set of SPRs access to which should generate an Facility Unavailable
interrupt if the facilities are not enabled in FSCR for problem state.
This adds EBB SPRs.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Edgar E. Iglesias writes:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
target-arm/cpu.h| 10 ++
target-arm/helper.c | 16
2 files changed, 26 insertions(+)
diff --git a/target-arm/cpu.h
On Sun, Jun 01, 2014 at 11:30:02PM +0700, Jun Koi wrote:
(1) do you think this VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL is the
reason why ESXi falls back to binary translation?
It might be, its been a while since I got ESXi to use VMX on KVM. Take
a look at the VMware log file for the L2, it
This stops using 7xx common SPRs init function and adds separate set
of helpers for 970.
This does not copy ICTC SPR as neither 970 manual nor PowerISA mention it.
This defines 970/book3s PMU SPRs constants as they differs from the ones
used for 7XX.
This creates 2 helpers for PMU SPRs, one for
From: Gonglei arei.gong...@huawei.com
add support for usb host adapter hotplug, as the same
as other pci devices.
changes since v1:
* rework usb_bus_release function suggested by Gerd.
* add more completely resource cleanup for every usb host adapter.
* fix memory leak.
Gonglei (9):
usb:
From: Gonglei arei.gong...@huawei.com
since hotunplug the ehci host adapter, we should
delete vm_change_state_handler also, so the
VMChangeStateEntry should be saved in EHCIState.
Signed-off-by: Gonglei arei.gong...@huawei.com
---
hw/usb/hcd-ehci.c | 2 +-
hw/usb/hcd-ehci.h | 1 +
2 files
From: Gonglei arei.gong...@huawei.com
As for usb-ehci-pci.c can call the function to
free ehci queue.
Signed-off-by: Gonglei arei.gong...@huawei.com
---
hw/usb/hcd-ehci.c | 2 +-
hw/usb/hcd-ehci.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/usb/hcd-ehci.c
From: Gonglei arei.gong...@huawei.com
add global variables releasing logic when the usb buses
were removed or hot-unpluged.
Signed-off-by: Gonglei arei.gong...@huawei.com
---
hw/usb/bus.c | 7 +++
include/hw/usb.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/usb/bus.c
On 2 June 2014 15:41, Gerd Hoffmann kra...@redhat.com wrote:
Hi,
Featuring new test cases for uhci+ehci. Also misc fixes,
mostly related to xhci emulation and usb3 support.
please pull,
Gerd
The following changes since commit 9bb931802e6ab5ab6947e3cb9cea934fc0724274:
Revert
Il 03/06/2014 11:21, Stefan Hajnoczi ha scritto:
qemu_bh_schedule() is supposed to be thread-safe at least the first time
it is called. Unfortunately this is not quite true:
bh-scheduled = 1;
aio_notify(bh-ctx);
Since another thread may run the BH callback once it has been scheduled,
Il 03/06/2014 11:54, Peter Maydell ha scritto:
In user emulation, things are more complicated for BE32,
because we're sort of emulating the word-invariant
bigendian using byte-invariant big-endian (this is
safe because there's no way for a userspace program
to get at anything that would let
Since we started adding POWER prefix to 64bit PMU SPRs, let's finish
the transition and fix MMCRA and define a hypv version of it.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
target-ppc/cpu.h| 3 ++-
target-ppc/translate_init.c | 2 +-
2 files changed, 3 insertions(+), 2
Il 03/06/2014 07:16, Marcelo Tosatti ha scritto:
On Mon, Jun 02, 2014 at 10:31:44PM +0200, Marcin Gibuła wrote:
+cpu_physical_memory_read(kvmclock_struct_pa, time, sizeof(time));
+
+delta = migration_tsc - time.tsc_timestamp;
Hi,
when I was testing live storage migration with libvirt
On 23 May 2014 03:30, Rob Herring robherri...@gmail.com wrote:
From: Rob Herring rob.herr...@linaro.org
Add support for handling PSCI calls in system emulation. Both version
0.1 and 0.2 of the PSCI spec are supported. Platforms can enable support
by setting psci-method QOM property on the
From: Gonglei arei.gong...@huawei.com
clean up xhci resource when xhci pci device exit.
Signed-off-by: Gonglei arei.gong...@huawei.com
---
hw/usb/hcd-xhci.c | 46 ++
1 file changed, 46 insertions(+)
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
From: Gonglei arei.gong...@huawei.com
usb host controller should be able to support hotplug/unplug,
as the same as the other pci devices, which not enable
multifunction capability.
BTW, the qemu have not the capability to support
hotplug mulitfuncition pci devices at present.
Signed-off-by:
On Tue, 3 Jun 2014, Paolo Bonzini wrote:
Il 30/05/2014 10:59, Tiejun Chen ha scritto:
+static int create_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
+{
+struct PCIDevice *dev;
+
+char rid;
+
+dev = pci_create(bus, PCI_DEVFN(0x1f, 0), intel-pch-isa-bridge);
On Tue, 3 Jun 2014, Ian Campbell wrote:
On Tue, 2014-06-03 at 03:16 -0600, Chun Yan Liu wrote:
On 6/2/2014 at 11:14 PM, in message
alpine.deb.2.02.1406021610070.4...@kaball.uk.xensource.com, Stefano
Stabellini stefano.stabell...@eu.citrix.com wrote:
On Fri, 30 May 2014, Konrad
From: Gonglei arei.gong...@huawei.com
clean up ohci resource when ohci pci device exit
Signed-off-by: Gonglei arei.gong...@huawei.com
---
hw/usb/hcd-ohci.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index dc1adbf..b513a13
Il 31/05/2014 23:39, Hani Benhabiles ha scritto:
This forces finishing data sending to client before closing the socket like in
exports listing or replying with NBD_REP_ERR_UNSUP cases.
Signed-off-by: Hani Benhabiles h...@linux.com
---
blockdev-nbd.c | 1 +
qemu-nbd.c | 1 +
2 files
This extends init_proc_book3s_64 to support POWER7 and POWER8.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Changes:
v4:
* added g_assert_not_reached() to default path to catch errors earlier
---
target-ppc/translate_init.c | 100 +++-
1 file
Il 31/05/2014 23:39, Hani Benhabiles ha scritto:
This is added by handling the NBD_OPT_LIST and NBD_OPT_ABORT options.
NBD_REP_ERR_UNSUP is also sent for unknown NBD option values.
Signed-off-by: Hani Benhabiles h...@linux.com
---
include/block/nbd.h | 5 ++
nbd.c | 197
On 06/03/2014 07:45 PM, Peter Maydell wrote:
On 3 June 2014 04:52, Alexey Kardashevskiy a...@ozlabs.ru wrote:
Is there anything I can do to help with this? Chase someone down? :)
Confirming that your lawyers are happy with the approach
Anthony proposed to take to fixing this would probably
On Mon, Jun 2, 2014 at 11:16 AM, Claudio Fontana hw.clau...@gmail.com wrote:
Hello Peter,
I am porting OSv to AArch64, and I have some working code running on
the Foundation Models,
where I run qemu natively with --enable-kvm,
which does not seem to work when run instead on top of the
Il 03/06/2014 13:29, Stefano Stabellini ha scritto:
It's really not your fault, there's not much you can do given the hardware
architecture. But I don't think this code can be accepted upstream, sorry.
Yeah, the code is not nice and it is not Tiejun's fault.
Is there any way at all he could
On 3 June 2014 12:38, Alexey Kardashevskiy a...@ozlabs.ru wrote:
On 06/03/2014 07:45 PM, Peter Maydell wrote:
On 3 June 2014 04:52, Alexey Kardashevskiy a...@ozlabs.ru wrote:
Is there anything I can do to help with this? Chase someone down? :)
Confirming that your lawyers are happy with the
On 06/03/2014 12:29 PM, Stefano Stabellini wrote:
On Tue, 3 Jun 2014, Paolo Bonzini wrote:
Il 30/05/2014 10:59, Tiejun Chen ha scritto:
+static int create_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
+{
+struct PCIDevice *dev;
+
+char rid;
+
+dev = pci_create(bus,
From: Gonglei arei.gong...@huawei.com
Signed-off-by: Gonglei arei.gong...@huawei.com
---
hw/usb/hcd-ohci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index cd87074..dc1adbf 100644
--- a/hw/usb/hcd-ohci.c
+++ b/hw/usb/hcd-ohci.c
@@
After merging 970s into one class, check_pow_970() is used for all of them.
Since POWER5+ is no different in the matter of supported power modes,
let's use the same check_pow() callback for POWER5+ too,
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
target-ppc/translate_init.c | 10
This adds TIR (Thread Identification Register) SPR first defined in
PowerISA 2.05.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
Changes:
v4:
* disabled reading it from user space
---
target-ppc/cpu.h| 1 +
target-ppc/translate_init.c | 5 +
2 files changed, 6
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