On 13/05/15 10:01, Paolo Bonzini wrote:
On 12/05/2015 09:22, Michael Tokarev wrote:
12.05.2015 04:05, Peter Crosthwaite wrote:
On Thu, May 7, 2015 at 2:34 AM, Michael Tokarev m...@tls.msk.ru wrote:
...
Ok, I can reproduce this, winXP BSODs on boot in tcg mode.
Git bisect points to this:
On Thu, Jun 11, 2015 at 12:48:22PM -0400, Kevin O'Connor wrote:
On Thu, Jun 11, 2015 at 04:35:33PM +0200, Laszlo Ersek wrote:
On 06/11/15 15:58, Kevin O'Connor wrote:
On Thu, Jun 11, 2015 at 04:37:08PM +0300, Marcel Apfelbaum wrote:
The fixes solves the following issue:
The PXB device
Hi,
I'm attempting my first hack of qemu, though I've got stuck on how to
correctly write to ps/2 input in the guest.
My idea was that if I create new keyboard (using void *ps2_kbd_init) I
can use that one to write (void ps2_write_keyboard).
The problem is, that this does not seem to do
On Fri, Jun 12, 2015 at 02:40:10PM -0400, Kevin O'Connor wrote:
(2) The QEMU command line and the effects the command line has on the
virtual hardware should not change. However, all of the following have
to be updated:
- the explicit_ofw_unit_address property assignments in
On Sun, Jun 14, 2015 at 02:10:22PM +0200, Michael S. Tsirkin wrote:
On Thu, Jun 11, 2015 at 12:48:22PM -0400, Kevin O'Connor wrote:
The SeaBIOS code is used on both virtual machines and real machines.
The bus number is something that is generated by software and it is
not assured to be
On 06/13/2015 04:52 PM, Laszlo Ersek wrote:
SeaBIOS expects OpenFirmware device paths in the bootorder fw_cfg file
to follow the pattern
/pci-root@N/pci@i0cf8/...
for devices that live behind an extra root bus. The extra root bus in
question is the N'th among the extra root bridges. (In
On Thu, Jun 11, 2015 at 8:14 PM, Andrey Korolyov and...@xdel.ru wrote:
Hello Igor,
the current hotplug code for dimms effectively prohibiting a
successful migration for VM if memory was added after startup:
- start a VM with certain amount of empty memory slots,
- add some dimms and online
On 14 Jun 2015, at 04:49, Peter Crosthwaite peter.crosthwa...@xilinx.com
wrote:
...
The number of machine init args blew out of control at one stage so
they were structified. It was natural to roll this struct into the
machine-state struct.
can we have multiple machine instances
On 06/13/2015 04:39 PM, Laszlo Ersek wrote:
Following up on this cross-posted message, I will send two patch sets,
one for QEMU (to qemu-devel) and another for OVMF (to edk2-devel). With
both in place, OVMF supports multiple PCI root buses, and SeaBIOS
recognizes boot options that reference
On 14 Jun 2015, at 04:49, Peter Crosthwaite peter.crosthwa...@xilinx.com
wrote:
...
Infact, I have an application of constructor arugments myself. This is
for the ARM A9 MPCore container where the number of CPUs is variable
per-instance. Same problem as you are facing, realize is too
On 14 Jun 2015, at 15:43, Liviu Ionescu i...@livius.net wrote:
I never said you cant ref one object from another. QOM links exist for
this exact purpose.
Q: any example of QOM links?
ok, I found them, they are not part of qdev but only in qom.
they look like this:
On Sun, Jun 14, 2015 at 08:06:22PM +0200, Michael S. Tsirkin wrote:
To summarise, you feel that modifying bus id without reordering
bus ids between roots is likely, modifications that would
cause reordering are unlikely, thus counting bus ids
in order gives a stable index. Is that right?
Yes.
On Sun, Jun 14, 2015 at 02:05:52PM +0200, Michael S. Tsirkin wrote:
On Fri, Jun 12, 2015 at 02:40:10PM -0400, Kevin O'Connor wrote:
(2) The QEMU command line and the effects the command line has on the
virtual hardware should not change. However, all of the following have
to be updated:
On Jun 14, 2015, at 1:11 PM, Peter Maydell wrote:
On 18 May 2015 at 17:23, Programmingkid programmingk...@gmail.com wrote:
Adds all removable devices to the Machine menu as a Change and Eject menu
item pair. ide-cd0 would have a Change ide-cd0... and Eject ide-cd0
menu items.
On Sun, Jun 14, 2015 at 10:50:22AM -0400, Kevin O'Connor wrote:
On Sun, Jun 14, 2015 at 02:05:52PM +0200, Michael S. Tsirkin wrote:
On Fri, Jun 12, 2015 at 02:40:10PM -0400, Kevin O'Connor wrote:
(2) The QEMU command line and the effects the command line has on the
virtual hardware
On Jun 14, 2015, at 5:55 AM, Mark Cave-Ayland wrote:
On 13/05/15 10:01, Paolo Bonzini wrote:
On 12/05/2015 09:22, Michael Tokarev wrote:
12.05.2015 04:05, Peter Crosthwaite wrote:
On Thu, May 7, 2015 at 2:34 AM, Michael Tokarev m...@tls.msk.ru wrote:
...
Ok, I can reproduce this, winXP
On Sun, Jun 14, 2015 at 11:47 AM, Liviu Ionescu i...@livius.net wrote:
On 13 Jun 2015, at 12:29, Peter Crosthwaite peter.crosthwa...@xilinx.com
wrote:
There is a way :). Check object_class_get_parent. qdev.c uses it to
implement device properties on multiple levels without overriding. You
On Sun, 2015-06-14 at 20:06 +0200, Michael S. Tsirkin wrote:
As I understand it, the use case for multiple PCI roots is large
servers that process a lot of IO.
For better or worse, guest OS-es assume that numa locality
can only be specified for PCI roots.
So the use case is to specify
On 06/14/15 12:08, Marcel Apfelbaum wrote:
On 06/13/2015 04:52 PM, Laszlo Ersek wrote:
SeaBIOS expects OpenFirmware device paths in the bootorder fw_cfg file
to follow the pattern
/pci-root@N/pci@i0cf8/...
for devices that live behind an extra root bus. The extra root bus in
question is
On 06/14/15 12:09, Marcel Apfelbaum wrote:
On 06/13/2015 04:39 PM, Laszlo Ersek wrote:
Following up on this cross-posted message, I will send two patch sets,
one for QEMU (to qemu-devel) and another for OVMF (to edk2-devel). With
both in place, OVMF supports multiple PCI root buses, and
On 18 May 2015 at 04:51, Programmingkid programmingk...@gmail.com wrote:
Add Machine menu to the Macintosh interface with pause
and resume menu items. These items can either pause or
resume execution of the guest operating system.
Signed-off-by: John Arbuckle programmingk...@gmail.com
On 18 May 2015 at 17:23, Programmingkid programmingk...@gmail.com wrote:
Adds all removable devices to the Machine menu as a Change and Eject menu
item pair. ide-cd0 would have a Change ide-cd0... and Eject ide-cd0
menu items.
Signed-off-by: John Arbuckle programmingk...@gmail.com
I'm afraid
On 17 May 2015 at 22:27, Programmingkid programmingk...@gmail.com wrote:
Add Reset and Power Down menu items to Machine menu.
Signed-off-by: John Arbuckle programmingk...@gmail.com
Thanks, applied to cocoa.next.
-- PMM
On 13 Jun 2015, at 12:29, Peter Crosthwaite peter.crosthwa...@xilinx.com
wrote:
There is a way :). Check object_class_get_parent. qdev.c uses it to
implement device properties on multiple levels without overriding. You
still need to explicit call to superclass in each child class but that
On 14 June 2015 at 18:48, Programmingkid programmingk...@gmail.com wrote:
On Jun 14, 2015, at 1:11 PM, Peter Maydell wrote:
On 18 May 2015 at 17:23, Programmingkid programmingk...@gmail.com wrote:
Adds all removable devices to the Machine menu as a Change and Eject menu
item pair. ide-cd0
Created an ARM_FEATURE_THUMB_DSP to be added to any non-M
thumb2-compatible CPU that uses DSP instructions. There are 85 DSP
instructions (all of them thumb2). On disas_thumb2_insn the DSP feature is
tested before the instruction is generated; if it's not enabled then its an
illegal op.
On Mon, Jun 15, 2015 at 07:39:18AM +1000, Benjamin Herrenschmidt wrote:
On Sun, 2015-06-14 at 20:06 +0200, Michael S. Tsirkin wrote:
As I understand it, the use case for multiple PCI roots is large
servers that process a lot of IO.
For better or worse, guest OS-es assume that numa
Add the ARM a9/a15 Cortex CPUs to their respective MPCore containers.
Update all users or MPCore to not instantiate CPUs on the machine
level.
A9 MPCore needs to be extended with the external interrupt controller
capability (which ors a set of pins with the GIC CPU IRQs). This is
needed by
Using a getter or trying to resolve an overloaded property is
ambiguous. Disallow it.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
qom/object.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/qom/object.c b/qom/object.c
index 967ed0d..1590df7 100644
On Fri, Jun 12, 2015 at 05:44:24PM +0100, Peter Maydell wrote:
On 5 June 2015 at 11:33, Edgar E. Iglesias edgar.igles...@gmail.com wrote:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Adds support for the virtual timer offset controlled by EL2.
Signed-off-by: Edgar E. Iglesias
Hi All,
This series introduced support for multi QOM properties with the same
name and then moves the ARM CPUs to the MPCore container objects (yes!
they are related!)
The application of the QOM change is container objects passing through
a single property on multiple same-type children as a
Add a mechanism to allow property name overloading. The property being
overloaded must explicitly allow it and the property types must match,
otherwise an error is returned as normal.
Once the property has been overloaded, set a flag indicating as such,
so operations that don't make sense for
So that container objects can implement multi-way setting aliases of
their contained objects.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
qom/object.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/qom/object.c b/qom/object.c
index 1590df7..496bed8 100644
---
On Mon, Jun 8, 2015 at 11:59 AM, Markus Armbruster arm...@redhat.com wrote:
Liviu Ionescu i...@livius.net writes:
similar to the object naming convention (where names-with-dashes are
preferred), I would like to know if this convention can also be
applied to file names?
I noticed a lot of
Adds all removable devices to the Machine menu as a Change and Eject menu
item pair. ide-cd0 would have a Change ide-cd0... and Eject ide-cd0
menu items.
Signed-off-by: John Arbuckle programmingk...@gmail.com
---
Removed depreciated code from QEMU_Alert().
Unified supported image file extensions
To not be a trial and error based approach. Rather, explicitly scan the
existing property lists for the array format strings using a nested
strcmp loop.
This prepares support for multiple properties with the same name.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
Set the description/value of all matching properties for a given
name.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
qom/object.c | 29 +++--
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/qom/object.c b/qom/object.c
index
Into its own function. This prepares support for cpu-inclusive MPCores
which may need to have these props set for them as well.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/arm/realview.c | 46 +++---
1 file changed, 27
If a property name is overloaded all instances should be deleted by the
deleter.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
qom/object.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/qom/object.c b/qom/object.c
index
On Fri, Jun 12, 2015 at 05:51:55PM +0100, Peter Maydell wrote:
On 5 June 2015 at 11:33, Edgar E. Iglesias edgar.igles...@gmail.com wrote:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Adds control for trapping selected timer and counter accesses to EL2.
Signed-off-by: Edgar E.
On Fri, Jun 12, 2015 at 06:00:15PM +0100, Peter Maydell wrote:
On 5 June 2015 at 11:33, Edgar E. Iglesias edgar.igles...@gmail.com wrote:
From: Edgar E. Iglesias edgar.igles...@xilinx.com
Signed-off-by: Edgar E. Iglesias edgar.igles...@xilinx.com
---
static const ARMCPRegInfo
Move the ARM coprocessor API to a new C file. helper.c is huge and
splitting off this self contained piece increases modularity.
Signed-off-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
---
I also need this for multi-arch where, this file needs to remain obj-y
while the others in target-arm
On Thu, Jun 4, 2015 at 11:42 PM, Alistair Francis
alistair.fran...@xilinx.com wrote:
Originally the version_mask PVR bits were manually set for each
machine. This is a hassle and difficult to read, instead set them
based on the CPU properties.
Signed-off-by: Alistair Francis
On Thu, Jun 4, 2015 at 11:43 PM, Alistair Francis
alistair.fran...@xilinx.com wrote:
Move the hard coded register values to the init function.
This also allows the entire reset function to be deleted, as
PVR registers are now preserved on reset.
The hardcoded PVR0 values can be removed as
On Thu, Jun 4, 2015 at 11:44 PM, Alistair Francis
alistair.fran...@xilinx.com wrote:
This code is already being run in the mb_cpu_realizefn()
function. As PVR registers are preserved on reset this
code is not required.
Signed-off-by: Alistair Francis alistair.fran...@xilinx.com
Reviewed-by:
On Thu, Jun 4, 2015 at 11:43 PM, Alistair Francis
alistair.fran...@xilinx.com wrote:
Remove the hardcoded values from the machine specific reset
function, as the same values are already set in the standard
MicroBlaze reset.
This also allows the entire reset function to be deleted, as
PVR
Use cpu_set_pc across the board for setting program counters. This
removes instances of system level code having to reach into the CPU
env.
Signed-off-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
---
hw/arm/boot.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff
Use the cpu_set_pc helper which will take care of CPUClass retrieval
for us.
Signed-off-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
---
gdbstub.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 75563db..ceb60ac 100644
--- a/gdbstub.c
+++
ARM program counters are always at least 16b aligned with the LSB
being only used the indicate thumb mode in exchange situations. Mask
this bit off in set_pc to ignore the exchange semantic (which must
still be managed by the caller).
Signed-off-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
Add a wrapper around the CPUClass::set_pc hook. Accepts an error
pointer to report the case where the hook is not set.
Signed-off-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
---
include/qom/cpu.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/include/qom/cpu.h
Use cpu_set_pc for setting program counters when bootloading. This
removes an instance of system level code having to reach into the CPU
env.
Signed-off-by: Peter Crosthwaite crosthwaite.pe...@gmail.com
---
hw/microblaze/boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Mon, Jun 8, 2015 at 4:31 PM, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
From: Alistair Francis alistair.fran...@xilinx.com
Originally the dcache-writeback PVR bits were manually set for each machine.
This is a hassle and difficult to read, instead set them based on the CPU
On Mon, Jun 8, 2015 at 4:31 PM, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
From: Alistair Francis alistair.fran...@xilinx.com
Originally the use-mmu PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
On Thu, Jun 4, 2015 at 11:41 PM, Alistair Francis
alistair.fran...@xilinx.com wrote:
Originally the endi PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis
On Thu, Jun 4, 2015 at 11:42 PM, Alistair Francis
alistair.fran...@xilinx.com wrote:
Originally the pvr-full PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis
On Sun, 2015-06-14 at 17:59 -0400, Kevin O'Connor wrote:
There are x86 systems with multiple separate PCI root buses where one
can access the pci config space of all the buses using the same 0x0cf8
IO space. During system setup, the multiple PCI root buses are each
configured to only respond
On Wed, Jun 10, 2015 at 12:51 AM, Pavel Fedin p.fe...@samsung.com wrote:
The function originally behaves very badly when adding properties with [*]
suffix. Normally these are used for numbering IRQ pins. In order to find the
correct starting number the function started from zero and checked for
Wrap the CPUClass::set_pc fn hook in a caller helper to reduce
verbosity of calls. Simplify the call from the gdbstub.
Then use the call to abstract away the PC env fields from the ARM and
Microblaze bootloaders.
This moves towards the goal of minimising system level code of the CPU
env (and one
From: Aurelien Jarno [mailto:aurel...@aurel32.net]
On 2015-06-10 11:33, Pavel Dovgalyuk wrote:
This patch fixes exception handling in MIPS.
MIPS instructions generate several types of exceptions.
When exception is generated, it breaks the execution of the current
translation
block.
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