On Fri, Jun 19, 2015 at 7:57 PM, Andrey Korolyov and...@xdel.ru wrote:
I don`t think that it could be ACPI-related in any way, instead, it
looks like race in vhost or simular mm-touching mechanism. The
repeated hits you mentioned should be fixed as well indeed, but they
can be barely the
On Fri, May 15, 2015 at 03:51:36PM +0800, Wen Congyang wrote:
If bus_size is less than 0, the command fails.
If buf_size is 0, use DEFAULT_MIRROR_BUF_SIZE.
If buf_size % granularity is not 0, mirror_free_init() will
do dangerous things.
Signed-off-by: Wen Congyang we...@cn.fujitsu.com
Hi Michael,
Have you had a chance to look at this?
There's no hurry, im just curious.
Thanks,
Sean
-Original Message-
From: Sean O. Stalley [mailto:sean.stal...@intel.com]
Sent: Monday, June 01, 2015 9:38 AM
To: Michael S. Tsirkin
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH 1/1]
On 19.06.2015 19:08, Peter Maydell wrote:
On 19 June 2015 at 15:48, Denis V. Lunev d...@openvz.org wrote:
From: Pavel Butsykin pbutsy...@virtuozzo.com
Added the hmp command to query io apic state, may be usefull after guest
crashes to understand IRQ routing in guest.
Implementation is only
On 19.06.2015 18:45, Andreas Färber wrote:
Am 19.06.2015 um 16:48 schrieb Denis V. Lunev:
From: Pavel Butsykin pbutsy...@virtuozzo.com
Added the hmp command to query local apic registers state, may be
usefull after guest crashes to understand IRQ routing in guest.
For command name uses
On 19.06.2015 18:53, Andreas Färber wrote:
Am 19.06.2015 um 16:48 schrieb Denis V. Lunev:
From: Pavel Butsykin pbutsy...@virtuozzo.com
Added the hmp command to query io apic state, may be usefull after guest
crashes to understand IRQ routing in guest.
Implementation is only for kvm here.
The wait command should check to make sure SACT is clear as well
as the Command Issue register.
Signed-off-by: John Snow js...@redhat.com
---
tests/libqos/ahci.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/tests/libqos/ahci.c b/tests/libqos/ahci.c
index
Don't attempt the NCQ transfer if the PRDT we were given is not big
enough to perform the entire transfer.
Signed-off-by: John Snow js...@redhat.com
---
hw/ide/ahci.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index
Most of the time, these bits can be safely ignored. For the purposes
of debugging however, it's nice to know that they're not being used.
Signed-off-by: John Snow js...@redhat.com
---
hw/ide/ahci.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/hw/ide/ahci.c
Trivial cleanup that I didn't want to tack-on to anything else.
Signed-off-by: John Snow js...@redhat.com
---
hw/ide/ahci.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 26df2ca..14eccb8 100644
--- a/hw/ide/ahci.c
+++
NCQ commands have the concept of a TAG that they need to set,
but in the AHCI world, it is mandated that the TAG always match
the command slot that you executed the NCQ from.
See AHCI 9.3.1.1.5.2 Native Queued Commands.
Signed-off-by: John Snow js...@redhat.com
---
tests/libqos/ahci.c | 5 +
NCQ frames are generated a little differently than
their non-NCQ cousins. Add support for them.
Signed-off-by: John Snow js...@redhat.com
---
tests/libqos/ahci.c | 44 +++-
tests/libqos/ahci.h | 29 -
2 files changed, 63
Signed-off-by: John Snow js...@redhat.com
---
tests/ahci-test.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/tests/ahci-test.c b/tests/ahci-test.c
index 941e0dd..206e6bb 100644
--- a/tests/ahci-test.c
+++ b/tests/ahci-test.c
@@ -1140,9 +1140,9 @@ static
NCQ commands are LBA48 by definition.
See SATA 3.2 13.6.4.1 READ FPDMA QUEUED, or
SATA 3.2 13.6.5.1 WRITE FPDMA QUEUED.
Signed-off-by: John Snow js...@redhat.com
---
tests/libqos/ahci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/libqos/ahci.c
NCQ commands will expect the SDBS interrupt,
and in the normative case, do not expect to see
a D2H Register FIS unless something went wrong.
Signed-off-by: John Snow js...@redhat.com
---
tests/libqos/ahci.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git
At 2015/6/19 18:49, Stefan Hajnoczi Wrote:
On Fri, Jun 19, 2015 at 08:54:56AM +0800, Wen Congyang wrote:
On 06/19/2015 12:06 AM, Stefan Hajnoczi wrote:
On Thu, Jun 18, 2015 at 10:36:39PM +0800, Wen Congyang wrote:
At 2015/6/18 20:55, Stefan Hajnoczi Wrote:
On Thu, Jun 18, 2015 at 04:49:12PM
@cc Fam Zheng f...@redhat.com,
as he's the author of tcmalloc support patch
- Mail original -
De: aderumier aderum...@odiso.com
À: qemu-devel qemu-devel@nongnu.org
Cc: aderumier aderum...@odiso.com
Envoyé: Vendredi 19 Juin 2015 12:56:58
Objet: [PATCH] configure: Add support for jemalloc
Set some appropriate error bits for NCQ for us.
Signed-off-by: John Snow js...@redhat.com
---
hw/ide/ahci.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 14eccb8..375aa44 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@
requires: 1434470575-21625-1-git-send-email-js...@redhat.com
[PATCH v2 0/4] ahci: misc fixes/tests for 2.4
This series adds a couple of tests to exercise the NCQ pathways
and establish a baseline for us.
Most of these patches are fairly short and should be relatively trivial
to review.
NCQ commands should not / do not update the byte count
in the command header post command, so this field is
meaningless for NCQ tests.
Signed-off-by: John Snow js...@redhat.com
---
tests/libqos/ahci.c | 46 --
tests/libqos/ahci.h | 3 +--
2 files
Several fields of the NCQFIS structure are ambiguously named. This patch
clarifies the intended (if unsupported) usage of the NCQ fields to aid
in creating more meaningful debug messages through the NCQ codepaths.
Signed-off-by: John Snow js...@redhat.com
---
hw/ide/ahci.h | 35
Hi Laurent,
On 20/06/15 05:39, Laurent Vivier wrote:
Le 19/06/2015 15:43, g...@uclinux.org a écrit :
Some small issues are causing problems with running modern versions of
Linux on the m68k/ColdFire 5208 target. These 3 patches fix those problems.
They are all due to use of more advanced
There's no real reason to have it bundled together, and this way
is a little nicer to follow if you have the AHCI spec pulled up.
Signed-off-by: John Snow js...@redhat.com
---
hw/ide/ahci.c | 23 ---
hw/ide/ahci.h | 3 ++-
2 files changed, 14 insertions(+), 12 deletions(-)
Test the NCQ pathways for a simple IO RW test.
Also, test that libqos doesn't explode when
running NCQ commands :)
Signed-off-by: John Snow js...@redhat.com
---
tests/ahci-test.c | 13 +
tests/libqos/ahci.c | 46 +-
tests/libqos/ahci.h |
This value should not be size-corrected, 0 sectors does not imply
1 sector(s). This is just debug information, but it's misleading!
Signed-off-by: John Snow js...@redhat.com
---
hw/ide/ahci.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
The legacy ide command execution layer will clear any errors outstanding
before execution, but the NCQ layer doesn't.
Even on success, this register will remain clogged.
Clear it out before each NCQ command so the guest can tell if the
error code produced after completion is meaningful or not.
With the pc-q35-2.4 machine type, if the user creates an ISA FDC manually:
-device isa-fdc,driveA=drive-fdc0-0-0 \
-drive file=...,if=none,id=drive-fdc0-0-0,format=raw
then the board-default FDC will be skipped, and only the explicitly
requested FDC will exist. qtree-wise, this is correct;
Extract the pc_cmos_init_floppy() function from pc_cmos_init(). The
function sets two RTC registers: floppy drive types (0x10), overwriting
the earlier value in there), and REG_EQUIPMENT_BYTE (0x14), setting bits
in the prior value.
Cc: Jan Tomko jto...@redhat.com
Cc: John Snow js...@redhat.com
This is for the other pc-q35-2.4 ISA-FDC problem reported by Jan.
Jan, can you give it a try pls?
Cc: Jan Tomko jto...@redhat.com
Cc: John Snow js...@redhat.com
Cc: Markus Armbruster arm...@redhat.com
Cc: Paolo Bonzini pbonz...@redhat.com
Laszlo Ersek (2):
hw/i386/pc: factor out
On 06/19/2015 09:50 PM, John Snow wrote:
Signed-off-by: John Snow js...@redhat.com
---
tests/ahci-test.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/tests/ahci-test.c b/tests/ahci-test.c
index 941e0dd..206e6bb 100644
--- a/tests/ahci-test.c
+++
On 19 June 2015 at 06:00, Greg Ungerer g...@uclinux.org wrote:
Hi All,
I see in the MAINTAINERS file that pretty much everything related
to the m68k architecture is listed as Orphan.
I have some patches that have been around for quite a while (posted
here twice) to fix some issues with the
1) Line lengths above 80 characters do exist. They are rare, but
they happen from time to time. An ignored rule is worse than an
exception to the rule, so do the latter.
2) Mixed declarations also do exist at the top of #ifdef blocks.
Remark on this particular usage and suggest an alternative.
tap_fd_set_vnet_le/tap_fd_set_vnet_be was missing,
fix it up.
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
net/tap-aix.c | 10 ++
net/tap-bsd.c | 10 ++
net/tap-haiku.c | 10 ++
net/tap-solaris.c | 10 ++
net/tap-win32.c | 10 ++
5
On 19 Jun 2015, at 09:42, Paolo Bonzini pbonz...@redhat.com wrote:
On 19/06/2015 09:40, Mark Burton wrote:
On 19/06/2015 09:29, Mark Burton wrote:
Does anybody know if the current atomic_cmpxchg will support
64 bit on a (normal) 32 bit x86, or do we need to special
case that with
Hi Peter,
On 19/06/15 15:24, Peter Crosthwaite wrote:
On Mon, Aug 18, 2014 at 10:37 PM, g...@uclinux.org wrote:
From: Greg Ungerer g...@uclinux.org
Implement the SIMR and CIMR registers of the 5208 interrupt controller.
These are used by modern versions of Linux running on ColdFire (not
On Wed, Jun 17, 2015 at 02:12:14PM +0530, Nikunj A Dadhania wrote:
David Gibson da...@gibson.dropbear.id.au writes:
On Thu, Jun 11, 2015 at 04:32:26PM +0530, Nikunj A Dadhania wrote:
All the PCI enumeration and device node creation was off-loaded to
SLOF. With PCI hotplug support, code
On Thu, Jun 18, 2015 at 11:49 PM, Greg Ungerer g...@uclinux.org wrote:
Hi Peter,
On 19/06/15 15:49, Peter Crosthwaite wrote:
On Mon, Aug 18, 2014 at 10:37 PM, g...@uclinux.org wrote:
From: Greg Ungerer g...@uclinux.org
The action to potentially switch sp register is not occurring at the
On 19/06/2015 09:40, Mark Burton wrote:
On 19/06/2015 09:29, Mark Burton wrote:
Does anybody know if the current atomic_cmpxchg will support
64 bit on a (normal) 32 bit x86, or do we need to special
case that with cmpxchg8b ? (I get the impression that it will
automatically use cmpxchg8b,
On 19 Jun 2015, at 09:31, Paolo Bonzini pbonz...@redhat.com wrote:
On 19/06/2015 09:29, Mark Burton wrote:
Does anybody know if the current atomic_cmpxchg will support 64 bit
on a (normal) 32 bit x86, or do we need to special case that with
cmpxchg8b ? (I get the impression that it
On 19 June 2015 at 08:17, Greg Ungerer g...@uclinux.org wrote:
Hi Peter,
On 19/06/15 17:12, Peter Maydell wrote:
If you make the minor fixes Peter C has suggested, rebase
them onto current master and resend with the relevant
reviewed-by: tags in the commit messages, I'll apply
them to
From: Lu Lina lina.lul...@huawei.com
Signed-off-by: Lu Lina lina.lul...@huawei.com
---
hw/block/nvme.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 4b6d5e6..c6a6a0e 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -154,6 +154,7 @@ static
Hi Peter,
On 19/06/15 15:49, Peter Crosthwaite wrote:
On Mon, Aug 18, 2014 at 10:37 PM, g...@uclinux.org wrote:
From: Greg Ungerer g...@uclinux.org
The action to potentially switch sp register is not occurring at the correct
point in the interrupt entry or exception exit sequences.
For
Hi Peter,
On 19/06/15 17:12, Peter Maydell wrote:
On 19 June 2015 at 06:00, Greg Ungerer g...@uclinux.org wrote:
Hi All,
I see in the MAINTAINERS file that pretty much everything related
to the m68k architecture is listed as Orphan.
I have some patches that have been around for quite a
David Gibson da...@gibson.dropbear.id.au writes:
On Thu, Jun 18, 2015 at 09:35:44PM +1000, Alexey Kardashevskiy wrote:
On 05/05/2015 10:49 PM, David Gibson wrote:
On Sat, Apr 25, 2015 at 10:24:43PM +1000, Alexey Kardashevskiy wrote:
This adds support for Dynamic DMA Windows (DDW) option
On 18/06/2015 22:24, Peter Crosthwaite wrote:
I'm pushing everything I have to tcg-arm-setend on my github repo.
Already found that branch and have rebased it. It looks like since
yesterday your merge base has changed but is not fully up to date.
Yes, the one before was tested but
On Thu, Jun 18, 2015 at 05:29:23PM +0100, Peter Maydell wrote:
On 18 June 2015 at 12:14, Michael S. Tsirkin m...@redhat.com wrote:
On Thu, Jun 18, 2015 at 11:36:26AM +0100, Peter Maydell wrote:
Hi. I'm afraid this fails to build for OSX:
LINK arm-softmmu/qemu-system-arm
Undefined
The following changes since commit 93f6d1c16036aaf34055d16f54ea770fb8d6d280:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-20150615-1' into
staging (2015-06-16 10:35:43 +0100)
are available in the git repository at:
git://github.com/bonzini/qemu.git tags/for-upstream
for you
From: Fam Zheng f...@redhat.com
Signed-off-by: Fam Zheng f...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
tests/libqos/virtio.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/tests/libqos/virtio.h b/tests/libqos/virtio.h
index 2449fee..0101278
Am 18.06.2015 um 11:36 schrieb Stefan Hajnoczi:
On Thu, Jun 18, 2015 at 10:29 AM, Peter Lieven p...@kamp.de wrote:
Am 18.06.2015 um 10:42 schrieb Kevin Wolf:
Am 18.06.2015 um 10:30 hat Peter Lieven geschrieben:
Am 18.06.2015 um 09:45 schrieb Kevin Wolf:
Am 18.06.2015 um 09:12 hat Peter Lieven
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Add a string property that specifies the primary boot cpu. All CPUs
except the one selected will start-powered-off. This allows for elf
boots on any CPU, which prepares support for booting R5 elfs directly
on the R5 processors.
Signed-off-by:
From: Aurelio C. Remonda aurelioremo...@gmail.com
This patch adds the Cortex-M4 CPU. The M4 is basically the same as
the M3, the main differences being the DSP instructions and an
optional FPU. Only no-FPU cortex-M4 is implemented here, cortex-M4F
is not because the core target-arm code doesn't
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Add the 2xCortexR5 CPUs to zynqmp board. They are powered off on reset
(this is true of real hardware) by default or selectable as the boot
processor.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
. Other than that
I think we should be down to bugfix patches.
-- PMM
The following changes since commit ffdb1409a79c9cc91afd9f58df625fdca16bf8b9:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-cocoa-20150619-1'
into staging (2015-06-19 12:54:08 +0100)
are available in the git
qdev_init() is a wrapper around setting property realized to true,
plus error handling that passes errors to qerror_report_err().
qerror_report_err() is a transitional interface to help with
converting existing monitor commands to QMP. It should not be used
elsewhere.
All code has been
From: Yossi Hindin yhin...@redhat.com
Debug printouts extended, helps installation troubleshooting
Signed-off-by: Yossi Hindin yhin...@redhat.com
Message-Id: 1430913460-13174-3-git-send-email-yhin...@redhat.com
Signed-off-by: Paolo Bonzini pbonz...@redhat.com
---
qga/channel-win32.c | 2 +-
From: Paul Donohue qemu-de...@paulsd.com
Commit 691a0c9c introduced a mechanism by which QEMU_CLOCK_HOST can
notify other parts of the emulator when the host clock has jumped
backward. This is used to avoid stalling timers that were scheduled
based on the host clock.
However, if the host clock
On Fri, 19 Jun 2015 09:29:04 +0200
Paolo Bonzini pbonz...@redhat.com wrote:
1) Line lengths above 80 characters do exist. They are rare, but
they happen from time to time. An ignored rule is worse than an
exception to the rule, so do the latter.
2) Mixed declarations also do exist at the
Am 19.06.2015 um 09:29 schrieb Paolo Bonzini:
1) Line lengths above 80 characters do exist. They are rare, but
they happen from time to time. An ignored rule is worse than an
exception to the rule, so do the latter.
2) Mixed declarations also do exist at the top of #ifdef blocks.
Remark
On Fri, 19 Jun 2015 09:44:00 +0200
Michael S. Tsirkin m...@redhat.com wrote:
tap_fd_set_vnet_le/tap_fd_set_vnet_be was missing,
fix it up.
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
net/tap-aix.c | 10 ++
net/tap-bsd.c | 10 ++
net/tap-haiku.c | 10
On 19 June 2015 at 08:30, Michael S. Tsirkin m...@redhat.com wrote:
They are trivial - a single patch on top that adds stubs for missing
platforms. And I think breaking bisect on non-linux isn't a big deal.
If you agree, please apply.
I would prefer the fix folded in to the correct point in
Until now the vvfat volume label was hardcoded to be
QEMU VVFAT, now you can pass a file.label=labelname option
to the -drive to change it.
The FAT structure defines the volume label to be limited to
11 bytes and is filled up spaces when shorter than that. The
trailing spaces however aren't
On 19/06/2015 12:03, Andreas Färber wrote:
Am 27.05.2015 um 20:20 schrieb Andreas Färber:
From: Daniel P. Berrange berra...@redhat.com
Some types of object must be created before chardevs, other types of
object must be created after chardevs. As such there is no option but
to create
This series introduces the Unified Hosting Interface support to QEMU.
Version 3 of this patchset contains just minor cleanup and corrections
in mips-semi.c comparing to previous version.
It has been on the mailing list for a while and given that command line
option responsible for passing
On Thu 18 Jun 2015 02:36:13 PM CEST, Eric Blake wrote:
[Detecting support for intermediate block streaming]
One possibility is to try to stream to an intermediate node and see
if it fails.
Example: in a chain like [A] - [B] - [C], streaming to [B] using
[A] as the 'base' parameter is a
On Fri, Jun 19, 2015 at 09:32:48AM +0100, Peter Maydell wrote:
On 19 June 2015 at 08:30, Michael S. Tsirkin m...@redhat.com wrote:
They are trivial - a single patch on top that adds stubs for missing
platforms. And I think breaking bisect on non-linux isn't a big deal.
If you agree, please
Make use of pc-dimm infrastructure to support memory hotplug
for PowerPC.
Signed-off-by: Bharata B Rao bhar...@linux.vnet.ibm.com
---
hw/ppc/spapr.c| 126 ++
hw/ppc/spapr_events.c | 8 ++--
2 files changed, 131 insertions(+), 3
On 19/06/2015 12:28, Andrey Smetanin wrote:
On Wed, 2015-06-17 at 14:44 +0200, Paolo Bonzini wrote:
On 11/06/2015 15:18, Denis V. Lunev wrote:
From: Andrey Smetanin asmeta...@virtuozzo.com
Windows 2012 guests can notify hypervisor about occurred guest crash
(Windows bugcheck(BSOD)) by
On Fri, Jun 19, 2015 at 02:27:34PM +0800, Ting Wang wrote:
Please CC the maintainer of this source file:
$ scripts/get_maintainer.pl -f hw/block/nvme.c
Keith Busch keith.bu...@intel.com (supporter:nvme)
Kevin Wolf kw...@redhat.com (supporter:Block layer core)
qemu-bl...@nongnu.org (open
Am 13.06.2015 um 13:18 schrieb Markus Armbruster:
Also polish an error message while I'm touching the line anyway,
Signed-off-by: Markus Armbruster arm...@redhat.com
Reviewed-by: Eric Blake ebl...@redhat.com
---
include/monitor/qdev.h | 2 +-
qdev-monitor.c | 36
Andreas Färber afaer...@suse.de writes:
Am 13.06.2015 um 13:18 schrieb Markus Armbruster:
It's a perfectly sensible helper function.
But only in the current state. Once/if we just set realized=true on
/machine level, then no other helper functions will need to set it, as
pointed out in the
Andreas Färber afaer...@suse.de writes:
Hi Markus,
Could you please add a verbose rationale here like qdev_init() does not
propagate the Error* and should be replaced by ...?
What about:
qdev_init() is a wrapper around setting property realized to true
plus error handling, which
On Fri, Jun 19, 2015 at 02:52:16PM +0200, Laszlo Ersek wrote:
Your merge is closer to a rewrite than to conflict resolution, rendering
my R-by totally meaningless.
In the future, please either fully test such a merge, or ask the
submitter / reviewers to review and test.
Yes, please.
From: Sergey Fedorov serge.f...@gmail.com
cp_reg_reset() is called from g_hash_table_foreach() which does not
define a specific ordering of the hash table iteration. Thus doing reset
for registers marked as ALIAS would give an ambiguous result when
resetvalue is different for original and alias
Andreas Färber afaer...@suse.de writes:
Did you mean avalanche?
Yes, fixing...
Am 13.06.2015 um 13:18 schrieb Markus Armbruster:
Reproducer:
$ qemu-system-x86_64 -nodefaults -device virtio-rng-pci -device
virtio-rng-pci -device virtio-rng-device,bus=virtio-bus
From: Greg Ungerer g...@uclinux.org
Fill out the code support for the move to/from usp instructions. They are
being decoded, but there is no code to support there actions. So add it.
Current versions of Linux running on the ColdFire 5208 use these instructions.
Signed-off-by: Greg Ungerer
From: Greg Ungerer g...@uclinux.org
The action to potentially switch sp register is not occurring at the correct
point in the interrupt entry or exception exit sequences.
For the interrupt entry case the sp on entry is used to create the stack
exception frame - but this may well be the user
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Introduce a CPU model for the Cortex R5 processor. ARMv7 with MPU,
and both thumb and ARM div instructions.
Also implement dummy ATCM and BTCM. These CPs are defined for R5 but
don't have a lot of meaning in QEMU yet. Raz them so the guest can
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Unified MPU only. Uses ARM architecture major revision to switch
between PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains
unsupported and is asserted against.
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
Signed-off-by: Peter
From: Eric Auger eric.au...@linaro.org
This patch allows the instantiation of the vfio-calxeda-xgmac device
from the QEMU command line (-device vfio-calxeda-xgmac,host=device).
A specialized device tree node is created for the guest, containing
compat, dma-coherent, reg and interrupts
It's a perfectly sensible helper function.
Signed-off-by: Markus Armbruster arm...@redhat.com
Reviewed-by: Eric Blake ebl...@redhat.com
---
include/hw/qdev-core.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index
Signed-off-by: Markus Armbruster arm...@redhat.com
Reviewed-by: Eric Blake ebl...@redhat.com
Reviewed-by: Andreas Färber afaer...@suse.de
---
qdev-monitor.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/qdev-monitor.c b/qdev-monitor.c
index 12d8f6b..c7b00e0 100644
---
On Fri, Jun 19, 2015 at 12:55:57PM +0200, Markus Armbruster wrote:
Michael S. Tsirkin m...@redhat.com writes:
On Fri, Jun 19, 2015 at 11:13:40AM +0100, Peter Maydell wrote:
On 19 June 2015 at 11:07, Michael S. Tsirkin m...@redhat.com wrote:
On Fri, Jun 19, 2015 at 12:00:53PM +0200, Greg
Some small issues are causing problems with running modern versions of
Linux on the m68k/ColdFire 5208 target. These 3 patches fix those problems.
They are all due to use of more advanced architecture features not used
in older Linux kernels.
Regards
Greg
v2:
* rebased to current master head
From: Greg Ungerer g...@uclinux.org
Implement the SIMR and CIMR registers of the 5208 interrupt controller.
These are used by modern versions of Linux running on ColdFire (not sure
of the exact version they were introduced, but they have been in for quite
a while now).
Without this change when
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
The CPUs currently supported by zynqmp are the APU (application
processing unit) CPUs. There are other CPUs in Zynqmp so unqualified
cpus in ambiguous. Preface the variables with APU accordingly, to
prepare support adding the RPU (realtime
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define the MPUIR register for MPU supporting ARMv6 and onwards.
Currently we only support unified MPU.
The size of the unified MPU is defined via the number of dregions.
So just a single config is added to specify this size. (When split MPU
is
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Define the arm CP registers for PMSAv7 and their accessor functions.
RGNR serves as a shared index that indexes into arrays storing the
DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd
separately from the CP interface using a
On Thu, Jun 18, 2015 at 06:43:45PM +0200, Kővágó, Zoltán wrote:
@@ -713,8 +710,6 @@ int net_init_tap(const NetClientOptions *opts, const char
*name,
const char *vhostfdname;
char ifname[128];
-assert(opts-kind == NET_CLIENT_OPTIONS_KIND_TAP);
-tap = opts-tap;
...
@@
On Fri, Jun 19, 2015 at 04:00:05PM +0200, Markus Armbruster wrote:
Michael S. Tsirkin m...@redhat.com writes:
On Fri, Jun 19, 2015 at 12:55:57PM +0200, Markus Armbruster wrote:
Michael S. Tsirkin m...@redhat.com writes:
On Fri, Jun 19, 2015 at 11:13:40AM +0100, Peter Maydell wrote:
Only the calls in do_device_add() remain, because QMP's command
handler interface requires them. They'll go away when I wean QMP off
QError.
Bonus: a few error reporting improvements.
Casualty: some explanatory messages, see PATCH 5.
v3:
* Trivially rebased, R-bys retained
* PATCH 1: Add
As usual, the conversion breaks printing explanatory messages after
the error: actual printing of the error gets delayed, so the
explanations precede rather than follow it.
Pity. Disable them for now. See also commit 7216ae3.
While there, eliminate QERR_BUS_NOT_FOUND, and clean up unusual
From: Leon Alrae leon.al...@imgtec.com
Add new arg sub-argument to the --semihosting-config allowing the user
to pass multiple input arguments separately. It is required for example
by UHI semihosting to construct argc and argv.
Also, update ARM semihosting to support new option (at the moment
Andreas Färber afaer...@suse.de writes:
Am 13.06.2015 um 13:18 schrieb Markus Armbruster:
Also polish an error message while I'm touching the line anyway,
Signed-off-by: Markus Armbruster arm...@redhat.com
Reviewed-by: Eric Blake ebl...@redhat.com
---
include/monitor/qdev.h | 2 +-
From: Leon Alrae leon.al...@imgtec.com
Remove semihosting_enabled and semihosting_target and replace them with
SemihostingConfig structure containing equivalent fields. The structure
is defined in vl.c where it is actually set.
Also introduce separate header file include/exec/semihost.h allowing
Michael S. Tsirkin m...@redhat.com writes:
On Fri, Jun 19, 2015 at 12:55:57PM +0200, Markus Armbruster wrote:
Michael S. Tsirkin m...@redhat.com writes:
On Fri, Jun 19, 2015 at 11:13:40AM +0100, Peter Maydell wrote:
On 19 June 2015 at 11:07, Michael S. Tsirkin m...@redhat.com wrote:
On
Reproducer:
$ qemu-system-x86_64 -nodefaults -device virtio-rng-pci -device
virtio-rng-pci -device virtio-rng-device,bus=virtio-bus
qemu-system-x86_64: -device virtio-rng-device,bus=virtio-bus: Bus
'virtio-bus' is full
qemu-system-x86_64: -device virtio-rng-device,bus=virtio-bus:
Also polish an error message while I'm touching the line anyway,
Signed-off-by: Markus Armbruster arm...@redhat.com
Reviewed-by: Eric Blake ebl...@redhat.com
Reviewed-by: Andreas Färber afaer...@suse.de
---
include/monitor/qdev.h | 2 +-
qdev-monitor.c | 36
Property bus has always been too screwed up to be really usable for
values other than plain bus IDs. This just fixes a bug that crept in
in commit 1395af6 qdev: add a maximum device allowed field for the
bus.
It doesn't always fail when it should:
$ qemu-system-x86_64 -nodefaults -device
On 19 June 2015 at 11:19, Michael S. Tsirkin m...@redhat.com wrote:
On Fri, Jun 19, 2015 at 09:32:48AM +0100, Peter Maydell wrote:
On 19 June 2015 at 08:30, Michael S. Tsirkin m...@redhat.com wrote:
They are trivial - a single patch on top that adds stubs for missing
platforms. And I think
From assert(3): assert() is implemented as a macro; if the expression tested
has side-effects, program behavior will be different depending on whether
NDEBUG is defined.
Even if QEMU isn't compiled with NDEBUG, it is bad practice to put bits
with a relevant functionnal meaning in assert().
This
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