On Fri, Jul 24, 2015 at 04:21:01PM +0100, Peter Maydell wrote:
> Some coprocessor register access functions need to be able
> to report "trap to EL3 with an 'uncategorized' syndrome";
> add the necessary CPAccessResult enum and handling for it.
>
> I don't currently know of any registers that need
Oh, it has been fixed, but did not merge into master branch.
commit b9b331a737f2cd34614355cc8facbbc49fc9816d
Author: Richard Henderson
Date: Fri Jan 29 15:28:51 2010 -0800
tcg-alpha: Fix type mismatch errors in cpu_signal_handler.
Signed-off-by: Richard Henderson
diff --git a/user-
On Fri, Jul 24, 2015 at 04:21:00PM +0100, Peter Maydell wrote:
> Wire up the AArch64 EL2 and EL3 address translation operations
> (AT S12E1*, AT S12E0*, AT S1E2*, AT S1E3*), and correct some
> errors in the ats_write64() function in previously unused code
> that would have done the wrong kind of lo
On Fri, Jul 24, 2015 at 04:20:59PM +0100, Peter Maydell wrote:
> For EL2 stage 1 translations, there is no TTBR1. We were already
> handling this for 64-bit EL2; add the code to take the 'no TTBR1'
> code path for 64-bit EL2 as well.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesia
On 16/08/15 09:28, Peter Crosthwaite wrote:
> From: Peter Crosthwaite
>
> The only generic code relying on this is linux-user, but linux users'
> default behaviour of defaulting ELF_MACHINE to ELF_ARCH will handle
> this.
>
> The machine model bootloaders can just pass EM_68K directly, as that
>
Am 2015-08-16 01:28, schrieb Peter Crosthwaite:
From: Peter Crosthwaite
The bootloaders can just pass EM_LATTICEMICO32 directly, as that is
architecture specific code.
This removes another architecture specific definition from the global
namespace.
Cc: Michael Walle
Signed-off-by: Peter Cros
On Thu, Jul 30, 2015 at 07:36:38PM +0100, Peter Maydell wrote:
> We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and
> ACTLR_EL3, for consistency.
>
> Since we don't currently have any CPUs that need the EL2/EL3
> versions to reset to non-zero values, implement as RAZ/WI.
>
> Signed-o
On Thu, Jul 30, 2015 at 07:36:37PM +0100, Peter Maydell wrote:
> The AFSR registers are implementation dependent auxiliary fault
> status registers. We already implemented a RAZ/WI AFSR0_EL1 and
> AFSR_EL1; add the missing AFSR{0,1}_EL{2,3} for consistency.
>
> Signed-off-by: Peter Maydell
Revie
On Thu, Jul 30, 2015 at 07:36:36PM +0100, Peter Maydell wrote:
> The AMAIR registers are for providing auxiliary implementation
> defined memory attributes. We already implemented a RAZ/WI
> AMAIR_EL1; add the EL2 and EL3 versions for consistency.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Ed
On Thu, Jul 30, 2015 at 07:36:35PM +0100, Peter Maydell wrote:
> Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only
> two which we had implemented the 32-bit Secure equivalents of but
> not the 64-bit Secure versions.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Igles
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